diff --git a/src/chipset/chipset.h b/src/chipset/chipset.h index 057df0cdb..da4942c99 100644 --- a/src/chipset/chipset.h +++ b/src/chipset/chipset.h @@ -66,6 +66,7 @@ extern const device_t sis_85c50x_device; /* VIA */ extern const device_t via_mvp3_device; +extern const device_t via_apro_device; /* VLSI */ extern const device_t vlsi_scamp_device; diff --git a/src/chipset/via_apro.c b/src/chipset/via_apro.c new file mode 100644 index 000000000..573f18df8 --- /dev/null +++ b/src/chipset/via_apro.c @@ -0,0 +1,345 @@ +/* + + 86Box A hypervisor and IBM PC system emulator that specializes in + running old operating systems and software designed for IBM + PC systems and compatibles from 1981 through fairly recent + system designs based on the PCI bus. + + + +VIA Apollo Pro North Bridge emulation + +VT82C691 used in the PC Partner APAS3 board +based on the model of VIA MVP3 by mooch & Sarah + +Authors: Sarah Walker, +Copyright(C) 2020 Tiseno100 +Copyright(C) 2020 Melissa Goad +Copyright(C) 2020 Miran Grca + + +Note: Due to 99.9% similarities with the VP3, MVP3 but also other later Apollo chipsets. We probably should create a common Apollo tree +just like the Intel 4x0 series. + +*/ + +#include +#include +#include +#include +#include +#include "86box.h" +#include "mem.h" +#include "86box_io.h" +#include "rom.h" +#include "pci.h" +#include "device.h" +#include "keyboard.h" +#include "chipset.h" + +typedef struct via_apro_t +{ + uint8_t pci_conf[2][256]; +} via_apro_t; + +static void +apro_map(uint32_t addr, uint32_t size, int state) +{ + switch (state & 3) { + case 0: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 1: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 2: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 3: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + } + + flushmmucache_nopc(); +} + +static void +via_apro_pci_regs(via_apro_t *dev) +{ + memset(dev, 0, sizeof(via_apro_t)); + +// Host Bridge registers + + dev->pci_conf[0][0x00] = 0x06; // VIA + dev->pci_conf[0][0x01] = 0x11; + + dev->pci_conf[0][0x02] = 0x91; // VT82C691 + dev->pci_conf[0][0x03] = 0x06; + + dev->pci_conf[0][0x04] = 6; // Command + dev->pci_conf[0][0x05] = 0; + +// These(06h-0fh) probably aren't needed but as they're referenced by the MVP3 chipset code i added them too + + dev->pci_conf[0][0x06] = 0; // Status + dev->pci_conf[0][0x07] = 0; + + dev->pci_conf[0][0x09] = 0; // Program Interface + + dev->pci_conf[0][0x0a] = 0; // Sub Class Code + + dev->pci_conf[0][0x0b] = 0; // Base Class Code + + dev->pci_conf[0][0x0c] = 0; // reserved + + dev->pci_conf[0][0x0d] = 0; // Latency Timer + + dev->pci_conf[0][0x0e] = 0; // Header Type + + dev->pci_conf[0][0x0f] = 0; // Built-in Self test + + dev->pci_conf[0][0x10] = 0x08; // Graphics Aperature Base + + dev->pci_conf[0][0x34] = 0xa0; // Capability Pointer + + dev->pci_conf[0][0x56] = 1; // Bank 6 Ending + dev->pci_conf[0][0x57] = 1; // Bank 7 Ending + dev->pci_conf[0][0x5a] = 1; // Bank 0 Ending + dev->pci_conf[0][0x5b] = 1; // Bank 1 Ending + dev->pci_conf[0][0x5c] = 1; // Bank 2 Ending + dev->pci_conf[0][0x5d] = 1; // Bank 3 Ending + dev->pci_conf[0][0x5e] = 1; // Bank 4 Ending + dev->pci_conf[0][0x5f] = 1; // Bank 5 Ending + + dev->pci_conf[0][0x64] = 0xec; // DRAM Timing for Banks 0,1 + dev->pci_conf[0][0x65] = 0xec; // DRAM Timing for Banks 2,3 + dev->pci_conf[0][0x66] = 0xec; // DRAM Timing for Banks 4,5 + dev->pci_conf[0][0x67] = 0x01; // DRAM Timing for Banks 6,7 + + dev->pci_conf[0][0x6b] = 1; // DRAM Abritration control + + dev->pci_conf[0][0xa4] = 0x03; // AGP Status + dev->pci_conf[0][0xa5] = 0x02; + dev->pci_conf[0][0xa6] = 0; + dev->pci_conf[0][0xa7] = 0x07; + +// PCI-to-PCI + + dev->pci_conf[1][0x00] = 0x06; // VIA + dev->pci_conf[1][0x01] = 0x11; + + dev->pci_conf[1][0x02] = 0x91; // VT82C691 + dev->pci_conf[1][0x03] = 0x06; + + dev->pci_conf[1][0x04] = 7; // Command + dev->pci_conf[1][0x05] = 0; + + dev->pci_conf[1][0x06] = 0x20; // Status + dev->pci_conf[1][0x07] = 0x02; + + dev->pci_conf[1][0x09] = 0; // Program Interface + + dev->pci_conf[1][0x0A] = 4; // Sub Class Code + + dev->pci_conf[1][0x0B] = 6; // Base Class Code + + dev->pci_conf[1][0x0C] = 0; // reserved + + dev->pci_conf[1][0x0D] = 0; // Latency Timer + + dev->pci_conf[1][0x0E] = 1; // Header Type + + dev->pci_conf[1][0x0F] = 0; // Built-in Self test + + dev->pci_conf[1][0x1c] = 0xf0; // I/O Base + + dev->pci_conf[1][0x20] = 0xf0; // Memory Base + dev->pci_conf[1][0x21] = 0xff; + dev->pci_conf[1][0x24] = 0xf0; + dev->pci_conf[1][0x25] = 0xff; + +} + +static void +host_bridge_write(int func, int addr, uint8_t val, void *priv) +{ + +via_apro_t *dev = (via_apro_t *) priv; + + // Read-Only registers. Exact same as MVP3 + if ((addr < 4) || ((addr >= 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) || ((addr >= 0xe) && (addr < 0x12)) || + ((addr >= 0x14) && (addr < 0x50)) || ((addr >= 0x79) && (addr < 0x7e)) || ((addr >= 0x85) && (addr < 0x88)) || + ((addr >= 0x8c) && (addr < 0xa8)) || ((addr >= 0xad) && (addr < 0xfd))) + return; + + switch(addr){ + case 0x04: // Command + dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40); + + case 0x07: // Status + dev->pci_conf[0][0x07] &= ~(val & 0xb0); + break; + + case 0x12: //Graphics Aperature Base + dev->pci_conf[0][0x12] = (val & 0xf0); + break; + case 0x13: + dev->pci_conf[0][0x13] = val; + break; + + case 0x61: // Shadow RAM control 1 + if ((dev->pci_conf[0][0x61] ^ val) & 0x03) + apro_map(0xc0000, 0x04000, val & 0x03); + if ((dev->pci_conf[0][0x61] ^ val) & 0x0c) + apro_map(0xc4000, 0x04000, (val & 0x0c) >> 2); + if ((dev->pci_conf[0][0x61] ^ val) & 0x30) + apro_map(0xc8000, 0x04000, (val & 0x30) >> 4); + if ((dev->pci_conf[0][0x61] ^ val) & 0xc0) + apro_map(0xcc000, 0x04000, (val & 0xc0) >> 6); + dev->pci_conf[0][0x61] = val; + return; + + case 0x62: // Shadow RAM Control 2 + if ((dev->pci_conf[0][0x62] ^ val) & 0x03) + apro_map(0xd0000, 0x04000, val & 0x03); + if ((dev->pci_conf[0][0x62] ^ val) & 0x0c) + apro_map(0xd4000, 0x04000, (val & 0x0c) >> 2); + if ((dev->pci_conf[0][0x62] ^ val) & 0x30) + apro_map(0xd8000, 0x04000, (val & 0x30) >> 4); + if ((dev->pci_conf[0][0x62] ^ val) & 0xc0) + apro_map(0xdc000, 0x04000, (val & 0xc0) >> 6); + dev->pci_conf[0][0x62] = val; + return; + + case 0x63: // Shadow RAM Control 3 + if ((dev->pci_conf[0][0x63] ^ val) & 0x30) { + apro_map(0xf0000, 0x10000, (val & 0x30) >> 4); + shadowbios = (((val & 0x30) >> 4) & 0x02); + } + if ((dev->pci_conf[0][0x63] ^ val) & 0xc0) + apro_map(0xe0000, 0x10000, (val & 0xc0) >> 6); + dev->pci_conf[0][0x63] = val; + return; + + //In case we throw somewhere + default: + dev->pci_conf[0][addr] = val; + break; + } +} + +static void +pci_to_pci_bridge_write(int func, int addr, uint8_t val, void *priv) +{ + via_apro_t *dev = (via_apro_t *) priv; + + if (func != 1) + return; + + //As with MVP3. Same deal + if ((addr < 4) || ((addr >= 5) && (addr < 7)) || + ((addr >= 8) && (addr < 0x18)) || (addr == 0x1b) || + ((addr >= 0x1e) && (addr < 0x20)) || ((addr >= 0x28) && (addr < 0x3e)) || + (addr >= 0x43)) + return; + + switch(addr) { + case 0x04: + dev->pci_conf[1][0x04] = (dev->pci_conf[1][0x04] & ~0x47) | (val & 0x47); + break; + case 0x07: + dev->pci_conf[1][0x07] &= ~(val & 0x30); + break; + + case 0x20: // Memory Base + dev->pci_conf[1][0x20] = val & 0xf0; + break; + + case 0x22: // Memory Limit + dev->pci_conf[1][0x22] = val & 0xf0; + break; + + case 0x24: // Prefetchable Memory base + dev->pci_conf[1][0x24] = val & 0xf0; + break; + + case 0x26: // Prefetchable Memory limit + dev->pci_conf[1][0x26] = val & 0xf0; + break; + + default: + dev->pci_conf[1][addr] = val; + break; + } +} + +static uint8_t +via_apro_read(int func, int addr, void *priv) +{ + via_apro_t *dev = (via_apro_t *) priv; + uint8_t ret = 0xff; + + switch(func) { + case 0: + ret = dev->pci_conf[0][addr]; + break; + case 1: + ret = dev->pci_conf[1][addr]; + break; + } + + return ret; +} + +static void +via_apro_write(int func, int addr, uint8_t val, void *priv) +{ + switch(func) { + case 0: + host_bridge_write(func, addr, val, priv); + break; + + case 1: + pci_to_pci_bridge_write(func, addr, val, priv); + break; + } +} + +static void +via_apro_reset(void *priv) +{ + via_apro_write(0, 0x63, via_apro_read(0, 0x63, priv) & 0xcf, priv); +} + +static void * +via_apro_init(const device_t *info) +{ + via_apro_t *dev = (via_apro_t *) malloc(sizeof(via_apro_t)); + + pci_add_card(PCI_ADD_NORTHBRIDGE, via_apro_read, via_apro_write, dev); + + via_apro_pci_regs(dev); + + return dev; +} + +static void +via_apro_close(void *priv) +{ + via_apro_t *dev = (via_apro_t *) priv; + + free(dev); +} + +const device_t via_apro_device = { + "VIA Apollo Pro", + DEVICE_PCI, + 0, + via_apro_init, + via_apro_close, + via_apro_reset, + NULL, + NULL, + NULL, + NULL +}; \ No newline at end of file diff --git a/src/cpu_common/cpu_table.c b/src/cpu_common/cpu_table.c index d13877db7..46289be47 100644 --- a/src/cpu_common/cpu_table.c +++ b/src/cpu_common/cpu_table.c @@ -723,8 +723,16 @@ CPU cpus_Celeron[] = { // Mendocino Celerons. Exact architecture as the P2D seri // The 100Mhz Mendocino is only meant to not cause any struggle // to the recompiler. - {"Celeron Mendocino 100", CPU_PENTIUM2D, 100000000, 3/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Celeron Mendocino 66", CPU_PENTIUM2D, 66666666, 1, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, + {"Celeron Mendocino 100", CPU_PENTIUM2D, 100000000, 3/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Celeron Mendocino 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, {"Celeron Mendocino 333", CPU_PENTIUM2D, 333333333, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, + {"Celeron Mendocino 366", CPU_PENTIUM2D, 366666666, 11/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33,17,17, 44}, + {"Celeron Mendocino 400", CPU_PENTIUM2D, 400000000, 4, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, + {"Celeron Mendocino 433", CPU_PENTIUM2D, 433333333, 9/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 39,39,13,13, 51}, + {"Celeron Mendocino 466", CPU_PENTIUM2D, 466666666, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43,43,15,15, 57}, + {"Celeron Mendocino 500", CPU_PENTIUM2D, 500000000, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45,45,15,15, 60}, + {"Celeron Mendocino 533", CPU_PENTIUM2D, 533333333, 11/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48,48,17,17, 64}, {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }; #endif @@ -745,4 +753,4 @@ CPU cpus_Cyrix3[] = { {"Cyrix III 650", CPU_CYRIX3S, 650000000, 6.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78}, {"Cyrix III 700", CPU_CYRIX3S, 700000000, 7, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84}, {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; \ No newline at end of file +}; diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c index 3601093cc..372778712 100644 --- a/src/machine/m_at_socket7_s7.c +++ b/src/machine/m_at_socket7_s7.c @@ -489,6 +489,34 @@ machine_at_j656vxd_init(const machine_t *model) return ret; } +int +machine_at_mb520n_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/mb520n/520n503s.rom", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + device_add(&i430vx_device); + device_add(&piix3_device); + device_add(&keyboard_ps2_pci_device); + device_add(&fdc37c669_device); + device_add(&sst_flash_29ee010_device); + + return ret; +} int diff --git a/src/machine/m_at_socket8.c b/src/machine/m_at_socket8.c index 32a4ec981..5dc9ae6cd 100644 --- a/src/machine/m_at_socket8.c +++ b/src/machine/m_at_socket8.c @@ -30,6 +30,7 @@ #include "hdc_ide.h" #include "keyboard.h" #include "intel_flash.h" +#include "via_vt82c586b.h" #include "intel_sio.h" #include "piix.h" #include "sio.h" @@ -237,13 +238,13 @@ machine_at_borapro_init(const machine_t *model) return ret; } -#if defined(DEV_BRANCH) && defined(USE_I686) + int -machine_at_p6bxt_init(const machine_t *model) +machine_at_apas3_init(const machine_t *model) { int ret; - ret = bios_load_linear(L"roms/machines/p6bxt/bxt53s.BIN", + ret = bios_load_linear(L"roms/machines/apas3/V0218SAG.BIN", 0x000c0000, 262144, 0); if (bios_only || !ret) @@ -253,23 +254,21 @@ machine_at_p6bxt_init(const machine_t *model) pci_init(PCI_CONFIG_TYPE_1); pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 3, 2, 1); /* Slot 5: Probably the integrated sound chip. */ + pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3); pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440bx_device); - device_add(&piix4e_device); - device_add(&w83977tf_device); + device_add(&via_apro_device); + device_add(&via_vt82c586b_device); + device_add(&fdc37c669_device); device_add(&keyboard_ps2_pci_device); device_add(&sst_flash_39sf020_device); spd_register(SPD_TYPE_SDRAM, 0x7, 256); return ret; } -#endif int machine_at_63a_init(const machine_t *model) @@ -304,4 +303,4 @@ machine_at_63a_init(const machine_t *model) spd_register(SPD_TYPE_SDRAM, 0x3, 256); return ret; -} +} \ No newline at end of file diff --git a/src/machine/machine.h b/src/machine/machine.h index ed4180989..bce64b60e 100644 --- a/src/machine/machine.h +++ b/src/machine/machine.h @@ -292,6 +292,7 @@ extern int machine_at_p55tvp4_init(const machine_t *); extern int machine_at_i430vx_init(const machine_t *); extern int machine_at_p55va_init(const machine_t *); extern int machine_at_j656vxd_init(const machine_t *); +extern int machine_at_mb520n_init(const machine_t *); extern int machine_at_p55xb2_init(const machine_t *); extern int machine_at_tx97_init(const machine_t *); @@ -301,6 +302,7 @@ extern int machine_at_807ds_init(const machine_t *); extern int machine_at_mvp3_init(const machine_t *); + #ifdef EMU_DEVICE_H extern const device_t *at_pb640_get_device(void); #endif @@ -309,13 +311,13 @@ extern const device_t *at_pb640_get_device(void); #if defined(DEV_BRANCH) && defined(USE_I686) extern int machine_at_i440fx_init(const machine_t *); extern int machine_at_s1668_init(const machine_t *); -extern int machine_at_p6bxt_init(const machine_t *); /*BIOS doesn't work correctly with VIA C3*/ #endif extern int machine_at_6abx3_init(const machine_t *); extern int machine_at_p2bls_init(const machine_t *); extern int machine_at_borapro_init(const machine_t *); extern int machine_at_63a_init(const machine_t *); +extern int machine_at_apas3_init(const machine_t *); /* m_at_t3100e.c */ extern int machine_at_t3100e_init(const machine_t *); diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 9765f334c..d20a8ba12 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -223,8 +223,9 @@ const machine_t machines[] = { { "[Socket 7 VX] ASUS P/I-P55TVP4", "p55tvp4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55tvp4_init, NULL }, { "[Socket 7 VX] Epox P55-VA", "p55va", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL }, { "[Socket 7 VX] Jetway J656VXD", "j656vxd", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_j656vxd_init, NULL }, + { "[Socket 7 VX] PC Partner MB520N", "mb520n", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_mb520n_init, NULL }, { "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL }, - + { "[Socket 7 TX] ASUS TX97", "txp4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_tx97_init, NULL }, { "[Socket 7 TX] Gigabyte GA-586T2", "586t2", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_586t2_init, NULL }, { "[Socket 7 TX] Intel YM430TX", "ym430tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_ym430tx_init, NULL }, @@ -244,14 +245,15 @@ const machine_t machines[] = { { "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL }, #endif #if defined(DEV_BRANCH) && defined(USE_I686) - { "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL }, + { "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL }, - { "[Socket 370 BX] ECS P6BXT-A+", "p6bxt", {{"Intel", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_p6bxt_init, NULL }, { "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL }, + { "[Socket 370 APRO] PC Partner APAS3", "apas3", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_apas3_init, NULL }, #else - { "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL }, + { "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL }, { "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL }, + { "[Socket 370 APRO] PC Partner APAS3", "apas3", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_apas3_init, NULL }, #endif { NULL, NULL, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL } diff --git a/src/smbus.c b/src/smbus.c index b436be703..4b2ac8c59 100644 --- a/src/smbus.c +++ b/src/smbus.c @@ -48,7 +48,7 @@ typedef struct _smbus_ { int smbus_initialized = 0; smbus_t *smbus[NADDRS], *smbus_last[NADDRS]; -#define ENABLE_SMBUS_LOG 1 + #ifdef ENABLE_SMBUS_LOG int smbus_do_log = ENABLE_SMBUS_LOG; diff --git a/src/spd.c b/src/spd.c index b0d3ca2bd..a4abca624 100644 --- a/src/spd.c +++ b/src/spd.c @@ -48,7 +48,6 @@ static uint8_t spd_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv); static void spd_write_byte(uint8_t addr, uint8_t val, void *priv); -#define ENABLE_SPD_LOG 1 #ifdef ENABLE_SPD_LOG int spd_do_log = ENABLE_SPD_LOG; @@ -153,13 +152,13 @@ void spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) { uint8_t slot, slot_count, vslot, next_empty_vslot, i, split; - uint16_t min_size, total_size, vslots[SPD_MAX_SLOTS]; + uint16_t min_module_size, total_size, vslots[SPD_MAX_SLOTS]; spd_sdram_t *sdram_data; /* determine the minimum module size for this RAM type */ switch (ram_type) { case SPD_TYPE_SDRAM: - min_size = SPD_MIN_SIZE_SDRAM; + min_module_size = SPD_MIN_SIZE_SDRAM; break; default: @@ -177,12 +176,16 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) } /* populate vslots with modules in power-of-2 capacities */ - total_size = mem_size / 1024; + total_size = (mem_size >> 10); for (vslot = 0; vslot < slot_count && total_size; vslot++) { /* populate slot */ vslots[vslot] = (1 << log2_ui16(MIN(total_size, max_module_size))); - spd_log("SPD: assigning %d MB to vslot %d\n", vslots[vslot], vslot); - total_size -= vslots[vslot]; + if (total_size >= vslots[vslot]) { + spd_log("SPD: vslot %d = %d MB\n", vslot, vslots[vslot]); + total_size -= vslots[vslot]; + } else { + break; + } } if (total_size > 0) /* did we populate everything? */ @@ -194,7 +197,7 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) /* look for a module to split */ split = 0; for (vslot = 0; vslot < slot_count; vslot++) { - if (vslots[vslot] < (min_size * 2)) + if (vslots[vslot] < (min_module_size << 1)) continue; /* no module here or module is too small to be split */ /* find next empty vslot */ @@ -207,8 +210,8 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) break; /* no empty vslots left */ /* split the module into its own vslot and the next empty vslot */ - spd_log("SPD: splitting vslot %d (%d MB) into %d and %d (%d MB each)\n", vslot, vslots[vslot], vslot, next_empty_vslot, vslots[vslot] >> 1); - vslots[vslot] = vslots[next_empty_vslot] = vslots[vslot] >> 1; + spd_log("SPD: splitting vslot %d (%d MB) into %d and %d (%d MB each)\n", vslot, vslots[vslot], vslot, next_empty_vslot, (vslots[vslot] >> 1)); + vslots[vslot] = vslots[next_empty_vslot] = (vslots[vslot] >> 1); split = 1; } @@ -219,14 +222,11 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) /* register SPD devices and populate their data according to the vslots */ vslot = 0; - for (slot = 0; slot < SPD_MAX_SLOTS; slot++) { + for (slot = 0; slot < SPD_MAX_SLOTS && vslots[vslot]; slot++) { if (!(slot_mask & (1 << slot))) continue; /* slot disabled */ - if (!vslots[vslot]) - break; /* no slots left to fill */ - - spd_log("SPD: registering slot %d = %d MB\n", slot, vslots[vslot]); + spd_log("SPD: registering slot %d = vslot %d = %d MB\n", slot, vslot, vslots[vslot]); spd_devices[slot] = (device_t *)malloc(sizeof(device_t)); memset(spd_devices[slot], 0, sizeof(device_t)); @@ -249,7 +249,8 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) sdram_data->data_width_lsb = 64; sdram_data->data_width_msb = 0; sdram_data->signal_level = SPD_SDR_SIGNAL_LVTTL; - sdram_data->tclk = sdram_data->tac = 0x10; + sdram_data->tclk = 0x75; /* 7.5 ns = 133.3 MHz */ + sdram_data->tac = 0x10; sdram_data->config = 0; sdram_data->refresh_rate = SPD_SDR_REFRESH_SELF | SPD_SDR_REFRESH_NORMAL; sdram_data->sdram_width = 8; @@ -258,15 +259,19 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) sdram_data->banks = 4; sdram_data->cas = sdram_data->cs = sdram_data->we = 0x7F; sdram_data->dev_attr = SPD_SDR_ATTR_EARLY_RAS | SPD_SDR_ATTR_AUTO_PC | SPD_SDR_ATTR_PC_ALL | SPD_SDR_ATTR_W1R_BURST; - sdram_data->tclk2 = sdram_data->tac2 = 0x10; + sdram_data->tclk2 = 0xA0; /* 10 ns = 100 MHz */ + sdram_data->tclk3 = 0xF0; /* 15 ns = 66.7 MHz */ + sdram_data->tac2 = sdram_data->tac3 = 0x10; sdram_data->trp = sdram_data->trrd = sdram_data->trcd = sdram_data->tras = 1; sdram_data->bank_density = 1 << (log2_ui16(vslots[vslot] >> 1) - 2); sdram_data->ca_setup = sdram_data->data_setup = 0x15; sdram_data->ca_hold = sdram_data->data_hold = 0x08; sdram_data->spd_rev = 0x12; sprintf(sdram_data->part_no, "86Box-SDR-%03dM", vslots[vslot]); + for (i = strlen(sdram_data->part_no); i < sizeof(sdram_data->part_no); i++) + sdram_data->part_no[i] = ' '; sdram_data->mfg_year = 0x20; - sdram_data->mfg_week = 0x01; + sdram_data->mfg_week = 0x13; sdram_data->freq = 100; sdram_data->features = 0xFF; diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index 50bcdafdb..95a55517a 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -575,7 +575,7 @@ CPUOBJ := cpu.o cpu_table.o \ CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \ intel_4x0.o neat.o opti495.o scamp.o scat.o \ sis_85c471.o sis_85c496.o \ - via_mvp3.o wd76c10.o + via_mvp3.o via_apro.o wd76c10.o MCHOBJ := machine.o machine_table.o \ m_xt.o m_xt_compaq.o \ diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index 9ffecdc3c..b2f6d81e8 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -580,7 +580,7 @@ CPUOBJ := cpu.o cpu_table.o \ CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \ intel_4x0.o neat.o opti495.o scamp.o scat.o \ sis_85c471.o sis_85c496.o \ - via_mvp3.o wd76c10.o + via_mvp3.o via_apro.o wd76c10.o MCHOBJ := machine.o machine_table.o \ m_xt.o m_xt_compaq.o \