diff --git a/src/chipset/sis_85c496.c b/src/chipset/sis_85c496.c
index 1e9b74f41..3c3d5bd8c 100644
--- a/src/chipset/sis_85c496.c
+++ b/src/chipset/sis_85c496.c
@@ -388,8 +388,7 @@ sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
             break;
         case 0x67: /* Miscellaneous Control */
             dev->pci_conf[addr] = val & 0xf9;
-            if (valxor & 0x60)
-                port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40));
+            cpu_cpurst_on_sr = ((val & 0xa0) == 0x80) && !(dev->pci_conf[0xc6] & 0x08);
             break;
 
         /* 86C497 Specific Registers (80h ~ FFh) */
@@ -480,7 +479,7 @@ sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
             break;
         case 0xc6: /* 85C497 Post / INIT Configuration */
             dev->pci_conf[addr] = val & 0x0f;
-            cpu_cpurst_on_sr = !(val & 0x08);
+            cpu_cpurst_on_sr = ((dev->pci_conf[0x67] & 0xa0) == 0x80) && !(val & 0x08);
             soft_reset_pci = !!(val & 0x04);
             break;
         case 0xc8:
@@ -610,6 +609,9 @@ sis_85c496_reset(void *priv)
     sis_85c49x_pci_write(0, 0xd0, 0x78, dev);
     sis_85c49x_pci_write(0, 0xd4, 0x00, dev);
 
+    dev->pci_conf[0x67] = 0x00;
+    dev->pci_conf[0xc6] = 0x00;
+
     ide_pri_disable();
     ide_sec_disable();
 
@@ -617,7 +619,7 @@ sis_85c496_reset(void *priv)
 
     sis_85c497_isa_reset(dev);
 
-    cpu_cpurst_on_sr = 1;
+    cpu_cpurst_on_sr = 0;
     soft_reset_pci = 0;
 }