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Seperated the UMC 8886, Added the UMC 8890

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This commit is contained in:
Panagiotis
2021-03-25 11:01:54 +02:00
committed by GitHub
parent 7b22fa60d1
commit 050c16424c
9 changed files with 501 additions and 177 deletions
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3
src/chipset/CMakeLists.txt
View File

@@ -16,7 +16,8 @@
add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c headland.c intel_82335.c
cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c ../ioapic.c
neat.c opti283.c opti291.c opti495.c opti895.c opti5x7.c scamp.c scat.c
sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c umc_hb4.c
sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c
umc_8886.c umc_8890.c umc_hb4.c
via_vt82c49x.c via_vt82c505.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c
gc100.c olivetti_eva.c stpc.c
via_apollo.c via_pipc.c wd76c10.c

271
src/chipset/umc_8886.c Normal file
View File

@@ -0,0 +1,271 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the UMC 8886xx PCI to ISA Bridge .
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
*
* Authors: Tiseno100,
*
* Copyright 2021 Tiseno100.
*/
/*
UMC 8886 Configuration Registers
TODO:
- More Appropriate Bitmasking(If it's even possible)
Warning: Register documentation may be inaccurate!
UMC 8886xx:
(F: Has No Internal IDE / AF or BF: Has Internal IDE)
Function 0 Register 43:
Bits 7-4 PCI IRQ for INTB
Bits 3-0 PCI IRQ for INTA
Function 0 Register 44:
Bits 7-4 PCI IRQ for INTD
Bits 3-0 PCI IRQ for INTC
Function 0 Register 46:
Bit 7: Replace SMI request for non-SMM CPU's (1: IRQ15/0: IRQ10)
Function 0 Register 51:
Bit 2: VGA Power Down (0: Standard/1: VESA DPMS)
Function 1 Register 4:
Bit 0: Enable Internal IDE
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/pci.h>
#include <86box/chipset.h>
#ifdef ENABLE_UMC_8886_LOG
int umc_8886_do_log = ENABLE_UMC_8886_LOG;
static void
umc_8886_log(const char *fmt, ...)
{
va_list ap;
if (umc_8886_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define umc_8886_log(fmt, ...)
#endif
/* PCI IRQ Flags */
#define INTA (PCI_INTA + (2 * !(addr & 1)))
#define INTB (PCI_INTB + (2 * !(addr & 1)))
#define IRQRECALCA (((val & 0xf0) != 0) ? ((val & 0xf0) >> 4) : PCI_IRQ_DISABLED)
#define IRQRECALCB (((val & 0x0f) != 0) ? (val & 0x0f) : PCI_IRQ_DISABLED)
/* Disable Internal IDE Flag needed for the BF Southbridge variant */
#define HAS_IDE dev->has_ide
/* Southbridge Revision */
#define SB_ID dev->sb_id
typedef struct umc_8886_t
{
uint8_t pci_conf_sb[2][256]; /* PCI Registers */
uint16_t sb_id; /* Southbridge Revision */
int has_ide; /* Check if Southbridge Revision is AF or F */
} umc_8886_t;
void umc_8886_ide_handler(int status)
{
ide_pri_disable();
ide_sec_disable();
if (status)
{
ide_pri_enable();
ide_sec_enable();
}
}
static void
um8886_write(int func, int addr, uint8_t val, void *priv)
{
umc_8886_t *dev = (umc_8886_t *)priv;
umc_8886_log("UM8886: dev->regs[%02x] = %02x (%02x)\n", addr, val, func);
if (addr > 3) /* We don't know the RW status of registers but Phoenix writes on some RO registers too*/
switch (func)
{
case 0: /* Southbridge */
switch (addr)
{
case 0x43:
case 0x44:
dev->pci_conf_sb[func][addr] = val;
pci_set_irq_routing(INTA, IRQRECALCA);
pci_set_irq_routing(INTB, IRQRECALCB);
break;
case 0x46:
dev->pci_conf_sb[func][addr] = val & 0xaf;
break;
case 0x47:
dev->pci_conf_sb[func][addr] = val & 0x4f;
break;
case 0x57:
dev->pci_conf_sb[func][addr] = val & 0x38;
break;
case 0x71:
dev->pci_conf_sb[func][addr] = val & 1;
break;
case 0x90:
dev->pci_conf_sb[func][addr] = val & 2;
break;
case 0x92:
dev->pci_conf_sb[func][addr] = val & 0x1f;
break;
case 0xa0:
dev->pci_conf_sb[func][addr] = val & 0xfc;
break;
case 0xa4:
dev->pci_conf_sb[func][addr] = val & 0x88;
break;
default:
dev->pci_conf_sb[func][addr] = val;
break;
}
break;
case 1: /* IDE Controller */
dev->pci_conf_sb[func][addr] = val;
if ((addr == 4) && HAS_IDE)
umc_8886_ide_handler(val & 1);
break;
}
}
static uint8_t
um8886_read(int func, int addr, void *priv)
{
umc_8886_t *dev = (umc_8886_t *)priv;
return dev->pci_conf_sb[func][addr];
}
static void
umc_8886_reset(void *priv)
{
umc_8886_t *dev = (umc_8886_t *)priv;
/* Defaults */
dev->pci_conf_sb[0][0] = 0x60; /* UMC */
dev->pci_conf_sb[0][1] = 0x10;
dev->pci_conf_sb[0][2] = (SB_ID & 0xff); /* 8886xx */
dev->pci_conf_sb[0][3] = ((SB_ID >> 8) & 0xff);
dev->pci_conf_sb[0][8] = 1;
dev->pci_conf_sb[0][0x09] = 0x00;
dev->pci_conf_sb[0][0x0a] = 0x01;
dev->pci_conf_sb[0][0x0b] = 0x06;
for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */
pci_set_irq_routing(i, PCI_IRQ_DISABLED);
if (HAS_IDE)
{
dev->pci_conf_sb[1][4] = 1; /* Start with Internal IDE Enabled */
umc_8886_ide_handler(1);
}
}
static void
umc_8886_close(void *priv)
{
umc_8886_t *dev = (umc_8886_t *)priv;
free(dev);
}
static void *
umc_8886_init(const device_t *info)
{
umc_8886_t *dev = (umc_8886_t *)malloc(sizeof(umc_8886_t));
memset(dev, 0, sizeof(umc_8886_t));
dev->has_ide = (info->local && 0x886a);
pci_add_card(PCI_ADD_SOUTHBRIDGE, um8886_read, um8886_write, dev); /* Device 12: UMC 8886xx */
/* Add IDE if UM8886AF variant */
if (HAS_IDE)
device_add(&ide_pci_2ch_device);
/* Get the Southbridge Revision */
SB_ID = info->local;
umc_8886_reset(dev);
return dev;
}
const device_t umc_8886f_device = {
"UMC 8886F",
DEVICE_PCI,
0x8886,
umc_8886_init,
umc_8886_close,
umc_8886_reset,
{NULL},
NULL,
NULL,
NULL};
const device_t umc_8886af_device = {
"UMC 8886AF",
DEVICE_PCI,
0x886a,
umc_8886_init,
umc_8886_close,
umc_8886_reset,
{NULL},
NULL,
NULL,
NULL};

180
src/chipset/umc_8890.c Normal file
View File

@@ -0,0 +1,180 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the UMC 8890 Chipset.
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
*
* Authors: Tiseno100,
*
* Copyright 2021 Tiseno100.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/apm.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#ifdef ENABLE_UMC_8890_LOG
int umc_8890_do_log = ENABLE_UMC_8890_LOG;
static void
umc_8890_log(const char *fmt, ...)
{
va_list ap;
if (umc_8890_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define umc_8890_log(fmt, ...)
#endif
/* Shadow RAM Flags */
#define ENABLE_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)
#define DISABLE_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
typedef struct umc_8890_t
{
apm_t *apm;
smram_t *smram;
uint8_t pci_conf[256];
} umc_8890_t;
uint16_t umc_8890_shadow_flag(uint8_t flag)
{
return (flag & 1) ? (MEM_READ_INTERNAL | ((flag & 2) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
void umc_8890_shadow(umc_8890_t *dev)
{
mem_set_mem_state_both(0xe0000, 0x10000, umc_8890_shadow_flag((dev->pci_conf[0x5f] & 0x0c) >> 2));
mem_set_mem_state_both(0xf0000, 0x10000, umc_8890_shadow_flag((dev->pci_conf[0x5f] & 0xc0) >> 6));
for(int i = 0; i < 8; i++)
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, umc_8890_shadow_flag(!!(dev->pci_conf[0x5d] & (1 << i))));
flushmmucache_nopc();
}
static void
um8890_write(int func, int addr, uint8_t val, void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
dev->pci_conf[addr] = val;
switch (addr)
{
case 0x5c:
case 0x5d:
case 0x5e:
case 0x5f:
umc_8890_shadow(dev);
break;
case 0x65: /* We don't know the default SMRAM values */
smram_disable_all();
smram_enable(dev->smram, 0xe0000, 0xe0000, 0x10000, dev->pci_conf[0x65] & 0x10, 1);
flushmmucache_nopc();
break;
}
umc_8890_log("UM8890: dev->regs[%02x] = %02x POST: %02x\n", addr, dev->pci_conf[addr], inb(0x80));
}
static uint8_t
um8890_read(int func, int addr, void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
return dev->pci_conf[addr];
}
static void
umc_8890_reset(void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
/* Defaults */
dev->pci_conf[0] = 0x60; /* UMC */
dev->pci_conf[1] = 0x10;
dev->pci_conf[2] = 0x91; /* 8891F */
dev->pci_conf[3] = 0x88;
dev->pci_conf[8] = 1;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
}
static void
umc_8890_close(void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
smram_del(dev->smram);
free(dev);
}
static void *
umc_8890_init(const device_t *info)
{
umc_8890_t *dev = (umc_8890_t *)malloc(sizeof(umc_8890_t));
memset(dev, 0, sizeof(umc_8890_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, um8890_read, um8890_write, dev); /* Device 0: UMC 8890 */
/* APM */
dev->apm = device_add(&apm_pci_device);
/* SMRAM(Needs excessive documentation before we begin SMM implementation) */
dev->smram = smram_add();
/* Port 92 */
device_add(&port_92_pci_device);
umc_8890_reset(dev);
return dev;
}
const device_t umc_8890_device = {
"UMC 8890(8891BF/8892BF)",
DEVICE_PCI,
0x886a,
umc_8890_init,
umc_8890_close,
umc_8890_reset,
{NULL},
NULL,
NULL,
NULL};

173
src/chipset/umc_hb4.c
View File

@@ -6,7 +6,7 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of the UMC HB4(8881F/8886xx) "Super Energy Star Green" PCI Chipset.
* Implementation of the UMC HB4 "Super Energy Star Green" PCI Chipset.
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
@@ -80,26 +80,6 @@ Bit 0: Reserved
Register 55:
Bit 7: Enable Shadow Reads For System & Selected Segments
Bit 6: Write Protect Enable
UMC 8886xx:
(F: Has No Internal IDE / AF or BF: Has Internal IDE)
Function 0 Register 43:
Bits 7-4 PCI IRQ for INTB
Bits 3-0 PCI IRQ for INTA
Function 0 Register 44:
Bits 7-4 PCI IRQ for INTD
Bits 3-0 PCI IRQ for INTC
Function 0 Register 46:
Bit 7: Replace SMI request for non-SMM CPU's (1: IRQ15/0: IRQ10)
Function 0 Register 51:
Bit 2: VGA Power Down (0: Standard/1: VESA DPMS)
Function 1 Register 4:
Bit 0: Enable Internal IDE
*/
#include <stdarg.h>
@@ -116,9 +96,6 @@ Bit 0: Enable Internal IDE
#include <86box/device.h>
#include <86box/apm.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/port_92.h>
@@ -149,26 +126,12 @@ hb4_log(const char *fmt, ...)
#define CAN_WRITE ((dev->pci_conf[0x55] & 0x40) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)
#define DISABLE (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
/* PCI IRQ Flags */
#define INTA (PCI_INTA + (2 * !(addr & 1)))
#define INTB (PCI_INTB + (2 * !(addr & 1)))
#define IRQRECALCA (((val & 0xf0) != 0) ? ((val & 0xf0) >> 4) : PCI_IRQ_DISABLED)
#define IRQRECALCB (((val & 0x0f) != 0) ? (val & 0x0f) : PCI_IRQ_DISABLED)
/* Disable Internal IDE Flag needed for the BF Southbridge variant */
#define HAS_IDE dev->has_ide
/* Southbridge Revision */
#define SB_ID dev->sb_id
typedef struct hb4_t
{
apm_t *apm;
smram_t *smram;
uint8_t pci_conf[256], pci_conf_sb[2][256]; /* PCI Registers */
uint16_t sb_id; /* Southbridge Revision */
int has_ide; /* Check if Southbridge Revision is AF or F */
uint8_t pci_conf[256]; /* PCI Registers */
} hb4_t;
void hb4_shadow(int cur_addr, hb4_t *dev)
@@ -180,18 +143,6 @@ void hb4_shadow(int cur_addr, hb4_t *dev)
mem_set_mem_state_both(0xe0000, 0x20000, CAN_READ | CAN_WRITE);
}
void ide_handler(int status)
{
ide_pri_disable();
ide_sec_disable();
if (status)
{
ide_pri_enable();
ide_sec_enable();
}
}
static void
um8881_write(int func, int addr, uint8_t val, void *priv)
{
@@ -235,81 +186,6 @@ um8881_read(int func, int addr, void *priv)
return dev->pci_conf[addr];
}
static void
um8886_write(int func, int addr, uint8_t val, void *priv)
{
hb4_t *dev = (hb4_t *)priv;
hb4_log("UM8886: dev->regs[%02x] = %02x (%02x)\n", addr, val, func);
if (addr > 3) /* We don't know the RW status of registers but Phoenix writes on some RO registers too*/
switch (func)
{
case 0: /* Southbridge */
switch (addr)
{
case 0x43:
case 0x44:
dev->pci_conf_sb[func][addr] = val;
pci_set_irq_routing(INTA, IRQRECALCA);
pci_set_irq_routing(INTB, IRQRECALCB);
break;
case 0x46:
dev->pci_conf_sb[func][addr] = val & 0xaf;
break;
case 0x47:
dev->pci_conf_sb[func][addr] = val & 0x4f;
break;
case 0x57:
dev->pci_conf_sb[func][addr] = val & 0x38;
break;
case 0x71:
dev->pci_conf_sb[func][addr] = val & 1;
break;
case 0x90:
dev->pci_conf_sb[func][addr] = val & 2;
break;
case 0x92:
dev->pci_conf_sb[func][addr] = val & 0x1f;
break;
case 0xa0:
dev->pci_conf_sb[func][addr] = val & 0xfc;
break;
case 0xa4:
dev->pci_conf_sb[func][addr] = val & 0x88;
break;
default:
dev->pci_conf_sb[func][addr] = val;
break;
}
break;
case 1: /* IDE Controller */
if ((addr == 4) && HAS_IDE)
{
dev->pci_conf_sb[func][addr] = val;
ide_handler(val & 1);
}
break;
}
}
static uint8_t
um8886_read(int func, int addr, void *priv)
{
hb4_t *dev = (hb4_t *)priv;
return dev->pci_conf_sb[func][addr];
}
static void
hb4_reset(void *priv)
{
@@ -327,28 +203,6 @@ hb4_reset(void *priv)
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf_sb[0][0] = 0x60; /* UMC */
dev->pci_conf_sb[0][1] = 0x10;
dev->pci_conf_sb[0][2] = (SB_ID & 0xff); /* 8886xx */
dev->pci_conf_sb[0][3] = ((SB_ID >> 8) & 0xff);
dev->pci_conf_sb[0][8] = 1;
dev->pci_conf_sb[0][0x09] = 0x00;
dev->pci_conf_sb[0][0x0a] = 0x01;
dev->pci_conf_sb[0][0x0b] = 0x06;
for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */
pci_set_irq_routing(i, PCI_IRQ_DISABLED);
if (HAS_IDE)
{
dev->pci_conf_sb[1][4] = 1; /* Start with Internal IDE Enabled */
ide_handler(1);
}
}
static void
@@ -366,9 +220,7 @@ hb4_init(const device_t *info)
hb4_t *dev = (hb4_t *)malloc(sizeof(hb4_t));
memset(dev, 0, sizeof(hb4_t));
dev->has_ide = (info->local & 0x886a);
pci_add_card(PCI_ADD_NORTHBRIDGE, um8881_read, um8881_write, dev); /* Device 10: UMC 8881x */
pci_add_card(PCI_ADD_SOUTHBRIDGE, um8886_read, um8886_write, dev); /* Device 12: UMC 8886xx */
/* APM */
dev->apm = device_add(&apm_pci_device);
@@ -379,20 +231,13 @@ hb4_init(const device_t *info)
/* Port 92 */
device_add(&port_92_pci_device);
/* Add IDE if UM8886AF variant */
if (HAS_IDE)
device_add(&ide_pci_2ch_device);
/* Get the Southbridge Revision */
SB_ID = info->local;
hb4_reset(dev);
return dev;
}
const device_t umc_hb4_device = {
"UMC HB4(8881F/8886AF)",
"UMC HB4(8881F)",
DEVICE_PCI,
0x886a,
hb4_init,
@@ -402,15 +247,3 @@ const device_t umc_hb4_device = {
NULL,
NULL,
NULL};
const device_t umc_hb4_early_device = {
"UMC HB4(8881F/8886F)",
DEVICE_PCI,
0x8886,
hb4_init,
hb4_close,
hb4_reset,
{NULL},
NULL,
NULL,
NULL};

5
src/include/86box/chipset.h
View File

@@ -119,7 +119,10 @@ extern const device_t stpc_lpt_device;
/* UMC */
extern const device_t umc_hb4_device;
extern const device_t umc_hb4_early_device;
extern const device_t umc_8890_device;
extern const device_t umc_8886f_device;
extern const device_t umc_8886af_device;
/* VIA */
extern const device_t via_vt82c49x_device;

2
src/include/86box/machine.h
View File

@@ -405,6 +405,8 @@ extern int machine_at_p5sp4_init(const machine_t *);
extern int machine_at_p54sp4_init(const machine_t *);
extern int machine_at_sq588_init(const machine_t *);
extern int machine_at_hot539_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_endeavor_get_device(void);
#define at_vectra54_get_device at_endeavor_get_device

31
src/machine/m_at_socket4_5.c
View File

@@ -738,3 +738,34 @@ machine_at_sq588_init(const machine_t *model)
return ret;
}
int
machine_at_hot539_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/hot539/539_R17.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x15, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x16, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&umc_8890_device);
device_add(&umc_8886af_device);
device_add(&intel_flash_bxt_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&um8669f_device);
return ret;
}

9
src/machine/machine_table.c
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@@ -240,9 +240,9 @@ const machine_t machines[] = {
{ "[SiS 496] Rise Computer R418", "r418", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_r418_init, NULL },
{ "[SiS 496] Soyo 4SA2", "4sa2", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_4sa2_init, NULL },
{ "[SiS 496] Zida Tomato 4DP", "4dps", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_4dps_init, NULL },
{ "[UMC 8880] A-Trend ATC-1415", "atc1415", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 65536, 1024, 255, machine_at_atc1415_init, NULL },
{ "[UMC 8880] ECS Elite UM8810PAIO", "ecs486", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_ecs486_init, NULL },
{ "[UMC 8880] Shuttle HOT-433A", "hot433", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 262144, 1024, 255, machine_at_hot433_init, NULL },
{ "[UMC 8881] A-Trend ATC-1415", "atc1415", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 65536, 1024, 255, machine_at_atc1415_init, NULL },
{ "[UMC 8881] ECS Elite UM8810PAIO", "ecs486", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_ecs486_init, NULL },
{ "[UMC 8881] Shuttle HOT-433A", "hot433", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 262144, 1024, 255, machine_at_hot433_init, NULL },
{ "[STPC Client] ITOX STAR", "itoxstar", MACHINE_TYPE_486, CPU_PKG_STPC, 0, 66666667, 75000000, 0, 0, 1.0, 1.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 255, machine_at_itoxstar_init, NULL },
{ "[STPC Consumer-II] Acrosser AR-B1479", "arb1479", MACHINE_TYPE_486, CPU_PKG_STPC, 0, 66666667, 66666667, 0, 0, 2.0, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 32768, 163840, 8192, 255, machine_at_arb1479_init, NULL },
{ "[STPC Elite] Advantech PCM-9340", "pcm9340", MACHINE_TYPE_486, CPU_PKG_STPC, 0, 66666667, 66666667, 0, 0, 2.0, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 32768, 98304, 8192, 255, machine_at_pcm9340_init, NULL },
@@ -286,6 +286,9 @@ const machine_t machines[] = {
{ "[SiS 85C50x] ASUS PCI/I-P54SP4", "p54sp4", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_K5, CPU_5K86), 40000000, 66666667, 3380, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54sp4_init, NULL },
{ "[SiS 85C50x] BCM SQ-588", "sq588", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_PENTIUMMMX), 50000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_sq588_init, NULL },
/* UMC 889x */
{ "[UMC 889x] Shuttle HOT-539", "hot539", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_K5, CPU_5K86), 40000000, 66666667, 3380, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 262144, 8192, 127, machine_at_hot539_init, NULL },
/* Socket 7 (Single Voltage) machines */
/* 430FX */
{ "[i430FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3600, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54tp4xe_init, NULL },

2
src/win/Makefile.mingw
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@@ -626,7 +626,7 @@ CHIPSETOBJ := acc2168.o cs8230.o ali1217.o ali1429.o headland.o intel_82335.o cs
neat.o opti495.o opti895.o opti5x7.o scamp.o scat.o via_vt82c49x.o via_vt82c505.o \
gc100.o olivetti_eva.o \
sis_85c310.o sis_85c4xx.o sis_85c496.o sis_85c50x.o stpc.o opti283.o opti291.o \
umc_hb4.o \
umc_8886.o umc_8890.o umc_hb4.o \
via_apollo.o via_pipc.o wd76c10.o vl82c480.o
MCHOBJ := machine.o machine_table.o \