Improvements to the OPTi 597 machine.
- Add emulation of the FDC37C661 Super I/O - Fix Pentium VLB timing (was running VLB at 2x bus speed instead of 1/2 bus speed) - Fix the cache register on the OPTi 5x7 chipset - The actual minimum RAM amount is 2 MB, not 1 MB. - Fix chipset naming consistency
This commit is contained in:
nerd73
278
src/sio/sio_fdc37c661.c
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278
src/sio/sio_fdc37c661.c
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the SMC FDC37C661 Super
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* I/O Chip.
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*
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*
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2020 Sarah Walker.
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* Copyright 2016-2020 Miran Grca.
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* Copyright 2020 plant/nerd73.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/timer.h>
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#include <86box/device.h>
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#include <86box/pci.h>
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#include <86box/lpt.h>
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#include <86box/serial.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/sio.h>
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typedef struct {
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uint8_t lock[2],
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regs[4];
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int cur_reg,
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com3_addr, com4_addr;
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fdc_t *fdc;
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serial_t *uart[2];
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} fdc37c661_t;
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static void
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write_lock(fdc37c661_t *dev, uint8_t val)
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{
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if (val == 0x55 && dev->lock[1] == 0x55)
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fdc_3f1_enable(dev->fdc, 0);
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if ((dev->lock[0] == 0x55) && (dev->lock[1] == 0x55) && (val != 0x55))
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fdc_3f1_enable(dev->fdc, 1);
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dev->lock[0] = dev->lock[1];
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dev->lock[1] = val;
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}
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static void
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set_com34_addr(fdc37c661_t *dev)
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{
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switch (dev->regs[1] & 0x60) {
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case 0x00:
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dev->com3_addr = 0x338;
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dev->com4_addr = 0x238;
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break;
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case 0x20:
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dev->com3_addr = 0x3e8;
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dev->com4_addr = 0x2e8;
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break;
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case 0x40:
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dev->com3_addr = 0x3e8;
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dev->com4_addr = 0x2e0;
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break;
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case 0x60:
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dev->com3_addr = 0x220;
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dev->com4_addr = 0x228;
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break;
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}
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}
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static void
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set_serial_addr(fdc37c661_t *dev, int port)
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{
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uint8_t shift = (port << 4);
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if (dev->regs[2] & (4 << shift)) {
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switch (dev->regs[2] & (3 << shift)) {
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case 0:
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serial_setup(dev->uart[port], SERIAL1_ADDR, SERIAL1_IRQ);
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break;
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case 1:
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serial_setup(dev->uart[port], SERIAL2_ADDR, SERIAL2_IRQ);
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break;
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case 2:
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serial_setup(dev->uart[port], dev->com3_addr, 4);
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break;
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case 3:
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serial_setup(dev->uart[port], dev->com4_addr, 3);
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break;
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}
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}
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}
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static void
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lpt1_handler(fdc37c661_t *dev)
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{
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lpt1_remove();
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switch (dev->regs[1] & 3) {
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case 1:
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lpt1_init(0x3bc);
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lpt1_irq(7);
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break;
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case 2:
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lpt1_init(0x378);
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lpt1_irq(5);
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break;
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case 3:
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lpt1_init(0x278);
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lpt1_irq(5);
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break;
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}
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}
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static void
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fdc_handler(fdc37c661_t *dev)
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{
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fdc_remove(dev->fdc);
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if (dev->regs[0] & 0x10)
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fdc_set_base(dev->fdc, 0x03f0);
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}
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static void
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fdc37c661_write(uint16_t port, uint8_t val, void *priv)
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{
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fdc37c661_t *dev = (fdc37c661_t *) priv;
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uint8_t valxor = 0;
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if ((dev->lock[0] == 0x55) && (dev->lock[1] == 0x55)) {
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if (port == 0x3f0) {
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if (val == 0xaa)
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write_lock(dev, val);
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else
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dev->cur_reg = val;
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} else {
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if (dev->cur_reg > 4)
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return;
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valxor = val ^ dev->regs[dev->cur_reg];
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dev->regs[dev->cur_reg] = val;
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switch(dev->cur_reg) {
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case 0:
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if (valxor & 0x10)
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fdc_handler(dev);
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break;
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case 1:
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if (valxor & 3)
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lpt1_handler(dev);
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if (valxor & 0x60) {
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serial_remove(dev->uart[0]);
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serial_remove(dev->uart[1]);
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set_com34_addr(dev);
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set_serial_addr(dev, 0);
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set_serial_addr(dev, 1);
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}
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break;
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case 2:
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if (valxor & 7) {
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serial_remove(dev->uart[0]);
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set_serial_addr(dev, 0);
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}
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if (valxor & 0x70) {
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serial_remove(dev->uart[1]);
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set_serial_addr(dev, 1);
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}
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break;
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case 3:
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if (valxor & 4)
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fdc_update_enh_mode(dev->fdc, (dev->regs[3] & 4) ? 1 : 0);
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break;
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}
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}
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} else {
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if (port == 0x3f0)
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write_lock(dev, val);
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}
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}
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static uint8_t
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fdc37c661_read(uint16_t port, void *priv)
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{
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fdc37c661_t *dev = (fdc37c661_t *) priv;
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uint8_t ret = 0xff;
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if ((dev->lock[0] == 0x55) && (dev->lock[1] == 0x55)) {
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if (port == 0x3f1)
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ret = dev->regs[dev->cur_reg];
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}
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return ret;
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}
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static void
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fdc37c661_reset(fdc37c661_t *dev)
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{
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dev->com3_addr = 0x338;
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dev->com4_addr = 0x238;
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serial_remove(dev->uart[0]);
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serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
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serial_remove(dev->uart[1]);
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serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
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lpt1_remove();
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lpt1_init(0x378);
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fdc_reset(dev->fdc);
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memset(dev->lock, 0, 2);
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memset(dev->regs, 0, 16);
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dev->regs[0x0] = 0x3f;
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dev->regs[0x1] = 0x9f;
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dev->regs[0x2] = 0xdc;
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dev->regs[0x3] = 0x78;
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}
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static void
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fdc37c661_close(void *priv)
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{
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fdc37c661_t *dev = (fdc37c661_t *) priv;
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free(dev);
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}
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static void *
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fdc37c661_init(const device_t *info)
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{
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fdc37c661_t *dev = (fdc37c661_t *) malloc(sizeof(fdc37c661_t));
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memset(dev, 0, sizeof(fdc37c661_t));
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dev->fdc = device_add(&fdc_at_smc_device);
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dev->uart[0] = device_add_inst(&ns16550_device, 1);
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dev->uart[1] = device_add_inst(&ns16550_device, 2);
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io_sethandler(0x03f0, 0x0002,
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fdc37c661_read, NULL, NULL, fdc37c661_write, NULL, NULL, dev);
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fdc37c661_reset(dev);
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return dev;
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}
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const device_t fdc37c661_device = {
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"SMC FDC37C661 Super I/O",
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0,
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0,
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fdc37c661_init, fdc37c661_close, NULL,
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NULL, NULL, NULL,
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NULL
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};
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