From 0a6f4e1b873d39108a9957ff989d145bd3a8c6fe Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 23 Mar 2020 08:50:59 +0100 Subject: [PATCH] Slight chipset clean-ups and ported the JMP FAR new recompiler commit from PCem. --- src/chipset/intel_4x0.c | 22 +- src/chipset/intel_4x0.c.old | 529 --------------------------------- src/chipset/sis_85c496.c | 9 +- src/cpu_new/codegen_ops_misc.c | 8 +- 4 files changed, 10 insertions(+), 558 deletions(-) delete mode 100644 src/chipset/intel_4x0.c.old diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index c03feb964..975eec0a5 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -64,8 +64,6 @@ typedef struct static void i4x0_map(uint32_t addr, uint32_t size, int state) { - // pclog("i4x0_map(%08X, %08X, %02X)\n", addr, size, state); - switch (state & 3) { case 0: mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); @@ -103,7 +101,6 @@ pm2_cntrl_read(uint16_t addr, void *p) { i4x0_t *dev = (i4x0_t *) p; - // pclog("PM2_CTL read: %02X\n", dev->pm2_cntrl & 0x01); return dev->pm2_cntrl & 0x01; } @@ -113,7 +110,6 @@ pm2_cntrl_write(uint16_t addr, uint8_t val, void *p) { i4x0_t *dev = (i4x0_t *) p; - // pclog("PM2_CTL write: %02X\n", val); dev->pm2_cntrl = val & 0x01; } @@ -131,15 +127,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) #endif #if defined(DEV_BRANCH) && defined(USE_I686) - if (func > dev->max_func) { + if (func > dev->max_func) #else - if (func > 0) { + if (func > 0) #endif - // pclog("invalid write %02X to %02X:%02X\n", val, func, addr); return; - } - - // pclog("write %02X to %02X:%02X\n", val, func, addr); if ((addr >= 0x10) && (addr < 0x4f)) return; @@ -702,7 +694,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); if (val & 0x40) io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); - // pclog("430TX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis"); break; #if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440BX: @@ -719,7 +710,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); if (val & 0x40) io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); - // pclog("440BX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis"); break; } break; @@ -965,13 +955,12 @@ i4x0_read(int func, int addr, void *priv) #endif #if defined(DEV_BRANCH) && defined(USE_I686) - if (func > dev->max_func) { + if (func > dev->max_func) #else - if (func > 0) { + if (func > 0) #endif ret = 0xff; - // pclog("invalid read %02X from %02X:%02X\n", ret, func, addr); - } else { + else { ret = regs[addr]; #if defined(DEV_BRANCH) && defined(USE_I686) /* Special behavior for 440FX register 0x93 which is basically TRC in PCI space @@ -979,7 +968,6 @@ i4x0_read(int func, int addr, void *priv) if ((func == 0) && (addr == 0x93) && (dev->type == INTEL_440FX)) ret = (ret & 0xf9) | (trc_read(0x0093, NULL) & 0x06); #endif - // pclog("read %02X from %02X:%02X\n", ret, func, addr); } return ret; diff --git a/src/chipset/intel_4x0.c.old b/src/chipset/intel_4x0.c.old deleted file mode 100644 index 3addcff70..000000000 --- a/src/chipset/intel_4x0.c.old +++ /dev/null @@ -1,529 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Implementation of the Intel PCISet chips from 420TX to 440FX. - * - * Version: @(#)intel_4x0.c 1.0.3 2020/01/24 - * - * Authors: Sarah Walker, - * Miran Grca, - * - * Copyright 2019,2020 Miran Grca. - */ -#include -#include -#include -#include -#include -#include "86box.h" -#include "cpu.h" -#include "mem.h" -#include "86box_io.h" -#include "rom.h" -#include "pci.h" -#include "device.h" -#include "keyboard.h" -#include "chipset.h" - - -enum -{ - INTEL_420TX, - INTEL_430LX, - INTEL_430NX, - INTEL_430FX, - INTEL_430FX_PB640, - INTEL_430HX, - INTEL_430VX, - INTEL_430TX -#if defined(DEV_BRANCH) && defined(USE_I686) - ,INTEL_440FX -#endif -}; - -typedef struct -{ - uint8_t pm2_cntrl; - uint8_t regs[256]; - int type; -} i4x0_t; -static void -i4x0_map(uint32_t addr, uint32_t size, int state) -{ - // pclog("i4x0_map(%08X, %08X, %02X)\n", addr, size, state); - - switch (state & 3) { - case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 1: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 2: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 3: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - } - flushmmucache_nopc(); -} - - -static void -i4x0_write(int func, int addr, uint8_t val, void *priv) -{ - i4x0_t *dev = (i4x0_t *) priv; - - if (func) - return; - - pclog("write %02X to %08X\n", val, addr); - - if ((addr >= 0x10) && (addr < 0x4f)) - return; - - switch (addr) { - case 0x00: case 0x01: case 0x02: case 0x03: - case 0x08: case 0x09: case 0x0a: case 0x0b: - case 0x0c: case 0x0e: - return; - - case 0x04: /*Command register*/ - if (dev->type >= INTEL_430FX) { - if (dev->type == INTEL_430FX_PB640) - val &= 0x06; - else - val &= 0x02; - } else - val &= 0x42; - val |= 0x04; - break; - case 0x05: - if (dev->type >= INTEL_430FX) - val = 0; - else - val &= 0x01; - break; - - case 0x06: /*Status*/ - val = 0; - break; - case 0x07: - if (dev->type >= INTEL_430HX) { - val &= 0x80; - val |= 0x02; - } else { - val = 0x02; - if (dev->type == INTEL_430FX_PB640) - val |= 0x20; - } - break; - - case 0x52: /*Cache Control Register*/ -#if defined(DEV_BRANCH) && defined(USE_I686) - if (dev->type < INTEL_440FX) { -#endif - cpu_cache_ext_enabled = (val & 0x01); - cpu_update_waitstates(); -#if defined(DEV_BRANCH) && defined(USE_I686) - } -#endif - break; - - case 0x59: /*PAM0*/ - if ((dev->regs[0x59] ^ val) & 0xf0) { - i4x0_map(0xf0000, 0x10000, val >> 4); - shadowbios = (val & 0x10); - } - break; - case 0x5a: /*PAM1*/ - if ((dev->regs[0x5a] ^ val) & 0x0f) - i4x0_map(0xc0000, 0x04000, val & 0xf); - if ((dev->regs[0x5a] ^ val) & 0xf0) - i4x0_map(0xc4000, 0x04000, val >> 4); - break; - case 0x5b: /*PAM2*/ - if ((dev->regs[0x5b] ^ val) & 0x0f) - i4x0_map(0xc8000, 0x04000, val & 0xf); - if ((dev->regs[0x5b] ^ val) & 0xf0) - i4x0_map(0xcc000, 0x04000, val >> 4); - break; - case 0x5c: /*PAM3*/ - if ((dev->regs[0x5c] ^ val) & 0x0f) - i4x0_map(0xd0000, 0x04000, val & 0xf); - if ((dev->regs[0x5c] ^ val) & 0xf0) - i4x0_map(0xd4000, 0x04000, val >> 4); - break; - case 0x5d: /*PAM4*/ - if ((dev->regs[0x5d] ^ val) & 0x0f) - i4x0_map(0xd8000, 0x04000, val & 0xf); - if ((dev->regs[0x5d] ^ val) & 0xf0) - i4x0_map(0xdc000, 0x04000, val >> 4); - break; - case 0x5e: /*PAM5*/ - if ((dev->regs[0x5e] ^ val) & 0x0f) - i4x0_map(0xe0000, 0x04000, val & 0xf); - if ((dev->regs[0x5e] ^ val) & 0xf0) - i4x0_map(0xe4000, 0x04000, val >> 4); - break; - case 0x5f: /*PAM6*/ - if ((dev->regs[0x5f] ^ val) & 0x0f) - i4x0_map(0xe8000, 0x04000, val & 0xf); - if ((dev->regs[0x5f] ^ val) & 0xf0) - i4x0_map(0xec000, 0x04000, val >> 4); - break; - case 0x72: /*SMRAM*/ - if ((dev->type >= INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x48)) - i4x0_map(0xa0000, 0x20000, ((val & 0x48) == 0x48) ? 3 : 0); - else if ((dev->type < INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x20)) - i4x0_map(0xa0000, 0x20000, ((val & 0x20) == 0x20) ? 3 : 0); - break; - - case 0x73: case 0x74: - // pclog("Access %i at %08X\n", dev->regs[0x73] & 3, dev->regs[0x74] << 19); - break; - } - - dev->regs[addr] = val; -} - - -static uint8_t -i4x0_read(int func, int addr, void *priv) -{ - i4x0_t *dev = (i4x0_t *) priv; - uint8_t ret = 0xff; - - if (!func) { - ret = dev->regs[addr]; - pclog("read %02X from %08X\n", ret, addr); - - // if (addr == 0x50) - // pclog("read %02X from %08X\n", ret, addr); - } - - return ret; -} - - -static void -i4x0_reset(void *priv) -{ - i4x0_t *i4x0 = (i4x0_t *)priv; - - i4x0_write(0, 0x59, 0x00, priv); - i4x0_write(0, 0x5e, 0x00, priv); - i4x0_write(0, 0x5f, 0x00, priv); - if (i4x0->type >= INTEL_430FX) - i4x0_write(0, 0x72, 0x02, priv); - - smbase = 0xa0000; -} - - -static void -i4x0_close(void *p) -{ - i4x0_t *i4x0 = (i4x0_t *)p; - - free(i4x0); -} - - -static uint8_t -pm2_cntrl_read(uint16_t addr, void *p) -{ - i4x0_t *dev = (i4x0_t *) p; - - return dev->pm2_cntrl & 0x01; -} - - -static void -pm2_cntrl_write(uint16_t addr, uint8_t val, void *p) -{ - i4x0_t *dev = (i4x0_t *) p; - - dev->pm2_cntrl = val & 0x01; -} - - -static void -*i4x0_init(const device_t *info) -{ - i4x0_t *i4x0 = (i4x0_t *) malloc(sizeof(i4x0_t)); - memset(i4x0, 0, sizeof(i4x0_t)); - - i4x0->type = info->local; - - i4x0->regs[0x00] = 0x86; i4x0->regs[0x01] = 0x80; /*Intel*/ - switch(i4x0->type) { - case INTEL_420TX: - i4x0->regs[0x02] = 0x83; i4x0->regs[0x03] = 0x04; /*82424TX/ZX*/ - i4x0->regs[0x08] = 0x03; /*A3 stepping*/ - i4x0->regs[0x50] = 0x80; - // i4x0->regs[0x50] = 0x23; - i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/ - break; - case INTEL_430LX: - i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/ - i4x0->regs[0x08] = 0x03; /*A3 stepping*/ - i4x0->regs[0x50] = 0x80; - i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/ - break; - case INTEL_430NX: - i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/ - i4x0->regs[0x08] = 0x10; /*A0 stepping*/ - i4x0->regs[0x50] = 0xA0; - i4x0->regs[0x52] = 0x44; /*256kb PLB cache*/ - i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02; - break; - case INTEL_430FX: - case INTEL_430FX_PB640: - i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/ - if (i4x0->type == INTEL_430FX_PB640) - i4x0->regs[0x08] = 0x02; /*???? stepping*/ - else - i4x0->regs[0x08] = 0x00; /*A0 stepping*/ - i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/ - break; - case INTEL_430HX: - i4x0->regs[0x02] = 0x50; i4x0->regs[0x03] = 0x12; /*82439HX*/ - i4x0->regs[0x08] = 0x00; /*A0 stepping*/ - i4x0->regs[0x51] = 0x20; - i4x0->regs[0x52] = 0xB5; /*512kb cache*/ - i4x0->regs[0x56] = 0x52; /*DRAM control*/ - // i4x0->regs[0x59] = 0x40; - // i4x0->regs[0x5A] = i4x0->regs[0x5B] = i4x0->regs[0x5C] = i4x0->regs[0x5D] = 0x44; - // i4x0->regs[0x5E] = i4x0->regs[0x5F] = 0x44; - i4x0->regs[0x65] = i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02; - i4x0->regs[0x68] = 0x11; - break; - case INTEL_430VX: - i4x0->regs[0x02] = 0x30; i4x0->regs[0x03] = 0x70; /*82437VX*/ - // i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/ - i4x0->regs[0x08] = 0x00; /*A0 stepping*/ - i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/ - i4x0->regs[0x53] = 0x14; - i4x0->regs[0x56] = 0x52; /*DRAM control*/ - i4x0->regs[0x67] = 0x11; - i4x0->regs[0x69] = 0x03; - i4x0->regs[0x70] = 0x20; - i4x0->regs[0x74] = 0x0e; - i4x0->regs[0x78] = 0x23; - break; - case INTEL_430TX: - io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, i4x0); - i4x0->regs[0x02] = 0x00; i4x0->regs[0x03] = 0x71; /*82439TX*/ - i4x0->regs[0x08] = 0x01; /*A0 stepping*/ - i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/ - i4x0->regs[0x53] = 0x14; - i4x0->regs[0x56] = 0x52; /*DRAM control*/ - i4x0->regs[0x65] = 0x02; - i4x0->regs[0x67] = 0x80; - i4x0->regs[0x69] = 0x03; - i4x0->regs[0x70] = 0x20; - break; -#if defined(DEV_BRANCH) && defined(USE_I686) - case INTEL_440FX: - i4x0->regs[0x02] = 0x37; i4x0->regs[0x03] = 0x12; /*82441FX*/ - i4x0->regs[0x08] = 0x02; /*A0 stepping*/ - i4x0->regs[0x2c] = 0xf4; - i4x0->regs[0x2d] = 0x1a; - i4x0->regs[0x2f] = 0x11; - i4x0->regs[0x51] = 0x01; - i4x0->regs[0x53] = 0x80; - i4x0->regs[0x58] = 0x10; - i4x0->regs[0x5a] = i4x0->regs[0x5b] = i4x0->regs[0x5c] = i4x0->regs[0x5d] = 0x11; - i4x0->regs[0x5e] = 0x11; - i4x0->regs[0x5f] = 0x31; - break; -#endif - } - i4x0->regs[0x04] = 0x06; i4x0->regs[0x05] = 0x00; -#if defined(DEV_BRANCH) && defined(USE_I686) - if (i4x0->type == INTEL_440FX) - i4x0->regs[0x06] = 0x80; -#endif - if (i4x0->type == INTEL_430FX) - i4x0->regs[0x07] = 0x82; -#if defined(DEV_BRANCH) && defined(USE_I686) - else if (i4x0->type != INTEL_440FX) -#else - else -#endif - i4x0->regs[0x07] = 0x02; - i4x0->regs[0x0b] = 0x06; - if (i4x0->type >= INTEL_430FX) - i4x0->regs[0x57] = 0x01; - else - i4x0->regs[0x57] = 0x31; - i4x0->regs[0x60] = i4x0->regs[0x61] = i4x0->regs[0x62] = i4x0->regs[0x63] = 0x02; - i4x0->regs[0x64] = 0x02; - if (i4x0->type >= INTEL_430FX) - i4x0->regs[0x72] = 0x02; - -#if defined(DEV_BRANCH) && defined(USE_I686) - if (i4x0->type == INTEL_440FX) { - cpu_cache_ext_enabled = 1; - cpu_update_waitstates(); - } -#endif - - pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, i4x0); - - i4x0_write(0, 0x59, 0x00, i4x0); - i4x0_write(0, 0x5a, 0x00, i4x0); - i4x0_write(0, 0x5b, 0x00, i4x0); - i4x0_write(0, 0x5c, 0x00, i4x0); - i4x0_write(0, 0x5d, 0x00, i4x0); - i4x0_write(0, 0x5e, 0x00, i4x0); - i4x0_write(0, 0x5f, 0x00, i4x0); - - smbase = 0xa0000; - - return i4x0; -} - - -const device_t i420tx_device = -{ - "Intel 82424TX", - DEVICE_PCI, - INTEL_420TX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430lx_device = -{ - "Intel 82434LX", - DEVICE_PCI, - INTEL_430LX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430nx_device = -{ - "Intel 82434NX", - DEVICE_PCI, - INTEL_430NX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430fx_device = -{ - "Intel SB82437FX-66", - DEVICE_PCI, - INTEL_430FX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430fx_pb640_device = -{ - "Intel SB82437FX-66 (PB640)", - DEVICE_PCI, - INTEL_430FX_PB640, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430hx_device = -{ - "Intel 82439HX", - DEVICE_PCI, - INTEL_430HX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430vx_device = -{ - "Intel 82437VX", - DEVICE_PCI, - INTEL_430VX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430tx_device = -{ - "Intel 82439TX", - DEVICE_PCI, - INTEL_430TX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -#if defined(DEV_BRANCH) && defined(USE_I686) -const device_t i440fx_device = -{ - "Intel 82441FX", - DEVICE_PCI, - INTEL_440FX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; -#endif diff --git a/src/chipset/sis_85c496.c b/src/chipset/sis_85c496.c index 51888f23f..607178fb9 100644 --- a/src/chipset/sis_85c496.c +++ b/src/chipset/sis_85c496.c @@ -120,8 +120,6 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv) if ((addr >= 4 && addr < 8) || addr >= 0x40) dev->pci_conf[addr] = val; - pclog("SiS 496 Write: %02X %02X %02X\n", func, addr, val); - valxor = old ^ val; switch (addr) { @@ -144,7 +142,6 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv) port_92_remove(dev->port_92); if (val & 0x02) port_92_add(dev->port_92); - pclog("Port 92: %sabled\n", (val & 0x02) ? "En" : "Dis"); } break; @@ -199,10 +196,8 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv) break; case 0x67: - if (valxor & 0x60) { + if (valxor & 0x60) port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40)); - pclog("[Port 92] Set features: %sreset, %sA20\n", !!(val & 0x20) ? "" : "no ", !!(val & 0x40) ? "" : "no "); - } break; case 0x82: @@ -252,8 +247,6 @@ sis_85c496_read(int func, int addr, void *priv) break; } - pclog("SiS 496 Read: %02X %02X %02X\n", func, addr, ret); - return ret; } diff --git a/src/cpu_new/codegen_ops_misc.c b/src/cpu_new/codegen_ops_misc.c index d4c243f96..eb73a4f81 100644 --- a/src/cpu_new/codegen_ops_misc.c +++ b/src/cpu_new/codegen_ops_misc.c @@ -359,11 +359,11 @@ uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe return -1; case 0x28: /*JMP far*/ + uop_MOVZX(ir, IREG_pc, src_reg); uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2); uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W); - uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc); + uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1); uop_CALL_FUNC(ir, loadcsjmp); - uop_MOVZX(ir, IREG_pc, src_reg); return -1; case 0x30: /*PUSH*/ @@ -466,11 +466,11 @@ uint32_t ropFF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe return -1; case 0x28: /*JMP far*/ + uop_MOV(ir, IREG_pc, src_reg); uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 4); uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W); - uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc); + uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1); uop_CALL_FUNC(ir, loadcsjmp); - uop_MOV(ir, IREG_pc, src_reg); return -1; case 0x30: /*PUSH*/