From 0af3f90c8f5a0784532b36834801f1ed5ce41aa3 Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Fri, 5 Jun 2020 23:12:36 +0300 Subject: [PATCH] Added the 440EX --- src/chipset/intel_4x0.c | 110 ++++++++++++++++++++++++++++++---- src/include/86box/chipset.h | 1 + src/include/86box/machine.h | 5 +- src/machine/m_at_slot1.c | 53 ++++++++++++++++ src/machine/m_at_socket7_s7.c | 30 ---------- src/machine/machine_table.c | 6 +- 6 files changed, 156 insertions(+), 49 deletions(-) diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index b06319e11..aee40c3e5 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -44,6 +44,7 @@ enum INTEL_430TX, INTEL_440FX, INTEL_440LX, + INTEL_440EX, INTEL_440BX, INTEL_440ZX }; @@ -258,7 +259,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42); break; case INTEL_430FX: case INTEL_430FX_PB640: case INTEL_430HX: case INTEL_430VX: case INTEL_430TX: - case INTEL_440FX: case INTEL_440LX: + case INTEL_440FX: case INTEL_440LX: case INTEL_440EX: regs[0x04] = (regs[0x04] & ~0x02) | (val & 0x02); break; } @@ -266,7 +267,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case 0x05: switch (dev->type) { case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX: - case INTEL_440FX: case INTEL_440LX: + case INTEL_440FX: case INTEL_440LX: case INTEL_440EX: case INTEL_440BX: case INTEL_440ZX: regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01); break; @@ -279,7 +280,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) regs[0x07] &= ~(val & 0x70); break; case INTEL_430FX: case INTEL_430FX_PB640: case INTEL_430VX: case INTEL_430TX: - case INTEL_440LX: + case INTEL_440LX: case INTEL_440EX: regs[0x07] &= ~(val & 0x30); break; case INTEL_440FX: @@ -336,7 +337,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case 0x34: switch (dev->type) { - case INTEL_440LX: + case INTEL_440LX: case INTEL_440EX: regs[0x34] = (val & 0xa0); } break; @@ -378,6 +379,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_440LX: regs[0x50] = (val & 0x03); break; + case INTEL_440EX: + regs[0x50] = (val & 0x23); + break; case INTEL_440BX: regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb); break; @@ -395,7 +399,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_440FX: regs[0x51] = (val & 0xc3); break; - case INTEL_440LX: + case INTEL_440LX: case INTEL_440EX: regs[0x51] = (val & 0x80); break; case INTEL_440BX: case INTEL_440ZX: @@ -439,7 +443,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_440LX: regs[0x53] = val & 0x0a; break; - case INTEL_440BX: + case INTEL_440EX: case INTEL_440BX: /* Not applicable to 440ZX as that does not support ECC. */ regs[0x53] = val; break; @@ -471,6 +475,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) regs[0x55] = val & 0x01; break; case INTEL_440FX: case INTEL_440LX: + case INTEL_440EX: regs[0x55] = val; break; } @@ -487,6 +492,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) regs[0x56] = val & 0x76; break; case INTEL_440FX: case INTEL_440LX: + case INTEL_440EX: regs[0x56] = val; break; } @@ -497,7 +503,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430LX: default: regs[0x57] = val & 0x3f; break; - case INTEL_430NX: + case INTEL_430NX: case INTEL_440EX: regs[0x57] = val; break; case INTEL_430FX: case INTEL_430FX_PB640: @@ -541,6 +547,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430TX: regs[0x57] = val & 0x7b; break; + case INTEL_440EX: + regs[0x58] = val & 0xbf; + break; } break; case 0x59: /* PAM0 */ @@ -604,7 +613,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX: - case INTEL_440FX: case INTEL_440LX: + case INTEL_440FX: + case INTEL_440LX: case INTEL_440EX: case INTEL_440BX: case INTEL_440ZX: default: regs[addr] = val; @@ -623,7 +633,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX: - case INTEL_440FX: case INTEL_440LX: + case INTEL_440FX: + case INTEL_440LX: case INTEL_440EX: case INTEL_440BX: case INTEL_440ZX: regs[addr] = val; break; @@ -639,6 +650,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) switch (dev->type) { case INTEL_430NX: case INTEL_430HX: case INTEL_440FX: case INTEL_440LX: + case INTEL_440EX: case INTEL_440BX: case INTEL_440ZX: regs[addr] = val; break; @@ -648,6 +660,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) switch (dev->type) { case INTEL_430NX: case INTEL_430HX: case INTEL_440FX: case INTEL_440LX: + case INTEL_440EX: case INTEL_440BX: case INTEL_440ZX: regs[addr] = val; break; @@ -669,6 +682,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) regs[0x68] = val & 0x1f; break; case INTEL_440FX: case INTEL_440LX: + case INTEL_440EX: regs[0x68] = val & 0xc0; break; case INTEL_440BX: @@ -697,6 +711,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) switch (dev->type) { case INTEL_430NX: case INTEL_440LX: + case INTEL_440EX: case INTEL_440BX: regs[addr] = val; break; @@ -711,6 +726,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case 0x6c: case 0x6d: case 0x6e: switch (dev->type) { case INTEL_440LX: + case INTEL_440EX: case INTEL_440BX: regs[addr] = val; break; @@ -725,6 +741,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case 0x6f: switch (dev->type){ case INTEL_440LX: + case INTEL_440EX: regs[addr] = val; break; } @@ -742,6 +759,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) regs[addr] = val & 0xfc; break; case INTEL_440FX: case INTEL_440LX: + case INTEL_440EX: regs[addr] = val & 0xf8; break; } @@ -752,7 +770,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430LX: regs[addr] = val & 0x4d; break; - case INTEL_430TX: + case INTEL_430TX: case INTEL_440EX: regs[addr] = val; break; case INTEL_440FX: case INTEL_440LX: @@ -893,6 +911,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_440LX: regs[0x80] = val & 0x08; break; + case INTEL_440EX: + regs[0x80] = val & 0x18; + break; case INTEL_440BX: case INTEL_440ZX: regs[0x7c] = val; break; @@ -902,6 +923,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) switch (dev->type) { case INTEL_430HX: case INTEL_440BX: case INTEL_440FX: case INTEL_440LX: + case INTEL_440EX: /* Not applicable on 82443ZX. */ regs[0x91] &= ~(val & 0x11); break; @@ -909,7 +931,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) break; case 0x92: switch (dev->type) { - case INTEL_440LX: + case INTEL_440LX: case INTEL_440EX: case INTEL_440BX: case INTEL_440ZX: regs[0x92] &= ~(val & 0x1f); break; @@ -919,6 +941,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) switch (dev->type) { case INTEL_440FX: case INTEL_440LX: + case INTEL_440EX: regs[0x93] = (val & 0x0f); trc_write(0x0093, val & 0x06, NULL); break; @@ -940,6 +963,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) break; case 0xb1: switch (dev->type) { + case INTEL_440EX: + regs[0xb1] = (val & 0x22); + break; case INTEL_440BX: case INTEL_440ZX: regs[0xb1] = (val & 0xa0); break; @@ -960,7 +986,31 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) break; } break; + case 0xba: case 0xbb: + switch (dev->type) { + case INTEL_440BX: case INTEL_440ZX: + regs[addr] = val; + break; + } + break; + + case 0xbc: + switch (dev->type) { + case INTEL_440EX: + regs[addr] = (val & 0xf8); + break; + } + break; + + case 0xbd: + switch (dev->type) { + case INTEL_440EX: + regs[addr] = (val & 0xf8); + break; + } + break; + case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7: switch (dev->type) { case INTEL_440BX: case INTEL_440ZX: @@ -1332,6 +1382,28 @@ static void regs[0xa5] = 0x02; regs[0xa7] = 0x1f; break; + case INTEL_440EX: + dev->max_func = 1; + + regs[0x02] = 0x80; regs[0x03] = 0x71; /* 82443EX. Same Vendor ID as 440LX*/ + regs[0x06] = 0x90; + regs[0x10] = 0x08; + regs[0x34] = 0xa0; + if (cpu_busspeed <= 66666667) + regs[0x51] |= 0x00; + else if ((cpu_busspeed > 66666667) && (cpu_busspeed <= 100000000)) + regs[0x51] |= 0x20; + regs[0x53] = 0x83; + regs[0x57] = 0x28; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01; + regs[0x6c] = regs[0x6d] = regs[0x6e] = regs[0x6f] = 0x55; + regs[0x72] = 0x02; + regs[0xa0] = 0x02; + regs[0xa2] = 0x10; + regs[0xa4] = 0x03; + regs[0xa5] = 0x02; + regs[0xa7] = 0x1f; + break; case INTEL_440BX: case INTEL_440ZX: regs[0x7a] = (info->local >> 8) & 0xff; dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1; @@ -1377,7 +1449,7 @@ static void i4x0_write(regs[0x5f], 0x5f, 0x00, dev); i4x0_write(regs[0x72], 0x72, 0x00, dev); - if ((dev->type == INTEL_440LX) && (dev->max_func == 1)) { + if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && (dev->max_func == 1)) { regs = (uint8_t *) dev->regs[1]; regs[0x00] = 0x86; regs[0x01] = 0x80; /* Intel */ @@ -1576,6 +1648,20 @@ const device_t i440lx_device = NULL }; +const device_t i440ex_device = +{ + "Intel 82443EX", + DEVICE_PCI, + INTEL_440EX, + i4x0_init, + i4x0_close, + i4x0_reset, + NULL, + NULL, + NULL, + NULL +}; + const device_t i440bx_device = { diff --git a/src/include/86box/chipset.h b/src/include/86box/chipset.h index 918f52287..5c840bd08 100644 --- a/src/include/86box/chipset.h +++ b/src/include/86box/chipset.h @@ -43,6 +43,7 @@ extern const device_t i430vx_device; extern const device_t i430tx_device; extern const device_t i440fx_device; extern const device_t i440lx_device; +extern const device_t i440ex_device; extern const device_t i440bx_device; extern const device_t i440zx_device; diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index b61583abc..22c140427 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -312,9 +312,6 @@ extern int machine_at_p5mms98_init(const machine_t *); extern int machine_at_ficva502_init(const machine_t *); extern int machine_at_ficpa2012_init(const machine_t *); -#if defined(DEV_BRANCH) && defined(NO_SIO) -extern int machine_at_advanceii_init(const machine_t *); -#endif #ifdef EMU_DEVICE_H extern const device_t *at_pb640_get_device(void); @@ -338,6 +335,8 @@ extern int machine_at_p65up5_cp6nd_init(const machine_t *); extern int machine_at_p65up5_cpknd_init(const machine_t *); extern int machine_at_kn97_init(const machine_t *); +extern int machine_at_p6i440e2_init(const machine_t *); + extern int machine_at_p2bls_init(const machine_t *); extern int machine_at_p3bf_init(const machine_t *); extern int machine_at_bf6_init(const machine_t *); diff --git a/src/machine/m_at_slot1.c b/src/machine/m_at_slot1.c index 2fdc1c065..d61e6eb50 100644 --- a/src/machine/m_at_slot1.c +++ b/src/machine/m_at_slot1.c @@ -108,6 +108,59 @@ machine_at_kn97_init(const machine_t *model) return ret; } +int +machine_at_p6i440e2_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/p6i440e2/E2_v14sl.bin", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440ex_device); + device_add(&piix4_device); + device_add(&keyboard_ps2_pci_device); + device_add(&w83977tf_device); + device_add(&sst_flash_29ee010_device); + spd_register(SPD_TYPE_SDRAM, 0x03, 256); + + hwm_values_t machine_hwm = { + { /* fan speeds */ + 3000, /* Chassis */ + 3000, /* CPU */ + 3000 /* Power */ + }, { /* temperatures */ + 30, /* MB */ + 0, /* unused */ + 27 /* CPU */ + }, { /* voltages */ + 2050, /* VCORE (2.05V by default) */ + 0, /* unused */ + 3300, /* +3.3V */ + RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */ + RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */ + RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */ + RESISTOR_DIVIDER(5000, 1, 2) /* -5V (divider values bruteforced) */ + } + }; + if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2) + machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Klamath */ + hwm_set_values(machine_hwm); + device_add(&w83781d_device); + + return ret; +} + int machine_at_p2bls_init(const machine_t *model) { diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c index a53216e1f..0b93b7b20 100644 --- a/src/machine/m_at_socket7_s7.c +++ b/src/machine/m_at_socket7_s7.c @@ -968,33 +968,3 @@ machine_at_ficpa2012_init(const machine_t *model) return ret; } - -#if defined(DEV_BRANCH) && defined(NO_SIO) -int -machine_at_advanceii_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/advanceii/VP3_V27.BIN", - 0x000e0000, 131072, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - device_add(&via_vp3_device); - device_add(&via_vt82c586b_device); - device_add(&keyboard_ps2_pci_device); - device_add(&um8669f_device); //IT8661F - device_add(&sst_flash_39sf010_device); - - return ret; -} -#endif \ No newline at end of file diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index e84f788d1..9a6804566 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -273,9 +273,6 @@ const machine_t machines[] = { /* Apollo VP3 */ { "[Socket 7 VP3] FIC PA-2012", "ficpa2012", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_ficpa2012_init, NULL }, -#if defined(DEV_BRANCH) && defined(NO_SIO) - { "[Socket 7 VP3] QDI Advance II", "advanceii", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_advanceii_init, NULL }, -#endif /* Super Socket 7 machines */ /* Apollo MVP3 */ @@ -296,7 +293,8 @@ const machine_t machines[] = { { "[Slot 1 FX] ASUS P/I-P65UP5 (C-PKND)", "p65up5_cpknd", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_p65up5_cpknd_init, NULL }, { "[Slot 1 FX] ASUS KN97", "kn97", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 384, 8, 127, machine_at_kn97_init, NULL }, - /* 440LX */ + /* 440EX */ + { "[Slot 1 EX] QDI EXCELLENT II", "p6i440e2", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_p6i440e2_init, NULL }, /* 440BX */ { "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },