Added the C&T 82C100 chipset needed by the Victor V86P.
This commit is contained in:
OBattler
parent
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commit
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352
src/chipset/82c100.c
Normal file
352
src/chipset/82c100.c
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@ -0,0 +1,352 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of Chips&Technology's 82C100 chipset.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2021 Miran Grca.
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/device.h>
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#include "cpu.h"
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#include "x86.h"
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#include <86box/io.h>
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#include <86box/mem.h>
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#include <86box/nmi.h>
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#include <86box/port_92.h>
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#include <86box/rom.h>
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#include <86box/chipset.h>
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typedef struct
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{
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int enabled;
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uint32_t virt, phys;
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} ems_page_t;
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typedef struct
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{
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uint8_t index, access;
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uint16_t ems_io_base;
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uint32_t ems_window_base;
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uint8_t ems_page_regs[4],
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regs[256];
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ems_page_t ems_pages[4];
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mem_mapping_t ems_mappings[4];
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} ct_82c100_t;
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static void
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ct_82c100_ems_pages_recalc(ct_82c100_t *dev)
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{
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int i;
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uint32_t page_base;
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for (i = 0; i < 4; i++) {
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page_base = dev->ems_window_base + (i << 14);
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if (dev->ems_page_regs[i] & 0x80) {
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dev->ems_pages[i].virt = page_base;
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dev->ems_pages[i].phys = 0xa0000 + (((uint32_t) (dev->ems_page_regs[4] & 0x7f)) << 14);
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mem_mapping_set_addr(&(dev->ems_mappings[i]), dev->ems_pages[i].virt, 0x4000);
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mem_mapping_set_exec(&(dev->ems_mappings[i]), &(ram[dev->ems_pages[i].phys]));
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mem_set_mem_state_both(page_base, 0x00004000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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} else {
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mem_mapping_disable(&(dev->ems_mappings[i]));
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mem_set_mem_state_both(page_base, 0x00004000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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}
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}
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}
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static void
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ct_82c100_ems_out(uint16_t port, uint8_t val, void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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dev->ems_page_regs[port >> 14] = val;
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ct_82c100_ems_pages_recalc(dev);
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}
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static uint8_t
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ct_82c100_ems_in(uint16_t port, void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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uint8_t ret = 0xff;
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ret = dev->ems_page_regs[port >> 14];
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return ret;
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}
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static void
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ct_82c100_ems_update(ct_82c100_t *dev)
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{
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int i;
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for (i = 0; i < 4; i++) {
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io_handler(0, dev->ems_io_base + (i << 14), 1,
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ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev);
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}
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dev->ems_io_base = 0x0208 + (dev->regs[0x4c] & 0xf0);
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for (i = 0; i < 4; i++) {
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io_handler(1, dev->ems_io_base + (i << 14), 1,
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ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev);
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}
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dev->ems_window_base = 0xc0000 + (((uint32_t) (dev->regs[0x4c] & 0x0f)) << 14);
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ct_82c100_ems_pages_recalc(dev);
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}
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static void
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ct_82c100_reset(void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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memset(dev->regs, 0x00, sizeof(dev->regs));
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memset(dev->ems_page_regs, 0x00, sizeof(dev->ems_page_regs));
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dev->index = dev->access = 0x00;
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/* INTERNAL CONFIGURATION/CONTROL REGISTERS */
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dev->regs[0x40] = 0x01; /* Defaults to 8086/V30 mode. */
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dev->regs[0x43] = 0x30;
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dev->regs[0x48] = 0x01;
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use_custom_nmi_vector = 0;
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ct_82c100_ems_update(dev);
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/* ADDITIONAL I/O REGISTERS */
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}
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static void
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ct_82c100_out(uint16_t port, uint8_t val, void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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if (port == 0x0022) {
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dev->index = val;
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dev->access = 1;
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} else if (port == 0x0023) {
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if (dev->access) {
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switch (dev->index) {
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/* INTERNAL CONFIGURATION/CONTROL REGISTERS */
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case 0x40:
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dev->regs[0x40] = val & 0xc7;
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/* TODO: Clock stuff - needs CPU speed change functionality that's
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going to be implemented in 86box v4.0.
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Bit 0 is 0 for 8088/V20 and 1 for 8086/V30. */
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break;
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case 0x41:
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dev->regs[0x41] = val & 0xed;
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/* TODO: Where is the Software Reset Function that's enabled by
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setting bit 6 to 1? */
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break;
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case 0x42:
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dev->regs[0x42] = val & 0x01;
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break;
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case 0x43:
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dev->regs[0x43] = val;
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break;
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case 0x44:
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dev->regs[0x44] = val;
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custom_nmi_vector = (custom_nmi_vector & 0xffffff00) | ((uint32_t) val);
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break;
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case 0x45:
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dev->regs[0x45] = val;
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custom_nmi_vector = (custom_nmi_vector & 0xffff00ff) | (((uint32_t) val) << 8);
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break;
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case 0x46:
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dev->regs[0x46] = val;
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custom_nmi_vector = (custom_nmi_vector & 0xff00ffff) | (((uint32_t) val) << 16);
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break;
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case 0x47:
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dev->regs[0x47] = val;
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custom_nmi_vector = (custom_nmi_vector & 0x00ffffff) | (((uint32_t) val) << 24);
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break;
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case 0x48: case 0x49:
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dev->regs[dev->index] = val;
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break;
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case 0x4b:
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dev->regs[0x4b] = val;
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use_custom_nmi_vector = !!(val & 0x40);
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break;
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case 0x4c:
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dev->regs[0x4c] = val;
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ct_82c100_ems_update(dev);
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break;
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}
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dev->access = 0;
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}
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} else if (port == 0x72)
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dev->regs[0x72] = val & 0x7e;
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else if (port == 0x7e)
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dev->regs[0x7e] = val;
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else if (port == 0x7f) {
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/* Bit 3 is Software Controlled Reset, asserted if set. Will be
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done in the feature/machine_and_kb branch using hardresetx86(). */
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dev->regs[0x7f] = val;
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if ((dev->regs[0x41] & 0x40) && (val & 0x08)) {
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softresetx86();
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cpu_set_edx();
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ct_82c100_reset(dev);
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}
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}
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}
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static uint8_t
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ct_82c100_in(uint16_t port, void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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uint8_t ret = 0xff;
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if (port == 0x0022)
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ret = dev->index;
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else if (port == 0x0023) {
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if (dev->access) {
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switch (dev->index) {
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/* INTERNAL CONFIGURATION/CONTROL REGISTERS */
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case 0x40 ... 0x49:
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case 0x4b: case 0x4c:
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ret = dev->regs[dev->index];
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break;
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}
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dev->access = 0;
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}
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} else if (port == 0x72)
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ret = dev->regs[0x72];
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else if (port == 0x7e)
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ret = dev->regs[0x7e];
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else if (port == 0x7f)
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ret = dev->regs[0x7f];
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return ret;
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}
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static uint8_t
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mem_read_emsb(uint32_t addr, void *priv)
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{
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ems_page_t *page = (ems_page_t *)priv;
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uint8_t val = 0xff;
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addr = addr - page->virt + page->phys;
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if (addr < ((uint32_t)mem_size << 10))
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val = ram[addr];
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return val;
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}
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static uint16_t
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mem_read_emsw(uint32_t addr, void *priv)
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{
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ems_page_t *page = (ems_page_t *)priv;
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uint16_t val = 0xffff;
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addr = addr - page->virt + page->phys;
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if (addr < ((uint32_t)mem_size << 10))
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val = *(uint16_t *)&ram[addr];
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return val;
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}
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static void
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mem_write_emsb(uint32_t addr, uint8_t val, void *priv)
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{
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ems_page_t *page = (ems_page_t *)priv;
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addr = addr - page->virt + page->phys;
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if (addr < ((uint32_t)mem_size << 10))
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ram[addr] = val;
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}
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static void
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mem_write_emsw(uint32_t addr, uint16_t val, void *priv)
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{
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ems_page_t *page = (ems_page_t *)priv;
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addr = addr - page->virt + page->phys;
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if (addr < ((uint32_t)mem_size << 10))
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*(uint16_t *)&ram[addr] = val;
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}
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static void
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ct_82c100_close(void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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free(dev);
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}
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static void *
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ct_82c100_init(const device_t *info)
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{
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ct_82c100_t *dev;
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uint32_t i;
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dev = (ct_82c100_t *)malloc(sizeof(ct_82c100_t));
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memset(dev, 0x00, sizeof(ct_82c100_t));
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ct_82c100_reset(dev);
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io_sethandler(0x0022, 2,
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ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev);
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io_sethandler(0x0072, 1,
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ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev);
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io_sethandler(0x007e, 2,
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ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev);
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for (i = 0; i < 4; i++) {
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mem_mapping_add(&(dev->ems_mappings[i]), (i + 28) << 14, 0x04000,
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mem_read_emsb, mem_read_emsw, NULL,
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mem_write_emsb, mem_write_emsw, NULL,
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ram + 0xa0000 + (i << 14), MEM_MAPPING_INTERNAL, &dev->ems_pages[i]);
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mem_mapping_disable(&(dev->ems_mappings[i]));
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}
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mem_mapping_disable(&ram_mid_mapping);
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device_add(&port_92_device);
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return(dev);
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}
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const device_t ct_82c100_device = {
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"C&T 82C100",
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0,
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0,
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ct_82c100_init, ct_82c100_close, ct_82c100_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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@ -13,7 +13,7 @@
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# Copyright 2020,2021 David Hrdlička.
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#
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add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c ali1489.c et6000.c headland.c
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add_library(chipset OBJECT 82c100.c acc2168.c cs8230.c ali1217.c ali1429.c ali1489.c et6000.c headland.c
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intel_82335.c cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c ../ioapic.c
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neat.c opti283.c opti291.c opti495.c opti822.c opti895.c opti5x7.c scamp.c scat.c
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sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c sis_5511.c sis_5571.c sis_5598.c
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@ -38,6 +38,10 @@
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/* Is the CPU 8088 or 8086. */
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int is8086 = 0;
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uint8_t use_custom_nmi_vector = 0;
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uint32_t custom_nmi_vector = 0x00000000;
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/* The prefetch queue (4 bytes for 8088, 6 bytes for 8086). */
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static uint8_t pfq[6];
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@ -578,6 +582,9 @@ reset_808x(int hard)
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prefetching = 1;
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cpu_alu_op = 0;
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use_custom_nmi_vector = 0x00;
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custom_nmi_vector = 0x00000000;
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}
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@ -943,6 +950,41 @@ interrupt(uint16_t addr)
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}
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static void
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custom_nmi(void)
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{
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uint16_t old_cs, old_ip;
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uint16_t new_cs, new_ip;
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uint16_t tempf;
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cpu_state.eaaddr = 0x0002;
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old_cs = CS;
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access(5, 16);
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(void) readmemw(0, cpu_state.eaaddr);
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new_ip = custom_nmi_vector & 0xffff;
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wait(1, 0);
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cpu_state.eaaddr = (cpu_state.eaaddr + 2) & 0xffff;
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access(6, 16);
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(void) readmemw(0, cpu_state.eaaddr);
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new_cs = custom_nmi_vector >> 16;
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prefetching = 0;
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pfq_clear();
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ovr_seg = NULL;
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access(39, 16);
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tempf = cpu_state.flags & 0x0fd7;
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push(&tempf);
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cpu_state.flags &= ~(I_FLAG | T_FLAG);
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access(40, 16);
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push(&old_cs);
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old_ip = cpu_state.pc;
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load_cs(new_cs);
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access(68, 16);
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set_ip(new_ip);
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access(41, 16);
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push(&old_ip);
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}
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static int
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irq_pending(void)
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{
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@ -967,7 +1009,10 @@ check_interrupts(void)
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}
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if (nmi && nmi_enable && nmi_mask) {
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nmi_enable = 0;
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interrupt(2);
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if (use_custom_nmi_vector)
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custom_nmi();
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else
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interrupt(2);
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#ifndef OLD_NMI_BEHAVIOR
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nmi = 0;
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#endif
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@ -715,6 +715,9 @@ extern int reset_on_hlt, hlt_reset_pending;
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extern cyrix_t cyrix;
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extern uint8_t use_custom_nmi_vector;
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extern uint32_t custom_nmi_vector;
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extern void (*cpu_exec)(int cycs);
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extern uint8_t do_translate, do_translate2;
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@ -37,6 +37,7 @@ extern const device_t ali6117d_device;
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extern const device_t amd640_device;
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/* C&T */
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extern const device_t ct_82c100_device;
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extern const device_t neat_device;
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extern const device_t scat_device;
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extern const device_t scat_4_device;
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@ -65,6 +66,7 @@ extern const device_t i420zx_device;
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extern const device_t i430lx_device;
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extern const device_t i430nx_device;
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extern const device_t i430fx_device;
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extern const device_t i430fx_old_device;
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extern const device_t i430fx_rev02_device;
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extern const device_t i430hx_device;
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extern const device_t i430vx_device;
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@ -84,6 +86,7 @@ extern const device_t sio_device;
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extern const device_t sio_zb_device;
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extern const device_t piix_device;
|
||||
extern const device_t piix_old_device;
|
||||
extern const device_t piix_rev02_device;
|
||||
extern const device_t piix3_device;
|
||||
extern const device_t piix4_device;
|
||||
|
||||
@ -43,6 +43,7 @@
|
||||
#include <86box/fdc.h>
|
||||
#include <86box/fdc_ext.h>
|
||||
#include <86box/keyboard.h>
|
||||
#include <86box/chipset.h>
|
||||
#include <86box/sio.h>
|
||||
#include <86box/video.h>
|
||||
|
||||
@ -69,6 +70,7 @@ machine_v86p_init(const machine_t *model)
|
||||
|
||||
machine_common_init(model);
|
||||
|
||||
device_add(&ct_82c100_device);
|
||||
device_add(&f82c606_device);
|
||||
|
||||
device_add(&keyboard_xt_device);
|
||||
|
||||
@ -20,6 +20,6 @@ void nmi_write(uint16_t port, uint8_t val, void *p)
|
||||
|
||||
void nmi_init(void)
|
||||
{
|
||||
io_sethandler(0x00a0, 0x0001, NULL, NULL, NULL, nmi_write, NULL, NULL, NULL);
|
||||
io_sethandler(0x00a0, 0x000f, NULL, NULL, NULL, nmi_write, NULL, NULL, NULL);
|
||||
nmi_mask = 0;
|
||||
}
|
||||
|
||||
@ -620,7 +620,7 @@ CPUOBJ := $(DYNARECOBJ) \
|
||||
808x.o 386.o 386_common.o 386_dynarec.o 386_dynarec_ops.o \
|
||||
x86seg.o x87.o x87_timings.o
|
||||
|
||||
CHIPSETOBJ := acc2168.o cs8230.o ali1217.o ali1429.o ali1489.o et6000.o headland.o intel_82335.o cs4031.o \
|
||||
CHIPSETOBJ := 82c100.o acc2168.o cs8230.o ali1217.o ali1429.o ali1489.o et6000.o headland.o intel_82335.o cs4031.o \
|
||||
intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
|
||||
neat.o opti495.o opti822.o opti895.o opti5x7.o scamp.o scat.o via_vt82c49x.o via_vt82c505.o \
|
||||
gc100.o \
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user