From 0fedbf9b469595fb7bd7fa23b5d6f409b1566e57 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 21 Jul 2024 21:46:13 -0400 Subject: [PATCH] Named initializers for socket 5's and 7's --- src/cpu/cpu_table.c | 2718 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 2566 insertions(+), 152 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 2541c5875..d9b5247ea 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -3562,15 +3562,159 @@ const cpu_family_t cpu_families[] = { .name = "Pentium", .internal_name = "pentium_p54c", .cpus = (const CPU[]) { - {"75", CPU_PENTIUM, fpus_internal, 75000000, 1.5, 3520, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"90", CPU_PENTIUM, fpus_internal, 90000000, 1.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"100/50", CPU_PENTIUM, fpus_internal, 100000000, 2.0, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12}, - {"100/66", CPU_PENTIUM, fpus_internal, 100000000, 1.5, 3520, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, - {"120", CPU_PENTIUM, fpus_internal, 120000000, 2.0, 3520, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"133", CPU_PENTIUM, fpus_internal, 133333333, 2.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"150", CPU_PENTIUM, fpus_internal, 150000000, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"166", CPU_PENTIUM, fpus_internal, 166666666, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_PENTIUM, fpus_internal, 200000000, 3.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + { + .name = "75", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x522, + .cpuid_model = 0x522, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 9 + }, + { + .name = "90", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 21/2 + }, + { + .name = "100/50", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 12 + }, + { + .name = "100/66", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x526, + .cpuid_model = 0x526, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x526, + .cpuid_model = 0x526, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "150", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "200", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, { .name = "", 0 } } }, @@ -3580,9 +3724,57 @@ const cpu_family_t cpu_families[] = { .name = "Pentium MMX", .internal_name = "pentium_p55c", .cpus = (const CPU[]) { - {"166", CPU_PENTIUMMMX, fpus_internal, 166666666, 2.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_PENTIUMMMX, fpus_internal, 233333333, 3.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + { + .name = "166", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "200", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, { .name = "", 0 } } }, @@ -3592,14 +3784,142 @@ const cpu_family_t cpu_families[] = { .name = "Mobile Pentium MMX", .internal_name = "pentium_tillamook", .cpus = (const CPU[]) { - {"120", CPU_PENTIUMMMX, fpus_internal, 120000000, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"133", CPU_PENTIUMMMX, fpus_internal, 133333333, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"150", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 2800, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"166", CPU_PENTIUMMMX, fpus_internal, 166666666, 2.5, 2800, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 2800, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_PENTIUMMMX, fpus_internal, 233333333, 3.5, 2800, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"266", CPU_PENTIUMMMX, fpus_internal, 266666666, 4.0, 2800, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_PENTIUMMMX, fpus_internal, 300000000, 4.5, 2800, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + { + .name = "120", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x543, + .cpuid_model = 0x543, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "150", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x544, + .cpuid_model = 0x544, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2800, + .edx_reset = 0x544, + .cpuid_model = 0x544, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "200", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2800, + .edx_reset = 0x581, + .cpuid_model = 0x581, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2800, + .edx_reset = 0x581, + .cpuid_model = 0x581, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { + .name = "266", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2800, + .edx_reset = 0x582, + .cpuid_model = 0x582, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { + .name = "300", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2800, + .edx_reset = 0x582, + .cpuid_model = 0x582, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 36 + }, { .name = "", 0 } } }, @@ -3609,9 +3929,57 @@ const cpu_family_t cpu_families[] = { .name = "Pentium OverDrive", .internal_name = "pentium_p54c_od3v", .cpus = (const CPU[]) { - {"125", CPU_PENTIUM, fpus_internal, 125000000, 3.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15}, - {"150", CPU_PENTIUM, fpus_internal, 150000000, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2}, - {"166", CPU_PENTIUM, fpus_internal, 166666666, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 20}, + { + .name = "125", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 125000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 15 + }, + { + .name = "150", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_PENTIUM, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x52c, + .cpuid_model = 0x52c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, { .name = "", 0 } } }, @@ -3621,12 +3989,98 @@ const cpu_family_t cpu_families[] = { .name = "Pentium OverDrive MMX", .internal_name = "pentium_p55c_od", .cpus = (const CPU[]) { - {"75", CPU_PENTIUMMMX, fpus_internal, 75000000, 1.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 7, 7,4,4, 9}, - {"125", CPU_PENTIUMMMX, fpus_internal, 125000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15}, - {"150/60", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2}, - {"166", CPU_PENTIUMMMX, fpus_internal, 166000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 20}, - {"180", CPU_PENTIUMMMX, fpus_internal, 180000000, 3.0, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18,9,9, 21}, - {"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 18,18,9,9, 24}, + { + .name = "75", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, .edx_reset = 0x1542, .cpuid_model = 0x1542, .cyrix_id = 0, .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, .mem_read_cycles = 7, .mem_write_cycles = 7,.cache_read_cycles = 4,.cache_write_cycles = 4, .atclk_div = 9}, + { + .name = "125", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 125000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 15 + }, + { + .name = "150/60", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 166000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "180", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 180000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 21 + }, + { + .name = "200", + .cpu_type = CPU_PENTIUMMMX, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x1542, + .cpuid_model = 0x1542, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, { .name = "", 0 } } }, @@ -3636,17 +4090,193 @@ const cpu_family_t cpu_families[] = { .name = "WinChip", .internal_name = "winchip", .cpus = (const CPU[]) { - {"75", CPU_WINCHIP, fpus_internal, 75000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, - {"90", CPU_WINCHIP, fpus_internal, 90000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, - {"100", CPU_WINCHIP, fpus_internal, 100000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, - {"120", CPU_WINCHIP, fpus_internal, 120000000, 2.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, - {"133", CPU_WINCHIP, fpus_internal, 133333333, 2.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, - {"150", CPU_WINCHIP, fpus_internal, 150000000, 2.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, - {"166", CPU_WINCHIP, fpus_internal, 166666666, 2.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, - {"180", CPU_WINCHIP, fpus_internal, 180000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, - {"200", CPU_WINCHIP, fpus_internal, 200000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"225", CPU_WINCHIP, fpus_internal, 225000000, 3.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, - {"240", CPU_WINCHIP, fpus_internal, 240000000, 4.0, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, + { + .name = "75", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 9 + }, + { + .name = "90", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 21/2 + }, + { + .name = "100", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "150", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "166", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 40 + }, + { + .name = "180", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 180000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 21 + }, + { + .name = "200", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "225", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 225000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 27 + }, + { + .name = "240", + .cpu_type = CPU_WINCHIP, + .fpus = fpus_internal, + .rspeed = 240000000, + .multi = 4.0, + .voltage = 3520, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 28 + }, { .name = "", 0 } } }, @@ -3656,10 +4286,74 @@ const cpu_family_t cpu_families[] = { .name = "WinChip 2", .internal_name = "winchip2", .cpus = (const CPU[]) { - {"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, - {"225", CPU_WINCHIP2, fpus_internal, 225000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9}, - {"240", CPU_WINCHIP2, fpus_internal, 240000000, 4.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"250", CPU_WINCHIP2, fpus_internal, 250000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + { + .name = "200", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 3*8 + }, + { + .name = "225", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 225000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 3*9 + }, + { + .name = "240", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 240000000, + .multi = 4.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 30 + }, + { + .name = "250", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 30 + }, { .name = "", 0 } } }, @@ -3669,10 +4363,74 @@ const cpu_family_t cpu_families[] = { .name = "WinChip 2A", .internal_name = "winchip2a", .cpus = (const CPU[]) { - {"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, - {"233", CPU_WINCHIP2, fpus_internal, 233333333, 3.5, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2}, - {"266", CPU_WINCHIP2, fpus_internal, 233333333, 7.0/3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28}, - {"300", CPU_WINCHIP2, fpus_internal, 250000000, 2.5, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 8, 8, 30}, + { + .name = "200", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 3*8 + }, + { + .name = "233", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = (7*8)/2 + }, + { + .name = "266", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 7.0/3.0, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 28 + }, + { + .name = "300", + .cpu_type = CPU_WINCHIP2, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x587, + .cpuid_model = 0x587, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 8, + .cache_write_cycles = 8, + .atclk_div = 30 + }, { .name = "", 0 } } }, @@ -3683,9 +4441,57 @@ const cpu_family_t cpu_families[] = { .name = "K5 (Model 0)", .internal_name = "k5_ssa5", .cpus = (const CPU[]) { - {"75 (PR75)", CPU_K5, fpus_internal, 75000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"90 (PR90)", CPU_K5, fpus_internal, 90000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"100 (PR100)", CPU_K5, fpus_internal, 100000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, + { + .name = "75 (PR75)", + .cpu_type = CPU_K5, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x501, + .cpuid_model = 0x501, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 9 + }, + { + .name = "90 (PR90)", + .cpu_type = CPU_K5, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x501, + .cpuid_model = 0x501, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 21/2 + }, + { + .name = "100 (PR100)", + .cpu_type = CPU_K5, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 3520, + .edx_reset = 0x501, + .cpuid_model = 0x501, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, { .name = "", 0 } } }, @@ -3695,11 +4501,91 @@ const cpu_family_t cpu_families[] = { .name = "K5 (Model 1/2/3)", .internal_name = "k5_5k86", .cpus = (const CPU[]) { - {"90 (PR120)", CPU_5K86, fpus_internal, 120000000, 2.0, 3520, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"100 (PR133)", CPU_5K86, fpus_internal, 133333333, 2.0, 3520, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"105 (PR150)", CPU_5K86, fpus_internal, 150000000, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, - {"116.7 (PR166)", CPU_5K86, fpus_internal, 166666666, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, - {"133 (PR200)", CPU_5K86, fpus_internal, 200000000, 3.0, 3520, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, + { + .name = "90 (PR120)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x511, + .cpuid_model = 0x511, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "100 (PR133)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x514, + .cpuid_model = 0x514, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "105 (PR150)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 35/2 + }, + { + .name = "116.7 (PR166)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 3520, + .edx_reset = 0x524, + .cpuid_model = 0x524, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "133 (PR200)", + .cpu_type = CPU_5K86, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 3520, + .edx_reset = 0x534, + .cpuid_model = 0x534, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, { .name = "", 0 } } }, @@ -3710,12 +4596,108 @@ const cpu_family_t cpu_families[] = { .name = "K6 (Model 6)", .internal_name = "k6_m6", .cpus = (const CPU[]) { - {"66", CPU_K6, fpus_internal, 66666666, 1.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ - {"100", CPU_K6, fpus_internal, 100000000, 1.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6, fpus_internal, 133333333, 2.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6, fpus_internal, 166666666, 2.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"200", CPU_K6, fpus_internal, 200000000, 3.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_K6, fpus_internal, 233333333, 3.5, 3200, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + { /* out of spec */ + .name = "66", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 1.0, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 8 + }, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "166", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "200", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 3200, + .edx_reset = 0x561, + .cpuid_model = 0x561, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, { .name = "", 0 } } }, { @@ -3724,13 +4706,117 @@ const cpu_family_t cpu_families[] = { .name = "K6 (Model 7)", .internal_name = "k6_m7", .cpus = (const CPU[]) { - {"100", CPU_K6, fpus_internal, 100000000, 1.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6, fpus_internal, 133333333, 2.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6, fpus_internal, 166666666, 2.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6, fpus_internal, 200000000, 3.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"233", CPU_K6, fpus_internal, 233333333, 3.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"266", CPU_K6, fpus_internal, 266666666, 4.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_K6, fpus_internal, 300000000, 4.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 166666666, .multi = 2.5, + .voltage = 2200, .edx_reset = 0x570, + .cpuid_model = 0x570, .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "200", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 200000000, .multi = 3.0, + .voltage = 2200, .edx_reset = 0x570, + .cpuid_model = 0x570, .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 233333333, .multi = 3.5, + .voltage = 2200, .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { + .name = "266", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { + .name = "300", + .cpu_type = CPU_K6, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 4.5, + .voltage = 2200, + .edx_reset = 0x570, + .cpuid_model = 0x570, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 13, + .cache_write_cycles = 13, + .atclk_div = 36 + }, { .name = "", 0 } } }, @@ -3740,24 +4826,312 @@ const cpu_family_t cpu_families[] = { .name = "K6-2", .internal_name = "k6_2", .cpus = (const CPU[]) { - {"100", CPU_K6_2, fpus_internal, 100000000, 1.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6_2, fpus_internal, 133333333, 2.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_2, fpus_internal, 166666666, 2.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_2, fpus_internal, 200000000, 3.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_2, fpus_internal, 233333333, 3.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, - {"266", CPU_K6_2, fpus_internal, 266666666, 4.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, - {"300", CPU_K6_2, fpus_internal, 300000000, 3.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, - {"333", CPU_K6_2, fpus_internal, 332500000, 3.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, - {"350", CPU_K6_2C, fpus_internal, 350000000, 3.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, - {"366", CPU_K6_2C, fpus_internal, 366666666, 5.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, - {"380", CPU_K6_2C, fpus_internal, 380000000, 4.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, - {"400/66", CPU_K6_2C, fpus_internal, 400000000, 6.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"400/100", CPU_K6_2C, fpus_internal, 400000000, 4.0, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"450", CPU_K6_2C, fpus_internal, 450000000, 4.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"475", CPU_K6_2C, fpus_internal, 475000000, 5.0, 2400, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"500", CPU_K6_2C, fpus_internal, 500000000, 5.0, 2400, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"533", CPU_K6_2C, fpus_internal, 533333333, 5.5, 2200, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, - {"550", CPU_K6_2C, fpus_internal, 550000000, 5.5, 2300, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { + .name = "233", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { + .name = "266", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { + .name = "300", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, + { + .name = "333", + .cpu_type = CPU_K6_2, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x580, + .cpuid_model = 0x580, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 40 + }, + { + .name = "350", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 42 + }, + { + .name = "366", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 44 + }, + { + .name = "380", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 46 + }, + { + .name = "400/66", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 6.0, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "400/100", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "450", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, + { + .name = "475", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 475000000, + .multi = 5.0, + .voltage = 2400, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 43, + .mem_write_cycles = 43, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 57 + }, + { + .name = "500", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2400, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, + { + .name = "533", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 533333333, + .multi = 5.5, + .voltage = 2200, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 48, + .mem_write_cycles = 48, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 64 + }, + { + .name = "550", + .cpu_type = CPU_K6_2C, + .fpus = fpus_internal, + .rspeed = 550000000, + .multi = 5.5, + .voltage = 2300, + .edx_reset = 0x58c, + .cpuid_model = 0x58c, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 50, + .mem_write_cycles = 50, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 66 + }, { .name = "", 0 } } }, { @@ -3766,24 +5140,312 @@ const cpu_family_t cpu_families[] = { .name = "K6-2+", .internal_name = "k6_2p", .cpus = (const CPU[]) { - {"100", CPU_K6_2P, fpus_internal, 100000000, 1.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6_2P, fpus_internal, 133333333, 2.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_2P, fpus_internal, 166666666, 2.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_2P, fpus_internal, 200000000, 3.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_2P, fpus_internal, 233333333, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ - {"266", CPU_K6_2P, fpus_internal, 266666666, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ - {"300", CPU_K6_2P, fpus_internal, 300000000, 3.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ - {"333", CPU_K6_2P, fpus_internal, 332500000, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ - {"350", CPU_K6_2P, fpus_internal, 350000000, 3.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ - {"366", CPU_K6_2P, fpus_internal, 366666666, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ - {"380", CPU_K6_2P, fpus_internal, 380000000, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ - {"400/66", CPU_K6_2P, fpus_internal, 400000000, 6.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, /* out of spec */ - {"400/100", CPU_K6_2P, fpus_internal, 400000000, 4.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, /* out of spec */ - {"450", CPU_K6_2P, fpus_internal, 450000000, 4.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"475", CPU_K6_2P, fpus_internal, 475000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"500", CPU_K6_2P, fpus_internal, 500000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"533", CPU_K6_2P, fpus_internal, 533333333, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, - {"550", CPU_K6_2P, fpus_internal, 550000000, 5.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "233", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { /* out of spec */ + .name = "266", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { /* out of spec */ + .name = "300", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, + { /* out of spec */ + .name = "333", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 40 + }, + { /* out of spec */ + .name = "350", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 42 + }, + { /* out of spec */ + .name = "366", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 44 + }, + { /* out of spec */ + .name = "380", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 46 + }, + { /* out of spec */ + .name = "400/66", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 6.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { /* out of spec */ + .name = "400/100", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "450", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, + { + .name = "475", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 475000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 43, + .mem_write_cycles = 43, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 57 + }, + { + .name = "500", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, + { + .name = "533", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 533333333, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 48, + .mem_write_cycles = 48, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 64 + }, + { + .name = "550", + .cpu_type = CPU_K6_2P, + .fpus = fpus_internal, + .rspeed = 550000000, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d4, + .cpuid_model = 0x5d4, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 50, + .mem_write_cycles = 50, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 66 + }, { .name = "", 0 } } }, { @@ -3792,19 +5454,227 @@ const cpu_family_t cpu_families[] = { .name = "K6-III", .internal_name = "k6_3", .cpus = (const CPU[]) { - {"100", CPU_K6_3, fpus_internal, 100000000, 1.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ - {"133", CPU_K6_3, fpus_internal, 133333333, 2.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_3, fpus_internal, 166666666, 2.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_3, fpus_internal, 200000000, 3.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_3, fpus_internal, 233333333, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ - {"266", CPU_K6_3, fpus_internal, 266666666, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ - {"300", CPU_K6_3, fpus_internal, 300000000, 3.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ - {"333", CPU_K6_3, fpus_internal, 332500000, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ - {"350", CPU_K6_3, fpus_internal, 350000000, 3.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ - {"366", CPU_K6_3, fpus_internal, 366666666, 5.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ - {"380", CPU_K6_3, fpus_internal, 380000000, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ - {"400", CPU_K6_3, fpus_internal, 400000000, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"450", CPU_K6_3, fpus_internal, 450000000, 4.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 9, + .mem_write_cycles = 9, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 12 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "233", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { /* out of spec */ + .name = "266", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { /* out of spec */ + .name = "300", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, + { /* out of spec */ + .name = "333", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 40 + }, + { /* out of spec */ + .name = "350", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 42 + }, + { /* out of spec */ + .name = "366", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 44 + }, + { /* out of spec */ + .name = "380", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 46 + }, + { + .name = "400", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "450", + .cpu_type = CPU_K6_3, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2200, + .edx_reset = 0x591, + .cpuid_model = 0x591, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, { .name = "", 0 } } }, @@ -3814,21 +5684,261 @@ const cpu_family_t cpu_families[] = { .name = "K6-III+", .internal_name = "k6_3p", .cpus = (const CPU[]) { - {"100", CPU_K6_3P, fpus_internal, 100000000, 1.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, /* out of spec */ - {"133", CPU_K6_3P, fpus_internal, 133333333, 2.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12, 12, 6, 6, 16}, /* out of spec */ - {"166", CPU_K6_3P, fpus_internal, 166666666, 2.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15, 15, 7, 7, 20}, /* out of spec */ - {"200", CPU_K6_3P, fpus_internal, 200000000, 3.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18, 18, 9, 9, 24}, /* out of spec */ - {"233", CPU_K6_3P, fpus_internal, 233333333, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, /* out of spec */ - {"266", CPU_K6_3P, fpus_internal, 266666666, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, /* out of spec */ - {"300", CPU_K6_3P, fpus_internal, 300000000, 3.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, /* out of spec */ - {"333", CPU_K6_3P, fpus_internal, 332500000, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, /* out of spec */ - {"350", CPU_K6_3P, fpus_internal, 350000000, 3.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, /* out of spec */ - {"366", CPU_K6_3P, fpus_internal, 366666666, 5.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, /* out of spec */ - {"380", CPU_K6_3P, fpus_internal, 380000000, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, /* out of spec */ - {"400", CPU_K6_3P, fpus_internal, 400000000, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"450", CPU_K6_3P, fpus_internal, 450000000, 4.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"475", CPU_K6_3P, fpus_internal, 475000000, 5.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"500", CPU_K6_3P, fpus_internal, 500000000, 5.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + { /* out of spec */ + .name = "100", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 1.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 9 + }, + { /* out of spec */ + .name = "133", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { /* out of spec */ + .name = "166", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { /* out of spec */ + .name = "200", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 200000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 24 + }, + { /* out of spec */ + .name = "233", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 10, + .cache_write_cycles = 10, + .atclk_div = 28 + }, + { /* out of spec */ + .name = "266", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 266666666, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 32 + }, + { /* out of spec */ + .name = "300", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, + { /* out of spec */ + .name = "333", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 332500000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 30, + .mem_write_cycles = 30, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 40 + }, + { /* out of spec */ + .name = "350", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 350000000, + .multi = 3.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 32, + .mem_write_cycles = 32, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 42 + }, + { /* out of spec */ + .name = "366", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 366666666, + .multi = 5.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 33, + .mem_write_cycles = 33, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 44 + }, + { /* out of spec */ + .name = "380", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 380000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 34, + .mem_write_cycles = 34, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 46 + }, + { + .name = "400", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 400000000, + .multi = 4.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 36, + .mem_write_cycles = 36, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 48 + }, + { + .name = "450", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 450000000, + .multi = 4.5, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 41, + .mem_write_cycles = 41, + .cache_read_cycles = 14, + .cache_write_cycles = 14, + .atclk_div = 54 + }, + { + .name = "475", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 475000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 43, + .mem_write_cycles = 43, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 57 + }, + { + .name = "500", + .cpu_type = CPU_K6_3P, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2000, + .edx_reset = 0x5d0, + .cpuid_model = 0x5d0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, { .name = "", 0 } } }, @@ -3839,12 +5949,108 @@ const cpu_family_t cpu_families[] = { .name = "Cx6x86", .internal_name = "cx6x86", .cpus = (const CPU[]) { - {"80 (PR90+)", CPU_Cx6x86, fpus_internal, 80000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, - {"100 (PR120+)", CPU_Cx6x86, fpus_internal, 100000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"110 (PR133+)", CPU_Cx6x86, fpus_internal, 110000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"120 (PR150+)", CPU_Cx6x86, fpus_internal, 120000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"133 (PR166+)", CPU_Cx6x86, fpus_internal, 133333333, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"150 (PR200+)", CPU_Cx6x86, fpus_internal, 150000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + { + .name = "80 (PR90+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, + { + .name = "100 (PR120+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 12 + }, + { + .name = "110 (PR133+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 110000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "120 (PR150+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133 (PR166+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "150 (PR200+)", + .cpu_type = CPU_Cx6x86, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.0, + .voltage = 3520, + .edx_reset = 0x520, + .cpuid_model = 0x520, + .cyrix_id = 0x1731, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 18 + }, { .name = "", 0 } } }, @@ -3854,10 +6060,74 @@ const cpu_family_t cpu_families[] = { .name = "Cx6x86L", .internal_name = "cx6x86l", .cpus = (const CPU[]) { - {"110 (PR133+)", CPU_Cx6x86L, fpus_internal, 110000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"120 (PR150+)", CPU_Cx6x86L, fpus_internal, 120000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"133 (PR166+)", CPU_Cx6x86L, fpus_internal, 133333333, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"150 (PR200+)", CPU_Cx6x86L, fpus_internal, 150000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + { + .name = "110 (PR133+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 110000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "120 (PR150+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 14 + }, + { + .name = "133 (PR166+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "150 (PR200+)", + .cpu_type = CPU_Cx6x86L, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 2.0, + .voltage = 2800, + .edx_reset = 0x540, + .cpuid_model = 0x540, + .cyrix_id = 0x2231, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 18 + }, { .name = "", 0 } } }, @@ -3867,10 +6137,74 @@ const cpu_family_t cpu_families[] = { .name = "Cx6x86MX", .internal_name = "cx6x86mx", .cpus = (const CPU[]) { - {"133 (PR166)", CPU_Cx6x86MX, fpus_internal, 133333333, 2.0, 2900, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"166 (PR200)", CPU_Cx6x86MX, fpus_internal, 166666666, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"187.5 (PR233)", CPU_Cx6x86MX, fpus_internal, 187500000, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, - {"208.3 (PR266)", CPU_Cx6x86MX, fpus_internal, 208333333, 2.5, 2700, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, + { + .name = "133 (PR166)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 2.0, + .voltage = 2900, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0451, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 16 + }, + { + .name = "166 (PR200)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 166666666, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0452, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 20 + }, + { + .name = "187.5 (PR233)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 187500000, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0452, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 45/2 + }, + { + .name = "208.3 (PR266)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 208333333, + .multi = 2.5, + .voltage = 2700, + .edx_reset = 0x600, + .cpuid_model = 0x600, + .cyrix_id = 0x0452, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 17, + .mem_write_cycles = 17, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 25 + }, { .name = "", 0 } } }, @@ -3880,11 +6214,91 @@ const cpu_family_t cpu_families[] = { .name = "MII", .internal_name = "mii", .cpus = (const CPU[]) { - {"233 (PR300)", CPU_Cx6x86MX, fpus_internal, 233333333, 3.5, 2900, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, - {"250/83 (PR333)", CPU_Cx6x86MX, fpus_internal, 250000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, - {"250/100 (PR366)", CPU_Cx6x86MX, fpus_internal, 250000000, 2.5, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30}, - {"285 (PR400)", CPU_Cx6x86MX, fpus_internal, 285000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34}, - {"300 (PR433)", CPU_Cx6x86MX, fpus_internal, 300000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, + { + .name = "233 (PR300)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 233333333, + .multi = 3.5, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0852, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 11, + .cache_write_cycles = 11, + .atclk_div = 28 + }, + { + .name = "250/83 (PR333)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 23, + .mem_write_cycles = 23, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 30 + }, + { + .name = "250/100 (PR366)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 250000000, + .multi = 2.5, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 23, + .mem_write_cycles = 23, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 30 + }, + { + .name = "285 (PR400)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 285000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 34 + }, + { + .name = "300 (PR433)", + .cpu_type = CPU_Cx6x86MX, + .fpus = fpus_internal, + .rspeed = 300000000, + .multi = 3.0, + .voltage = 2900, + .edx_reset = 0x601, + .cpuid_model = 0x601, + .cyrix_id = 0x0853, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 27, + .mem_write_cycles = 27, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 36 + }, { .name = "", 0 } } },