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Implemented MSRs

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This commit is contained in:
nerd73
2020-03-21 23:42:01 -06:00
parent 746b5e42ff
commit 172f85ad40
2 changed files with 95 additions and 48 deletions
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131
src/cpu_common/cpu.c
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@@ -177,11 +177,6 @@ uint64_t pmc[2] = {0, 0};
uint16_t temp_seg_data[4] = {0, 0, 0, 0}; uint16_t temp_seg_data[4] = {0, 0, 0, 0};
#if defined(DEV_BRANCH) && defined(USE_I686)
uint16_t cs_msr = 0;
uint32_t esp_msr = 0;
uint32_t eip_msr = 0;
uint64_t apic_base_msr = 0;
uint64_t mtrr_cap_msr = 0; uint64_t mtrr_cap_msr = 0;
uint64_t mtrr_physbase_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0}; uint64_t mtrr_physbase_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0};
uint64_t mtrr_physmask_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0}; uint64_t mtrr_physmask_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0};
@@ -189,8 +184,14 @@ uint64_t mtrr_fix64k_8000_msr = 0;
uint64_t mtrr_fix16k_8000_msr = 0; uint64_t mtrr_fix16k_8000_msr = 0;
uint64_t mtrr_fix16k_a000_msr = 0; uint64_t mtrr_fix16k_a000_msr = 0;
uint64_t mtrr_fix4k_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0}; uint64_t mtrr_fix4k_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0};
uint64_t pat_msr = 0;
uint64_t mtrr_deftype_msr = 0; uint64_t mtrr_deftype_msr = 0;
#if defined(DEV_BRANCH) && defined(USE_I686)
uint16_t cs_msr = 0;
uint32_t esp_msr = 0;
uint32_t eip_msr = 0;
uint64_t apic_base_msr = 0;
uint64_t pat_msr = 0;
uint64_t msr_ia32_pmc[8] = {0, 0, 0, 0, 0, 0, 0, 0}; uint64_t msr_ia32_pmc[8] = {0, 0, 0, 0, 0, 0, 0, 0};
uint64_t ecx17_msr = 0; uint64_t ecx17_msr = 0;
uint64_t ecx79_msr = 0; uint64_t ecx79_msr = 0;
@@ -2483,29 +2484,76 @@ void cpu_RDMSR()
EAX = EDX = 0; EAX = EDX = 0;
switch (ECX) switch (ECX)
{ {
case 0x02:
EAX = msr.tr1;
break;
case 0x0e:
EAX = msr.tr12;
break;
case 0x10: case 0x10:
EAX = tsc & 0xffffffff; EAX = tsc & 0xffffffff;
EDX = tsc >> 32; EDX = tsc >> 32;
break; break;
case 0x11: case 0x2a:
EAX = msr.cesr; if (cpu_dmulti == 3)
EAX = ((0 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
else if (cpu_dmulti == 3.5)
EAX = ((0 << 25) | (1 << 24) | (0 << 23) | (1 << 22));
else if (cpu_dmulti == 4)
EAX = ((0 << 25) | (0 << 24) | (1 << 23) | (0 << 22));
else if (cpu_dmulti == 4.5)
EAX = ((0 << 25) | (1 << 24) | (1 << 23) | (0 << 22));
else if (cpu_dmulti == 5)
EAX = 0;
else if (cpu_dmulti == 5.5)
EAX = ((0 << 25) | (1 << 24) | (0 << 23) | (0 << 22));
else if (cpu_dmulti == 6)
EAX = ((1 << 25) | (0 << 24) | (1 << 23) | (1 << 22));
else if (cpu_dmulti == 6.5)
EAX = ((1 << 25) | (1 << 24) | (1 << 23) | (1 << 22));
else if (cpu_dmulti == 7)
EAX = ((1 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
else
EAX = ((0 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
break; break;
case 0x1107: case 0x1107:
EAX = msr.fcr; EAX = msr.fcr;
break; break;
case 0x108: case 0x1108:
EAX = msr.fcr2 & 0xffffffff; EAX = msr.fcr2 & 0xffffffff;
EDX = msr.fcr2 >> 32; EDX = msr.fcr2 >> 32;
break; break;
case 0x10a: case 0x200: case 0x201: case 0x202: case 0x203: case 0x204: case 0x205: case 0x206: case 0x207:
EAX = cpu_multi & 3; case 0x208: case 0x209: case 0x20A: case 0x20B: case 0x20C: case 0x20D: case 0x20E: case 0x20F:
if (ECX & 1)
{
EAX = mtrr_physmask_msr[(ECX - 0x200) >> 1] & 0xffffffff;
EDX = mtrr_physmask_msr[(ECX - 0x200) >> 1] >> 32;
}
else
{
EAX = mtrr_physbase_msr[(ECX - 0x200) >> 1] & 0xffffffff;
EDX = mtrr_physbase_msr[(ECX - 0x200) >> 1] >> 32;
}
break; break;
case 0x250:
EAX = mtrr_fix64k_8000_msr & 0xffffffff;
EDX = mtrr_fix64k_8000_msr >> 32;
break;
case 0x258:
EAX = mtrr_fix16k_8000_msr & 0xffffffff;
EDX = mtrr_fix16k_8000_msr >> 32;
break;
case 0x259:
EAX = mtrr_fix16k_a000_msr & 0xffffffff;
EDX = mtrr_fix16k_a000_msr >> 32;
break;
case 0x268: case 0x269: case 0x26A: case 0x26B: case 0x26C: case 0x26D: case 0x26E: case 0x26F:
EAX = mtrr_fix4k_msr[ECX - 0x268] & 0xffffffff;
EDX = mtrr_fix4k_msr[ECX - 0x268] >> 32;
break;
case 0x277:
EAX = pat_msr & 0xffffffff;
EDX = pat_msr >> 32;
break;
case 0x2FF:
EAX = mtrr_deftype_msr & 0xffffffff;
EDX = mtrr_deftype_msr >> 32;
break;
} }
break; break;
@@ -2940,45 +2988,44 @@ void cpu_WRMSR()
case CPU_CYRIX3S: case CPU_CYRIX3S:
switch (ECX) switch (ECX)
{ {
case 0x02:
msr.tr1 = EAX & 2;
break;
case 0x0e:
msr.tr12 = EAX & 0x228;
break;
case 0x10: case 0x10:
tsc = EAX | ((uint64_t)EDX << 32); tsc = EAX | ((uint64_t)EDX << 32);
break; break;
case 0x11:
msr.cesr = EAX & 0xff00ff;
break;
case 0x1107: case 0x1107:
msr.fcr = EAX; msr.fcr = EAX;
if (EAX & (1 << 9))
cpu_features |= CPU_FEATURE_MMX;
else
cpu_features &= ~CPU_FEATURE_MMX;
if (EAX & (1 << 1)) if (EAX & (1 << 1))
cpu_features |= CPU_FEATURE_CX8; cpu_features |= CPU_FEATURE_CX8;
else else
cpu_features &= ~CPU_FEATURE_CX8; cpu_features &= ~CPU_FEATURE_CX8;
#ifdef USE_NEW_DYNAREC
if (EAX & (1 << 20))
cpu_features |= CPU_FEATURE_3DNOW;
else
cpu_features &= ~CPU_FEATURE_3DNOW;
#endif
if (EAX & (1 << 29))
CPUID = 0;
else
CPUID = machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpuid_model;
break; break;
case 0x108: case 0x1108:
msr.fcr2 = EAX | ((uint64_t)EDX << 32); msr.fcr2 = EAX | ((uint64_t)EDX << 32);
break; break;
case 0x109: case 0x1109:
msr.fcr3 = EAX | ((uint64_t)EDX << 32); msr.fcr3 = EAX | ((uint64_t)EDX << 32);
break; break;
case 0x200: case 0x201: case 0x202: case 0x203: case 0x204: case 0x205: case 0x206: case 0x207:
case 0x208: case 0x209: case 0x20A: case 0x20B: case 0x20C: case 0x20D: case 0x20E: case 0x20F:
if (ECX & 1)
mtrr_physmask_msr[(ECX - 0x200) >> 1] = EAX | ((uint64_t)EDX << 32);
else
mtrr_physbase_msr[(ECX - 0x200) >> 1] = EAX | ((uint64_t)EDX << 32);
break;
case 0x250:
mtrr_fix64k_8000_msr = EAX | ((uint64_t)EDX << 32);
break;
case 0x258:
mtrr_fix16k_8000_msr = EAX | ((uint64_t)EDX << 32);
break;
case 0x259:
mtrr_fix16k_a000_msr = EAX | ((uint64_t)EDX << 32);
break;
case 0x268: case 0x269: case 0x26A: case 0x26B: case 0x26C: case 0x26D: case 0x26E: case 0x26F:
mtrr_fix4k_msr[ECX - 0x268] = EAX | ((uint64_t)EDX << 32);
break;
case 0x2FF:
mtrr_deftype_msr = EAX | ((uint64_t)EDX << 32);
break;
} }
break; break;

12
src/cpu_common/cpu_table.c
View File

@@ -721,17 +721,17 @@ CPU cpus_PentiumII[] = {
CPU cpus_Cyrix3[] = { CPU cpus_Cyrix3[] = {
/*VIA Cyrix III (Samuel)*/ /*VIA Cyrix III (Samuel)*/
{"Cyrix III 66", CPU_CYRIX3S, 66666666, 1, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 8}, /*66 MHz version*/ {"Cyrix III 66", CPU_CYRIX3S, 66666666, 1, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 8}, /*66 MHz version*/
{"Cyrix III 233", CPU_CYRIX3S, 233333333, 7/2, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, 28}, {"Cyrix III 233", CPU_CYRIX3S, 233333333, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, 28},
{"Cyrix III 266", CPU_CYRIX3S, 266666666, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32}, {"Cyrix III 266", CPU_CYRIX3S, 266666666, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32},
{"Cyrix III 300", CPU_CYRIX3S, 300000000, 9/2, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36}, {"Cyrix III 300", CPU_CYRIX3S, 300000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36},
{"Cyrix III 333", CPU_CYRIX3S, 333333333, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40}, {"Cyrix III 333", CPU_CYRIX3S, 333333333, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40},
{"Cyrix III 350", CPU_CYRIX3S, 350000000, 7/2, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42}, {"Cyrix III 350", CPU_CYRIX3S, 350000000, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42},
{"Cyrix III 400", CPU_CYRIX3S, 400000000, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48}, {"Cyrix III 400", CPU_CYRIX3S, 400000000, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48},
{"Cyrix III 450", CPU_CYRIX3S, 450000000, 9/2, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/ {"Cyrix III 450", CPU_CYRIX3S, 450000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/
{"Cyrix III 500", CPU_CYRIX3S, 500000000, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60}, {"Cyrix III 500", CPU_CYRIX3S, 500000000, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60},
{"Cyrix III 550", CPU_CYRIX3S, 550000000, 11/2, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66}, {"Cyrix III 550", CPU_CYRIX3S, 550000000, 5.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66},
{"Cyrix III 600", CPU_CYRIX3S, 600000000, 6, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72}, {"Cyrix III 600", CPU_CYRIX3S, 600000000, 6, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72},
{"Cyrix III 650", CPU_CYRIX3S, 650000000, 13/2, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78}, {"Cyrix III 650", CPU_CYRIX3S, 650000000, 6.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78},
{"Cyrix III 700", CPU_CYRIX3S, 700000000, 7, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84}, {"Cyrix III 700", CPU_CYRIX3S, 700000000, 7, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
}; };