@@ -1636,7 +1636,7 @@ gd543x_recalc_mapping(gd54xx_t *gd54xx)
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uint32_t base;
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uint32_t size;
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if ((gd54xx->pci && (!(gd54xx->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))) || (gd54xx->mca && (!(gd54xx->pos_regs[2] & 1)))) {
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if (gd54xx->pci && (!(gd54xx->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))) {
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mem_mapping_disable(&svga->mapping);
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mem_mapping_disable(&gd54xx->linear_mapping);
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mem_mapping_disable(&gd54xx->mmio_mapping);
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@@ -3863,13 +3863,16 @@ gd5428_mca_write(int port, uint8_t val, void *priv)
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return;
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gd54xx->pos_regs[port & 7] = val;
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gd543x_recalc_mapping(gd54xx);
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mem_mapping_disable(&gd54xx->bios_rom.mapping);
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if (gd54xx->pos_regs[2] & 0x01)
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mem_mapping_enable(&gd54xx->bios_rom.mapping);
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}
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static uint8_t
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gd5428_mca_feedb(UNUSED(void *priv))
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gd5428_mca_feedb(void *priv)
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{
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return 1;
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gd54xx_t *gd54xx = (gd54xx_t *) priv;
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return gd54xx->pos_regs[2] & 0x01;
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}
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static void
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@@ -3891,7 +3894,7 @@ gd54xx_reset(void *priv)
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io_sethandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx);
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mem_mapping_disable(&gd54xx->vgablt_mapping);
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if (gd54xx->has_bios && gd54xx->pci)
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if (gd54xx->has_bios && (gd54xx->pci || gd54xx->mca))
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mem_mapping_disable(&gd54xx->bios_rom.mapping);
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memset(gd54xx->pci_regs, 0x00, 256);
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@@ -4235,6 +4238,7 @@ gd54xx_init(const device_t *info)
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if (gd54xx->mca) {
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gd54xx->pos_regs[0] = svga->crtc[0x27] == CIRRUS_ID_CLGD5426 ? 0x82 : 0x7b;
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gd54xx->pos_regs[1] = svga->crtc[0x27] == CIRRUS_ID_CLGD5426 ? 0x81 : 0x91;
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mem_mapping_disable(&gd54xx->bios_rom.mapping);
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mca_add(gd5428_mca_read, gd5428_mca_write, gd5428_mca_feedb, NULL, gd54xx);
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io_sethandler(0x46e8, 0x0001, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx);
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}
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