80486DX2-66/86Box-fork
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Fixes from OBattler

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This commit is contained in:
Melissa Goad
2020-01-12 20:36:38 -06:00
parent aa73f2215f
commit 199db4acbe
1 changed files with 130 additions and 101 deletions
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229
src/chipset/via_mvp3.c
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@@ -30,60 +30,35 @@
#include "../keyboard.h" #include "../keyboard.h"
#include "chipset.h" #include "chipset.h"
typedef struct via_mvp3_t typedef struct via_mvp3_t
{ {
uint8_t pci_conf[2][256]; uint8_t pci_conf[2][256];
} via_mvp3_t; } via_mvp3_t;
static void static void
via_mvp3_recalcmapping(via_mvp3_t *dev) mvp3_map(uint32_t addr, uint32_t size, int state)
{ {
int c, d; switch (state & 3) {
uint32_t base; case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
for (c = 0; c < 2; c++) { break;
for (d = 0; d < 4; d++) { case 1:
base = 0xc0000 + (d << 14); mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
switch (dev->pci_conf[0][0x61 + c] & (3 << (d << 1))) { break;
case 0x00: case 2:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break; break;
case 0x01: case 3:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break; break;
case 0x02:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 0x03:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
}
}
for(d = 0; d < 2; d++)
{
base = 0xe0000 + (d << 16);
switch (dev->pci_conf[0][0x63] & (3 << (d << 1))) {
case 0x00:
mem_set_mem_state(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0x01:
mem_set_mem_state(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 0x02:
mem_set_mem_state(base, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 0x03:
mem_set_mem_state(base, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
} }
flushmmucache_nopc(); flushmmucache_nopc();
shadowbios = 1;
} }
static void static void
via_mvp3_setup(via_mvp3_t *dev) via_mvp3_setup(via_mvp3_t *dev)
{ {
@@ -158,108 +133,160 @@ via_mvp3_setup(via_mvp3_t *dev)
dev->pci_conf[1][0x25] = 0xff; dev->pci_conf[1][0x25] = 0xff;
} }
static void static void
via_mvp3_host_bridge_write(int func, int addr, uint8_t val, void *priv) via_mvp3_host_bridge_write(int func, int addr, uint8_t val, void *priv)
{ {
via_mvp3_t *dev = (via_mvp3_t *) priv; via_mvp3_t *dev = (via_mvp3_t *) priv;
if (func) if (func)
return; return;
/*Read-only addresses*/ /*Read-only addresses*/
if ((addr < 4) || (addr >= 5 && addr < 7) if ((addr < 4) || ((addr >= 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) ||
|| (addr >= 8 && addr < 0xd) ((addr >= 0xe) && (addr < 0x12)) || ((addr >= 0x14) && (addr < 0x50)) ||
|| (addr >= 0xe && addr < 0x12) ((addr >= 0x79) && (addr < 0x7e)) || ((addr >= 0x85) && (addr < 0x88)) ||
|| (addr >= 0x14 && addr < 0x50) ((addr >= 0x8c) && (addr < 0xa8)) || ((addr >= 0xad) && (addr < 0xfd)))
|| (addr >= 0x79 && addr < 0x7e) return;
|| (addr >= 0x85 && addr < 0x88)
|| (addr >= 0x8c && addr < 0xa8)
|| (addr >= 0xad && addr < 0xfd))
return;
switch(addr) switch(addr) {
{ case 0x04:
case 0x04: dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40);
dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40); break;
break; case 0x07:
case 0x07: dev->pci_conf[0][0x07] &= ~(val & 0xb0);
dev->pci_conf[0][0x07] &= ~(val & 0xb0); break;
case 0x61: case 0x62: case 0x63:
dev->pci_conf[0][addr] = val; case 0x12: /* Graphics Aperture Base */
via_mvp3_recalcmapping(dev); dev->pci_conf[0][0x12] = (val & 0xf0);
break; break;
default: case 0x13: /* Graphics Aperture Base */
dev->pci_conf[0][addr] = val; dev->pci_conf[0][0x13] = val;
break; break;
case 0x61: /* Shadow RAM Control 1 */
if ((dev->pci_conf[0][0x61] ^ val) & 0x03)
mvp3_map(0xc0000, 0x04000, val & 0x03);
if ((dev->pci_conf[0][0x61] ^ val) & 0x0c)
mvp3_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
if ((dev->pci_conf[0][0x61] ^ val) & 0x30)
mvp3_map(0xc8000, 0x04000, (val & 0x30) >> 4);
if ((dev->pci_conf[0][0x61] ^ val) & 0xc0)
mvp3_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
dev->pci_conf[0][0x61] = val;
return;
case 0x62: /* Shadow RAM Control 2 */
if ((dev->pci_conf[0][0x62] ^ val) & 0x03)
mvp3_map(0xd0000, 0x04000, val & 0x03);
if ((dev->pci_conf[0][0x62] ^ val) & 0x0c)
mvp3_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
if ((dev->pci_conf[0][0x62] ^ val) & 0x30)
mvp3_map(0xd8000, 0x04000, (val & 0x30) >> 4);
if ((dev->pci_conf[0][0x62] ^ val) & 0xc0)
mvp3_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
dev->pci_conf[0][0x62] = val;
return;
case 0x63: /* Shadow RAM Control 3 */
if ((dev->pci_conf[0][0x63] ^ val) & 0x30) {
mvp3_map(0xf0000, 0x10000, (val & 0x30) >> 4);
shadowbios = (((val & 0x30) >> 4) & 0x02);
}
if ((dev->pci_conf[0][0x63] ^ val) & 0xc0)
mvp3_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
dev->pci_conf[0][0x63] = val;
return;
default:
dev->pci_conf[0][addr] = val;
break;
} }
} }
static void static void
via_mvp3_pci_bridge_write(int func, int addr, uint8_t val, void *priv) via_mvp3_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
{ {
via_mvp3_t *dev = (via_mvp3_t *) priv; via_mvp3_t *dev = (via_mvp3_t *) priv;
if(func != 1) return; if (func != 1)
return;
/*Read-only addresses*/ /*Read-only addresses*/
if ((addr < 4) || (addr >= 5 && addr < 7) if ((addr < 4) || ((addr >= 5) && (addr < 7)) ||
|| (addr >= 8 && addr < 0x18) ((addr >= 8) && (addr < 0x18)) || (addr == 0x1b) ||
|| (addr == 0x1b) ((addr >= 0x1e) && (addr < 0x20)) || ((addr >= 0x28) && (addr < 0x3e)) ||
|| (addr >= 0x1e && addr < 0x20) (addr >= 0x43))
|| (addr >= 0x28 && addr < 0x3e) return;
|| (addr >= 0x43))
return;
switch(addr) switch(addr) {
{ case 0x04:
case 0x04: dev->pci_conf[1][0x04] = (dev->pci_conf[1][0x04] & ~0x47) | (val & 0x47);
dev->pci_conf[1][0x04] = (dev->pci_conf[1][0x04] & ~0x47) | (val & 0x47); break;
break; case 0x07:
case 0x07: dev->pci_conf[1][0x07] &= ~(val & 0x30);
dev->pci_conf[1][0x07] &= ~(val & 0x30); break;
default:
dev->pci_conf[1][addr] = val; case 0x20: /* Memory Base */
break; dev->pci_conf[1][0x20] = val & 0xf0;
break;
case 0x22: /* Memory Limit */
dev->pci_conf[1][0x22] = val & 0xf0;
break;
case 0x24: /* Prefetchable Memory Base */
dev->pci_conf[1][0x24] = val & 0xf0;
break;
case 0x26: /* Prefetchable Memory Limit */
dev->pci_conf[1][0x26] = val & 0xf0;
break;
default:
dev->pci_conf[1][addr] = val;
break;
} }
} }
static uint8_t static uint8_t
via_mvp3_read(int func, int addr, void *priv) via_mvp3_read(int func, int addr, void *priv)
{ {
via_mvp3_t *dev = (via_mvp3_t *) priv; via_mvp3_t *dev = (via_mvp3_t *) priv;
uint8_t ret = 0xff;
switch(func) switch(func) {
{ case 0:
case 0: return dev->pci_conf[0][addr]; ret = dev->pci_conf[0][addr];
case 1: return dev->pci_conf[1][addr]; break;
default: return 0xff; case 1:
ret = dev->pci_conf[1][addr];
break;
} }
return ret;
} }
static void static void
via_mvp3_write(int func, int addr, uint8_t val, void *priv) via_mvp3_write(int func, int addr, uint8_t val, void *priv)
{ {
switch(func) switch(func) {
{ case 0:
case 0: via_mvp3_host_bridge_write(func, addr, val, priv);
via_mvp3_host_bridge_write(func, addr, val, priv); break;
break; case 1:
case 1: via_mvp3_pci_bridge_write(func, addr, val, priv);
via_mvp3_pci_bridge_write(func, addr, val, priv); break;
break;
} }
} }
static void static void
via_mvp3_reset(void *priv) via_mvp3_reset(void *priv)
{ {
via_mvp3_t *dev = (via_mvp3_t *) priv; via_mvp3_write(0, 0x63, via_mvp3_read(0, 0x63, priv) & 0xcf, priv);
via_mvp3_setup(dev);
} }
static void * static void *
via_mvp3_init(const device_t *info) via_mvp3_init(const device_t *info)
{ {
@@ -272,6 +299,7 @@ via_mvp3_init(const device_t *info)
return dev; return dev;
} }
static void static void
via_mvp3_close(void *priv) via_mvp3_close(void *priv)
{ {
@@ -280,6 +308,7 @@ via_mvp3_close(void *priv)
free(dev); free(dev);
} }
const device_t via_mvp3_device = const device_t via_mvp3_device =
{ {
"VIA MVP3", "VIA MVP3",