Merge pull request #867 from 86Box/bugfix/s3_911_win3x
Evidently pixel cntl 0x80 (CPU data determines mix register) isn't ha…
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@@ -695,7 +695,7 @@ static void s3_accel_out_fifo_w(s3_t *s3, uint16_t port, uint16_t val)
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{
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{
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if (s3->accel.cmd & 0x100)
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if (s3->accel.cmd & 0x100)
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{
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{
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if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80)
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if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80 && (s3->chip != S3_86C911))
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{
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{
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if (s3->accel.cmd & 0x1000)
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if (s3->accel.cmd & 0x1000)
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val = (val >> 8) | (val << 8);
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val = (val >> 8) | (val << 8);
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@@ -704,7 +704,7 @@ static void s3_accel_out_fifo_w(s3_t *s3, uint16_t port, uint16_t val)
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s3_accel_start(8, 1, (val >> 8) & 0xff, 0, s3);
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s3_accel_start(8, 1, (val >> 8) & 0xff, 0, s3);
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s3_accel_start(8, 1, val & 0xff, 0, s3);
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s3_accel_start(8, 1, val & 0xff, 0, s3);
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}
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}
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if ((s3->accel.cmd & 0x600) == 0x000)
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else if ((s3->accel.cmd & 0x600) == 0x000)
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s3_accel_start(8, 1, val | (val << 16), 0, s3);
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s3_accel_start(8, 1, val | (val << 16), 0, s3);
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else
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else
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s3_accel_start(16, 1, val | (val << 16), 0, s3);
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s3_accel_start(16, 1, val | (val << 16), 0, s3);
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