Implement missing Pentium MSRs
Includes obscure behavior, like undocumented "high" MSRs
This commit is contained in:
Alexander Babikov
299
src/cpu/cpu.c
299
src/cpu/cpu.c
@@ -248,8 +248,7 @@ uint32_t cache_index = 0;
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uint8_t _cache[2048];
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uint8_t _cache[2048];
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uint64_t cpu_CR4_mask;
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uint64_t cpu_CR4_mask;
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uint64_t tsc = 0;
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uint64_t tsc = 0;
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uint64_t pmc[2] = { 0, 0 };
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double cpu_dmulti;
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double cpu_dmulti;
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double cpu_busspeed;
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double cpu_busspeed;
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@@ -2824,17 +2823,159 @@ amd_k_invalid_rdmsr:
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case CPU_PENTIUM:
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case CPU_PENTIUM:
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case CPU_PENTIUMMMX:
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case CPU_PENTIUMMMX:
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EAX = EDX = 0;
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EAX = EDX = 0;
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switch (ECX) {
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/* Filter out the upper 27 bits when ECX value is over 0x80000000, as per:
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Ralf Brown, Pentium Model-Specific Registers and What They Reveal.
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https://www.cs.cmu.edu/~ralf/papers/highmsr.html
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But leave the bit 31 intact to be able to handle both low and high
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MSRs in a single switch block. */
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switch (ECX & (ECX > 0x7fffffff ? 0x8000001f : 0x7fffffff)) {
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/* Machine Check Exception Address */
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/* Machine Check Exception Address */
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case 0x00:
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case 0x00000000:
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case 0x80000000:
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EAX = msr.mcar & 0xffffffff;
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EDX = msr.mcar >> 32;
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break;
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/* Machine Check Exception Type */
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/* Machine Check Exception Type */
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case 0x01:
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case 0x00000001:
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case 0x80000001:
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EAX = msr.mctr & 0xffffffff;
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EDX = msr.mctr >> 32;
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msr.mctr &= ~0x1; /* clear the machine check pending bit */
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break;
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/* TR1 - Parity Reversal Test Register */
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case 0x00000002:
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case 0x80000002:
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EAX = msr.tr1;
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break;
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/* TR2 - Instruction Cache End Bit */
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case 0x00000004:
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case 0x80000004:
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if (cpu_s->cpu_type == CPU_PENTIUMMMX)
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goto pentium_invalid_rdmsr;
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EAX = msr.tr2;
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break;
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/* TR3 - Cache Test Data */
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case 0x00000005:
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case 0x80000005:
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EAX = msr.tr3;
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break;
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/* TR4 - Cache Test Tag */
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case 0x00000006:
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case 0x80000006:
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EAX = msr.tr4;
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break;
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/* TR5 - Cache Test Control */
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case 0x00000007:
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case 0x80000007:
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EAX = msr.tr5;
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break;
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/* TR6 - TLB Test Command */
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case 0x00000008:
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case 0x80000008:
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EAX = msr.tr6;
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break;
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/* TR7 - TLB Test Data */
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case 0x00000009:
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case 0x80000009:
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EAX = msr.tr7;
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break;
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/* TR9 - Branch Target Buffer Tag */
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case 0x0000000b:
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case 0x8000000b:
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EAX = msr.tr9;
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break;
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/* TR10 - Branch Target Buffer Target */
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case 0x0000000c:
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case 0x8000000c:
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EAX = msr.tr10;
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break;
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/* TR11 - Branch Target Buffer Control */
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case 0x0000000d:
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case 0x8000000d:
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EAX = msr.tr11;
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break;
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/* TR12 - New Feature Control */
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case 0x0000000e:
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case 0x8000000e:
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EAX = msr.tr12;
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break;
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break;
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/* Time Stamp Counter */
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/* Time Stamp Counter */
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case 0x10:
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case 0x00000010:
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case 0x80000010:
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EAX = tsc & 0xffffffff;
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EAX = tsc & 0xffffffff;
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EDX = tsc >> 32;
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EDX = tsc >> 32;
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break;
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break;
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/* Performance Monitor - Control and Event Select */
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case 0x00000011:
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case 0x80000011:
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EAX = msr.cesr;
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break;
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/* Performance Monitor - Event Counter 0 */
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case 0x00000012:
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case 0x80000012:
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EAX = msr.pmc[0] & 0xffffffff;
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EDX = msr.pmc[0] >> 32;
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break;
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/* Performance Monitor - Event Counter 1 */
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case 0x00000013:
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case 0x80000013:
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EAX = msr.pmc[1] & 0xffffffff;
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EDX = msr.pmc[1] >> 32;
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break;
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/* Unknown */
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case 0x00000014:
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case 0x80000014:
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if ((CPUID & 0xfff) <= 0x520)
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goto pentium_invalid_rdmsr;
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break;
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/* Unknown, possibly paging-related; initial value is 0004h,
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becomes 0008h once paging is enabled */
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case 0x80000018:
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EAX = ((cr0 & (1 << 31)) ? 0x00000008 : 0x00000004);
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break;
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/* Floating point - last prefetched opcode
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bits 10-8: low three bits of first byte of FP instruction
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bits 7-0: second byte of floating-point instruction */
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case 0x80000019:
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EAX = 0;
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break;
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/* Floating point - last executed non-control opcode */
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case 0x8000001a:
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EAX = 0;
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break;
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/* Floating point - last non-control exception opcode - part
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of FSTENV/FSAVE'd environment */
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case 0x8000001b:
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EAX = msr.fp_last_xcpt;
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break;
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/* Unknown */
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case 0x8000001c:
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EAX = 0x00000004;
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break;
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/* Probe Mode Control */
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case 0x8000001d:
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EAX = msr.probe_ctl;
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break;
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/* Unknown, possibly scratchpad register */
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case 0x8000001e:
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EAX = msr.ecx8000001e;
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break;
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/* Unknown, possibly scratchpad register */
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case 0x8000001f:
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EAX = msr.ecx8000001f;
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break;
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/* Reserved/Unimplemented */
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case 0x80000003:
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case 0x8000000a:
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case 0x8000000f:
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case 0x80000015 ... 0x80000017:
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EAX = (ECX & 0x1f) * 2;
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break;
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default:
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pentium_invalid_rdmsr:
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cpu_log("RDMSR: Invalid MSR: %08X\n", ECX);
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x86gpf(NULL, 0);
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break;
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}
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}
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cpu_log("RDMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
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cpu_log("RDMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
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break;
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break;
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@@ -3368,20 +3509,150 @@ amd_k_invalid_wrmsr:
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case CPU_PENTIUM:
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case CPU_PENTIUM:
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case CPU_PENTIUMMMX:
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case CPU_PENTIUMMMX:
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cpu_log("WRMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
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cpu_log("WRMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
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switch (ECX) {
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/* Filter out the upper 27 bits when ECX value is over 0x80000000, as per:
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Ralf Brown, Pentium Model-Specific Registers and What They Reveal.
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https://www.cs.cmu.edu/~ralf/papers/highmsr.html
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But leave the bit 31 intact to be able to handle both low and high
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MSRs in a single switch block. */
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switch (ECX & (ECX > 0x7fffffff ? 0x8000001f : 0x7fffffff)) {
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/* Machine Check Exception Address */
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/* Machine Check Exception Address */
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case 0x00:
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case 0x00000000:
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case 0x80000000:
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/* Machine Check Exception Type */
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/* Machine Check Exception Type */
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case 0x01:
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case 0x00000001:
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case 0x80000001:
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break;
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/* TR1 - Parity Reversal Test Register */
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case 0x00000002:
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case 0x80000002:
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msr.tr1 = EAX & 0x3fff;
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break;
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/* TR2 - Instruction Cache End Bit */
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case 0x00000004:
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case 0x80000004:
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if (cpu_s->cpu_type == CPU_PENTIUMMMX)
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goto pentium_invalid_wrmsr;
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msr.tr2 = EAX & 0xf;
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break;
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/* TR3 - Cache Test Data */
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case 0x00000005:
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case 0x80000005:
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msr.tr3 = EAX;
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break;
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/* TR4 - Cache Test Tag */
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case 0x00000006:
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case 0x80000006:
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msr.tr4 = EAX & ((cpu_s->cpu_type == CPU_PENTIUMMMX) ? 0xffffff1f : 0xffffff07);
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break;
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/* TR5 - Cache Test Control */
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case 0x00000007:
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case 0x80000007:
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msr.tr5 = EAX & ((cpu_s->cpu_type == CPU_PENTIUMMMX) ? 0x87fff : 0x7fff);
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break;
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/* TR6 - TLB Test Command */
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case 0x00000008:
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case 0x80000008:
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msr.tr6 = EAX & 0xffffff07;
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break;
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/* TR7 - TLB Test Data */
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case 0x00000009:
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case 0x80000009:
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msr.tr7 = EAX & ((cpu_s->cpu_type == CPU_PENTIUMMMX) ? 0xfffffc7f : 0xffffff9c);
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break;
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/* TR9 - Branch Target Buffer Tag */
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case 0x0000000b:
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case 0x8000000b:
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msr.tr9 = EAX & ((cpu_s->cpu_type == CPU_PENTIUMMMX) ? 0xffffffff : 0xffffffc3);
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break;
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/* TR10 - Branch Target Buffer Target */
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case 0x0000000c:
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case 0x8000000c:
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msr.tr10 = EAX;
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break;
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/* TR11 - Branch Target Buffer Control */
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case 0x0000000d:
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case 0x8000000d:
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msr.tr11 = EAX & ((cpu_s->cpu_type >= CPU_PENTIUMMMX) ? 0x3001fcf : 0xfcf);
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break;
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/* TR12 - New Feature Control */
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case 0x0000000e:
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case 0x8000000e:
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if (cpu_s->cpu_type == CPU_PENTIUMMMX)
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temp = EAX & 0x38034f;
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else if ((CPUID & 0xfff) >= 0x52b)
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temp = EAX & 0x20435f;
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else if ((CPUID & 0xfff) >= 0x520)
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temp = EAX & 0x20035f;
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else
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temp = EAX & 0x20030f;
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msr.tr12 = temp;
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break;
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break;
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/* Time Stamp Counter */
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/* Time Stamp Counter */
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case 0x10:
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case 0x00000010:
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case 0x80000010:
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tsc = EAX | ((uint64_t) EDX << 32);
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tsc = EAX | ((uint64_t) EDX << 32);
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break;
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break;
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/* BIOS Update Signature */
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/* Performance Monitor - Control and Event Select */
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case 0x8b:
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case 0x00000011:
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cpu_log("WRMSR: Invalid MSR: 0x8B\n");
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case 0x80000011:
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x86gpf(NULL, 0); /* Needed for Vista to correctly break on Pentium */
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msr.cesr = EAX & 0x3ff03ff;
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break;
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/* Performance Monitor - Event Counter 0 */
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case 0x00000012:
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case 0x80000012:
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msr.pmc[0] = EAX | ((uint64_t) EDX << 32);
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break;
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/* Performance Monitor - Event Counter 1 */
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case 0x00000013:
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case 0x80000013:
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msr.pmc[1] = EAX | ((uint64_t) EDX << 32);
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break;
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/* Unknown */
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case 0x00000014:
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case 0x80000014:
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if ((CPUID & 0xfff) <= 0x520)
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goto pentium_invalid_wrmsr;
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break;
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/* Unknown, possibly paging-related; initial value is 0004h,
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becomes 0008h once paging is enabled */
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|
case 0x80000018:
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|
/* Floating point - last prefetched opcode
|
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|
bits 10-8: low three bits of first byte of FP instruction
|
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|
bits 7-0: second byte of floating-point instruction */
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case 0x80000019:
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/* Floating point - last executed non-control opcode */
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case 0x8000001a:
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break;
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/* Floating point - last non-control exception opcode - part
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of FSTENV/FSAVE'd environment */
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case 0x8000001b:
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EAX = msr.fp_last_xcpt & 0x7ff;
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break;
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/* Unknown */
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case 0x8000001c:
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break;
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/* Probe Mode Control */
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case 0x8000001d:
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EAX = msr.probe_ctl & 0x7;
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break;
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/* Unknown, possibly scratchpad register */
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case 0x8000001e:
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msr.ecx8000001e = EAX;
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break;
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/* Unknown, possibly scratchpad register */
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case 0x8000001f:
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msr.ecx8000001f = EAX;
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break;
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/* Reserved/Unimplemented */
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case 0x80000003:
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case 0x8000000a:
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case 0x8000000f:
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case 0x80000015 ... 0x80000017:
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break;
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default:
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pentium_invalid_wrmsr:
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cpu_log("WRMSR: Invalid MSR: %08X\n", ECX);
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x86gpf(NULL, 0);
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break;
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break;
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}
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}
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break;
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break;
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@@ -249,9 +249,25 @@ typedef struct {
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uint64_t amd_l2aar; /* 0xc0000089 - K6-III and later */
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uint64_t amd_l2aar; /* 0xc0000089 - K6-III and later */
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/* Pentium/Pentium MMX MSRs */
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/* Pentium/Pentium MMX MSRs */
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uint32_t tr1; /* 0x00000002 - also on WinChip C6/2 */
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uint64_t mcar; /* 0x00000000 - also on K5 and (R/W) K6 */
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uint32_t tr12; /* 0x0000000e - also on WinChip C6/2 */
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uint64_t mctr; /* 0x00000001 - also on K5 and (R/W) K6 */
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uint32_t cesr; /* 0x00000011 - also on WinChip C6/2 */
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uint32_t tr1; /* 0x00000002 - also on WinChip C6/2 */
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uint32_t tr2; /* 0x00000004 - reserved on PMMX */
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uint32_t tr3; /* 0x00000005 */
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uint32_t tr4; /* 0x00000006 */
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uint32_t tr5; /* 0x00000007 */
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uint32_t tr6; /* 0x00000008 */
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uint32_t tr7; /* 0x00000009 */
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uint32_t tr9; /* 0x0000000b */
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uint32_t tr10; /* 0x0000000c */
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uint32_t tr11; /* 0x0000000d */
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uint32_t tr12; /* 0x0000000e - also on WinChip C6/2 and K6 */
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uint32_t cesr; /* 0x00000011 - also on WinChip C6/2 and Cx6x86MX */
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uint64_t pmc[2]; /* 0x00000012, 0x00000013 - also on WinChip C6/2 and Cx6x86MX */
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uint32_t fp_last_xcpt; /* 0x8000001b - undocumented */
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||||||
|
uint32_t probe_ctl; /* 0x8000001d - undocumented */
|
||||||
|
uint32_t ecx8000001e; /* 0x8000001e - undocumented */
|
||||||
|
uint32_t ecx8000001f; /* 0x8000001f - undocumented */
|
||||||
|
|
||||||
/* Pentium Pro/II MSRs */
|
/* Pentium Pro/II MSRs */
|
||||||
uint64_t apic_base; /* 0x0000001b */
|
uint64_t apic_base; /* 0x0000001b */
|
||||||
@@ -559,7 +575,6 @@ extern double bus_timing;
|
|||||||
extern double isa_timing;
|
extern double isa_timing;
|
||||||
extern double pci_timing;
|
extern double pci_timing;
|
||||||
extern double agp_timing;
|
extern double agp_timing;
|
||||||
extern uint64_t pmc[2];
|
|
||||||
extern uint16_t temp_seg_data[4];
|
extern uint16_t temp_seg_data[4];
|
||||||
extern uint16_t cs_msr;
|
extern uint16_t cs_msr;
|
||||||
extern uint32_t esp_msr;
|
extern uint32_t esp_msr;
|
||||||
|
|||||||
Reference in New Issue
Block a user