Remove the AP61 hack completely
It's no longer needed
This commit is contained in:
@@ -2391,20 +2391,14 @@ cpu_CPUID(void)
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EBX = ECX = 0;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_CMOV;
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EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_CMOV;
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} else if (EAX == 2) {
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} else if (EAX == 2) {
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/* if (!strcmp(machine_get_internal_name(), "ap61")) {
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EAX = 0x00000001;
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EDX = 0x00000000;
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} else */ {
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EAX = 0x03020101; /* Instruction TLB: 4 KB pages, 4-way set associative, 32 entries
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EAX = 0x03020101; /* Instruction TLB: 4 KB pages, 4-way set associative, 32 entries
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Instruction TLB: 4 MB pages, fully associative, 2 entries
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Instruction TLB: 4 MB pages, fully associative, 2 entries
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Data TLB: 4 KB pages, 4-way set associative, 64 entries */
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Data TLB: 4 KB pages, 4-way set associative, 64 entries */
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EBX = ECX = 0;
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EDX = 0x06040a42; /* 2nd-level cache: 256 KB, 4-way set associative, 32-byte line size
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EDX = 0x06040a42; /* 2nd-level cache: 256 KB, 4-way set associative, 32-byte line size
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1st-level data cache: 8 KB, 2-way set associative, 32-byte line size
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1st-level data cache: 8 KB, 2-way set associative, 32-byte line size
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Data TLB: 4 MB pages, 4-way set associative, 8 entries
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Data TLB: 4 MB pages, 4-way set associative, 8 entries
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1st-level instruction cache: 8 KB, 4-way set associative, 32-byte line size */
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1st-level instruction cache: 8 KB, 4-way set associative, 32-byte line size */
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}
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EBX = ECX = 0;
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} else
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} else
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EAX = EBX = ECX = EDX = 0;
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EAX = EBX = ECX = EDX = 0;
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break;
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break;
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