From 20e771ad3a847ac0b02ec844665a57a2f74fc358 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Wed, 12 Jul 2023 00:32:21 +0200
Subject: [PATCH] Part 2.

---
 src/chipset/intel_420ex.c | 36 +++++++++++++++++++++++++++++++-
 src/chipset/intel_4x0.c   | 11 +++++++---
 src/chipset/sis_85c496.c  | 43 +++++++++++++++++++++++++++++++++++----
 3 files changed, 82 insertions(+), 8 deletions(-)

diff --git a/src/chipset/intel_420ex.c b/src/chipset/intel_420ex.c
index 4f7951047..64fd8a6ab 100644
--- a/src/chipset/intel_420ex.c
+++ b/src/chipset/intel_420ex.c
@@ -41,6 +41,9 @@
 #include <86box/machine.h>
 #include <86box/chipset.h>
 #include <86box/spd.h>
+#ifndef USE_DRB_HACK
+#include <86box/row.h>
+#endif
 
 #define MEM_STATE_SHADOW_R 0x01
 #define MEM_STATE_SHADOW_W 0x02
@@ -158,6 +161,27 @@ i420ex_smram_handler_phase1(i420ex_t *dev)
                  (regs[0x70] & 0x70) == 0x40, !(regs[0x70] & 0x20));
 }
 
+#ifndef USE_DRB_HACK
+static void
+i420ex_drb_recalc(i420ex_t *dev)
+{
+    int i;
+    uint32_t boundary, shift;
+
+    for (i = 4; i >= 0; i--)
+        row_disable(i);
+
+    for (i = 0; i <= 4; i++) {
+	shift = (i & 1) << 2;
+	boundary = ((uint32_t) dev->regs[0x60 + i]) & 0xff;
+	row_set_boundary(i, boundary);
+    }
+
+    flushmmucache();
+}
+#endif
+
+
 static void
 i420ex_write(int func, int addr, uint8_t val, void *priv)
 {
@@ -289,7 +313,12 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
         case 0x62:
         case 0x63:
         case 0x64:
+#ifdef USE_DRB_HACK
             spd_write_drbs(dev->regs, 0x60, 0x64, 1);
+#else
+            dev->regs[addr] = val;
+            i420ex_drb_recalc(dev);
+#endif
             break;
         case 0x66:
         case 0x67:
@@ -452,7 +481,7 @@ i420ex_reset(void *priv)
         i420ex_write(0, 0x59 + i, 0x00, priv);
 
     for (uint8_t i = 0; i <= 4; i++)
-        i420ex_write(0, 0x60 + i, 0x01, priv);
+        dev->regs[0x60 + i] = 0x01;
 
     dev->regs[0x70] &= 0xef; /* Forcibly unlock the SMRAM register. */
     dev->smram_locked = 0;
@@ -530,6 +559,11 @@ i420ex_init(const device_t *info)
 
     device_add(&ide_pci_2ch_device);
 
+#ifndef USE_DRB_HACK
+    row_device.local = 4 | (1 << 8) | (0x01 << 16) | (8 << 24);
+    device_add((const device_t *) &row_device);
+#endif
+
     i420ex_reset_hard(dev);
 
     return dev;
diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c
index ab34ddd02..c8bc80271 100644
--- a/src/chipset/intel_4x0.c
+++ b/src/chipset/intel_4x0.c
@@ -1536,8 +1536,13 @@ i4x0_reset(void *priv)
     for (uint8_t i = 0; i < 6; i++)
         i4x0_write(0, 0x5a + i, 0x00, priv);
 
-    for (uint8_t i = 0; i <= dev->max_drb; i++)
-        i4x0_write(0, 0x60 + i, dev->drb_default, priv);
+    for (i = 0; i <= dev->max_drb; i++)
+        dev->regs[0x60 + i] = dev->drb_default;
+
+    if (dev->type >= INTEL_430NX) {
+        for (i = 0; i < 4; i++)
+            dev->regs[0x68 + i] = 0x00;
+    }
 
     if (dev->type >= INTEL_430FX) {
         dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */
@@ -1621,7 +1626,7 @@ i4x0_init(const device_t *info)
             regs[0x59] = 0x0f;
             regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = 0x02;
             dev->max_drb                                      = 3;
-            dev->drb_unit                                     = 4;
+            dev->drb_unit                                     = 1;
             dev->drb_default                                  = 0x02;
             break;
         case INTEL_430LX:
diff --git a/src/chipset/sis_85c496.c b/src/chipset/sis_85c496.c
index 6c0c1d0d3..6d1695108 100644
--- a/src/chipset/sis_85c496.c
+++ b/src/chipset/sis_85c496.c
@@ -38,10 +38,17 @@
 #include <86box/machine.h>
 #include <86box/chipset.h>
 #include <86box/spd.h>
+#ifndef USE_DRB_HACK
+#include <86box/row.h>
+#endi
 
 typedef struct sis_85c496_t {
     uint8_t    cur_reg;
     uint8_t    rmsmiblk_count;
+#ifndef USE_DRB_HACK
+    uint8_t    drb_default;
+    uint8_t    drb_bits;
+#endif
     uint8_t    regs[127];
     uint8_t    pci_conf[256];
     smram_t   *smram;
@@ -184,6 +191,27 @@ sis_85c496_ide_handler(sis_85c496_t *dev)
     }
 }
 
+#ifndef USE_DRB_HACK
+static void
+sis_85c496_drb_recalc(sis_85c496_t *dev)
+{
+    int i;
+    uint32_t boundary, shift;
+
+    for (i = 7; i >= 0; i--)
+        row_disable(i);
+
+    for (i = 0; i <= 7; i++) {
+        shift = (i & 1) << 2;
+        boundary = ((uint32_t) dev->pci_conf[0x48 + i]);
+        row_set_boundary(i, boundary);
+    }
+
+    flushmmucache();
+}
+#endif
+
+
 /* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */
 static void
 sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
@@ -259,10 +287,12 @@ sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
         case 0x4d:
         case 0x4e:
         case 0x4f:
-#if 0
-            dev->pci_conf[addr] = val;
-#endif
+#ifdef USE_DRB_HACK
             spd_write_drbs(dev->pci_conf, 0x48, 0x4f, 1);
+#else
+            dev->pci_conf[addr] = val;
+            sis_85c496_drb_recalc(dev);
+#endif
             break;
         case 0x50:
         case 0x51: /* Exclusive Area 0 Setup */
@@ -552,7 +582,7 @@ sis_85c496_reset(void *priv)
     // sis_85c49x_pci_write(0, 0x5a, 0x06, dev);
 
     for (uint8_t i = 0; i < 8; i++)
-        sis_85c49x_pci_write(0, 0x48 + i, 0x00, dev);
+        dev->pci_conf[0x48 + i] = 0x02;
 
     sis_85c49x_pci_write(0, 0x80, 0x00, dev);
     sis_85c49x_pci_write(0, 0x81, 0x00, dev);
@@ -643,6 +673,11 @@ static void
 
     timer_add(&dev->rmsmiblk_timer, sis_85c496_rmsmiblk_count, dev, 0);
 
+#ifndef USE_DRB_HACK
+    row_device.local = 7 | (1 << 8) | (0x02 << 16) | (7 << 24);
+    device_add((const device_t *) &row_device);
+#endif
+
     sis_85c496_reset(dev);
 
     return dev;