From 232b44323cce2f762d7fb7975a83bece56f2a4da Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 21 Jul 2024 00:06:33 -0400 Subject: [PATCH] Named initializers for soclet 1 486's --- src/cpu/cpu_table.c | 810 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 765 insertions(+), 45 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index c24167500..6ae963c79 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -2071,10 +2071,74 @@ const cpu_family_t cpu_families[] = { .name = "i486SX", .internal_name = "i486sx", .cpus = (const CPU[]) { - {"16", CPU_i486SX, fpus_486sx, 16000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, - {"20", CPU_i486SX, fpus_486sx, 20000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"25", CPU_i486SX, fpus_486sx, 25000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486SX, fpus_486sx, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + { + .name = "16", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 16000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 3, + .mem_write_cycles = 3, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 2 + }, + { + .name = "20", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 20000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "25", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_i486SX, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, { .name = "", 0 } } }, @@ -2084,8 +2148,40 @@ const cpu_family_t cpu_families[] = { .name = "i486SX-S", .internal_name = "i486sx_slenh", .cpus = (const CPU[]) { - {"25", CPU_i486SX_SLENH, fpus_486sx, 25000000, 1, 5000, 0x423, 0x423, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486SX_SLENH, fpus_486sx, 33333333, 1, 5000, 0x42a, 0x42a, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + { + .name = "25", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x423, + .cpuid_model = 0x423, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x42a, + .cpuid_model = 0x42a, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, { .name = "", 0 } } }, @@ -2095,8 +2191,40 @@ const cpu_family_t cpu_families[] = { .name = "i486SX2", .internal_name = "i486sx2", .cpus = (const CPU[]) { - {"50", CPU_i486SX_SLENH, fpus_486sx, 50000000, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66 (Q0569)", CPU_i486SX_SLENH, fpus_486sx, 66666666, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, + { + .name = "50", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0x45b, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66 (Q0569)", + .cpu_type = CPU_i486SX_SLENH, + .fpus = fpus_486sx, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0x45b, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -2106,9 +2234,57 @@ const cpu_family_t cpu_families[] = { .name = "i486DX", .internal_name = "i486dx", .cpus = (const CPU[]) { - {"25", CPU_i486DX, fpus_internal, 25000000, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486DX, fpus_internal, 33333333, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"50", CPU_i486DX, fpus_internal, 50000000, 1, 5000, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + { + .name = "25", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 25000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x404, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x404, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "50", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x411, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 6 + }, { .name = "", 0 } } }, @@ -2118,8 +2294,40 @@ const cpu_family_t cpu_families[] = { .name = "i486DX-S", .internal_name = "i486dx_slenh", .cpus = (const CPU[]) { - {"33", CPU_i486DX_SLENH, fpus_internal, 33333333, 1, 5000, 0x414, 0x414, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 1, 5000, 0x414, 0x414, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + { + .name = "33", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x414, + .cpuid_model = 0x414, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "50", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x414, + .cpuid_model = 0x414, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 4, + .cache_write_cycles = 4, + .atclk_div = 6 + }, { .name = "", 0 } } }, @@ -2129,9 +2337,57 @@ const cpu_family_t cpu_families[] = { .name = "i486DX2", .internal_name = "i486dx2", .cpus = (const CPU[]) { - {"40", CPU_i486DX, fpus_internal, 40000000, 2, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"50", CPU_i486DX, fpus_internal, 50000000, 2, 5000, 0x433, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX, fpus_internal, 66666666, 2, 5000, 0x433, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + { + .name = "40", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 5 + }, + { + .name = "50", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x433, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_i486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x433, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -2141,9 +2397,57 @@ const cpu_family_t cpu_families[] = { .name = "i486DX2-S", .internal_name = "i486dx2_slenh", .cpus = (const CPU[]) { - {"40", CPU_i486DX_SLENH, fpus_internal, 40000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX_SLENH, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + { + .name = "40", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 5 + }, + { + .name = "50", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -2153,8 +2457,40 @@ const cpu_family_t cpu_families[] = { .name = "i486DX2 WB", .internal_name = "i486dx2_pc330", .cpus = (const CPU[]) { - {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 2, 5000, 0x436, 0x436, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX_SLENH, fpus_internal, 66666666, 2, 5000, 0x436, 0x436, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + { + .name = "50", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x436, + .cpuid_model = 0x436, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x436, + .cpuid_model = 0x436, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -2164,8 +2500,40 @@ const cpu_family_t cpu_families[] = { .name = "iDX4", .internal_name = "idx4", .cpus = (const CPU[]) { - {"75", CPU_i486DX_SLENH, fpus_internal, 75000000, 3.0, 5000, 0x480, 0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"100", CPU_i486DX_SLENH, fpus_internal, 100000000, 3.0, 5000, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, + { + .name = "75", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0x480, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 + }, + { + .name = "100", + .cpu_type = CPU_i486DX_SLENH, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x483, + .cpuid_model = 0x483, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 18, + .mem_write_cycles = 18, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, { .name = "", 0 } } }, @@ -2186,8 +2554,40 @@ const cpu_family_t cpu_families[] = { .name = "Am486SX", .internal_name = "am486sx", .cpus = (const CPU[]) { - {"33", CPU_Am486SX, fpus_486sx, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486SX, fpus_486sx, 40000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "33", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -2197,8 +2597,40 @@ const cpu_family_t cpu_families[] = { .name = "Am486SX2", .internal_name = "am486sx2", .cpus = (const CPU[]) { - {"50", CPU_Am486SX, fpus_486sx, 50000000, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Am486SX, fpus_486sx, 66666666, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + { + .name = "50", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_Am486SX, + .fpus = fpus_486sx, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x45b, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, { .name = "", 0 } } }, @@ -2208,8 +2640,40 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX", .internal_name = "am486dx", .cpus = (const CPU[]) { - {"33", CPU_Am486DX, fpus_internal, 33333333, 1, 5000, 0x412, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486DX, fpus_internal, 40000000, 1, 5000, 0x412, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "33", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x412, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x412, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -2219,9 +2683,57 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX2", .internal_name = "am486dx2", .cpus = (const CPU[]) { - {"50", CPU_Am486DX, fpus_internal, 50000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Am486DX, fpus_internal, 66666666, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Am486DX, fpus_internal, 80000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { + .name = "50", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { + .name = "80", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, { .name = "", 0 } } }, @@ -2231,8 +2743,40 @@ const cpu_family_t cpu_families[] = { .name = "Am486DXL", .internal_name = "am486dxl", .cpus = (const CPU[]) { - {"33", CPU_Am486DXL, fpus_internal, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486DXL, fpus_internal, 40000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "33", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1, + .voltage = 5000, + .edx_reset = 0x422, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -2242,9 +2786,57 @@ const cpu_family_t cpu_families[] = { .name = "Am486DXL2", .internal_name = "am486dxl2", .cpus = (const CPU[]) { - {"50", CPU_Am486DXL, fpus_internal, 50000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Am486DXL, fpus_internal, 66666666, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Am486DXL, fpus_internal, 80000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { + .name = "50", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { + .name = "80", + .cpu_type = CPU_Am486DXL, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, { .name = "", 0 } } }, @@ -2302,9 +2894,57 @@ const cpu_family_t cpu_families[] = { .name = "Cx486S", .internal_name = "cx486s", .cpus = (const CPU[]) { - {"25", CPU_Cx486S, fpus_486sx, 25000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, - {"33", CPU_Cx486S, fpus_486sx, 33333333, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Cx486S, fpus_486sx, 40000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "25", + .cpu_type = CPU_Cx486S, + .fpus = fpus_486sx, + .rspeed = 25000000, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0x0010, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 4, + .mem_write_cycles = 4, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 3 + }, + { + .name = "33", + .cpu_type = CPU_Cx486S, + .fpus = fpus_486sx, + .rspeed = 33333333, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0x0010, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_Cx486S, + .fpus = fpus_486sx, + .rspeed = 40000000, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x420, + .cpuid_model = 0, + .cyrix_id = 0x0010, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -2314,8 +2954,40 @@ const cpu_family_t cpu_families[] = { .name = "Cx486DX", .internal_name = "cx486dx", .cpus = (const CPU[]) { - {"33", CPU_Cx486DX, fpus_internal, 33333333, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Cx486DX, fpus_internal, 40000000, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + { + .name = "33", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 33333333, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x051a, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 6, + .mem_write_cycles = 6, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 4 + }, + { + .name = "40", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 40000000, + .multi = 1.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x051a, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 7, + .mem_write_cycles = 7, + .cache_read_cycles = 3, + .cache_write_cycles = 3, + .atclk_div = 5 + }, { .name = "", 0 } } }, @@ -2325,9 +2997,57 @@ const cpu_family_t cpu_families[] = { .name = "Cx486DX2", .internal_name = "cx486dx2", .cpus = (const CPU[]) { - {"50", CPU_Cx486DX, fpus_internal, 50000000, 2.0, 5000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Cx486DX, fpus_internal, 66666666, 2.0, 5000, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Cx486DX, fpus_internal, 80000000, 2.0, 5000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { + .name = "50", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 50000000, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x081b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 8, + .mem_write_cycles = 8, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 6 + }, + { + .name = "66", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x0b1b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { + .name = "80", + .cpu_type = CPU_Cx486DX, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x430, + .cpuid_model = 0, + .cyrix_id = 0x311b, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, { .name = "", 0 } } },