From 88e396f852acaad74c876e6f8f7a5371982b9767 Mon Sep 17 00:00:00 2001 From: RichardG867 Date: Sun, 11 Oct 2020 18:52:00 -0300 Subject: [PATCH 1/6] Clean up SMBus PIIX4 code --- src/device/smbus_piix4.c | 237 ++++++++++++++++++++------------------- 1 file changed, 119 insertions(+), 118 deletions(-) diff --git a/src/device/smbus_piix4.c b/src/device/smbus_piix4.c index affadf39e..131c5c126 100644 --- a/src/device/smbus_piix4.c +++ b/src/device/smbus_piix4.c @@ -39,9 +39,9 @@ smbus_piix4_log(const char *fmt, ...) va_list ap; if (smbus_piix4_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else @@ -56,30 +56,30 @@ smbus_piix4_read(uint16_t addr, void *priv) uint8_t ret = 0x00; switch (addr - dev->io_base) { - case 0x00: - ret = dev->stat; - break; - case 0x02: - dev->index = 0; /* reading from this resets the block data index */ - ret = dev->ctl; - break; - case 0x03: - ret = dev->cmd; - break; - case 0x04: - ret = dev->addr; - break; - case 0x05: - ret = dev->data0; - break; - case 0x06: - ret = dev->data1; - break; - case 0x07: - ret = dev->data[dev->index++]; - if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE) - dev->index = 0; - break; + case 0x00: + ret = dev->stat; + break; + case 0x02: + dev->index = 0; /* reading from this resets the block data index */ + ret = dev->ctl; + break; + case 0x03: + ret = dev->cmd; + break; + case 0x04: + ret = dev->addr; + break; + case 0x05: + ret = dev->data0; + break; + case 0x06: + ret = dev->data1; + break; + case 0x07: + ret = dev->data[dev->index++]; + if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE) + dev->index = 0; + break; } smbus_piix4_log("SMBus PIIX4: read(%02x) = %02x\n", addr, ret); @@ -100,99 +100,100 @@ smbus_piix4_write(uint16_t addr, uint8_t val, void *priv) prev_stat = dev->next_stat; dev->next_stat = 0; switch (addr - dev->io_base) { - case 0x00: - /* some status bits are reset by writing 1 to them */ - for (smbus_addr = 0x02; smbus_addr <= 0x10; smbus_addr <<= 1) { - if (val & smbus_addr) - dev->stat &= ~smbus_addr; - } - break; - case 0x02: - dev->ctl = val & ~(0x40); /* START always reads 0 */ - if (val & 0x02) { /* cancel an in-progress command if KILL is set */ - /* cancel only if a command is in progress */ - if (prev_stat) { - dev->stat = 0x10; /* raise FAILED */ - timer_disable(&dev->response_timer); - } - } - if (val & 0x40) { /* dispatch command if START is set */ - smbus_addr = (dev->addr >> 1); - if (!smbus_has_device(smbus_addr)) { - /* raise DEV_ERR if no device is at this address */ - dev->next_stat = 0x4; - break; - } - smbus_read = (dev->addr & 0x01); + case 0x00: + /* some status bits are reset by writing 1 to them */ + for (smbus_addr = 0x02; smbus_addr <= 0x10; smbus_addr <<= 1) { + if (val & smbus_addr) + dev->stat &= ~smbus_addr; + } + break; + case 0x02: + dev->ctl = val & ~(0x40); /* START always reads 0 */ + if (val & 0x02) { /* cancel an in-progress command if KILL is set */ + /* cancel only if a command is in progress */ + if (prev_stat) { + dev->stat = 0x10; /* raise FAILED */ + timer_disable(&dev->response_timer); + } + } + if (val & 0x40) { /* dispatch command if START is set */ + smbus_addr = (dev->addr >> 1); + if (!smbus_has_device(smbus_addr)) { + /* raise DEV_ERR if no device is at this address */ + dev->next_stat = 0x4; + break; + } + smbus_read = (dev->addr & 0x01); - /* decode the 3-bit command protocol */ - switch ((val >> 2) & 0x7) { - case 0x0: /* quick R/W */ - dev->next_stat = 0x2; - break; - case 0x1: /* byte R/W */ - if (smbus_read) - dev->data0 = smbus_read_byte(smbus_addr); - else - smbus_write_byte(smbus_addr, dev->data0); - dev->next_stat = 0x2; - break; - case 0x2: /* byte data R/W */ - if (smbus_read) - dev->data0 = smbus_read_byte_cmd(smbus_addr, dev->cmd); - else - smbus_write_byte_cmd(smbus_addr, dev->cmd, dev->data0); - dev->next_stat = 0x2; - break; - case 0x3: /* word data R/W */ - if (smbus_read) { - temp = smbus_read_word_cmd(smbus_addr, dev->cmd); - dev->data0 = (temp & 0xFF); - dev->data1 = (temp >> 8); - } else { - temp = ((dev->data1 << 8) | dev->data0); - smbus_write_word_cmd(smbus_addr, dev->cmd, temp); - } - dev->next_stat = 0x2; - break; - case 0x5: /* block R/W */ - if (smbus_read) - dev->data0 = smbus_read_block_cmd(smbus_addr, dev->cmd, dev->data, SMBUS_PIIX4_BLOCK_DATA_SIZE); - else - smbus_write_block_cmd(smbus_addr, dev->cmd, dev->data, dev->data0); - dev->next_stat = 0x2; - break; - default: - /* other command protocols have undefined behavior, but raise DEV_ERR to be safe */ - dev->next_stat = 0x4; - break; - } - } - break; - case 0x03: - dev->cmd = val; - break; - case 0x04: - dev->addr = val; - break; - case 0x05: - dev->data0 = val; - break; - case 0x06: - dev->data1 = val; - break; - case 0x07: - dev->data[dev->index++] = val; - if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE) - dev->index = 0; - break; + /* decode the 3-bit command protocol */ + dev->next_stat = 0x2; /* raise INTER (command completed) by default */ + switch ((val >> 2) & 0x7) { + case 0x0: /* quick R/W */ + break; + + case 0x1: /* byte R/W */ + if (smbus_read) + dev->data0 = smbus_read_byte(smbus_addr); + else + smbus_write_byte(smbus_addr, dev->data0); + break; + + case 0x2: /* byte data R/W */ + if (smbus_read) + dev->data0 = smbus_read_byte_cmd(smbus_addr, dev->cmd); + else + smbus_write_byte_cmd(smbus_addr, dev->cmd, dev->data0); + break; + + case 0x3: /* word data R/W */ + if (smbus_read) { + temp = smbus_read_word_cmd(smbus_addr, dev->cmd); + dev->data0 = (temp & 0xFF); + dev->data1 = (temp >> 8); + } else { + temp = ((dev->data1 << 8) | dev->data0); + smbus_write_word_cmd(smbus_addr, dev->cmd, temp); + } + break; + + case 0x5: /* block R/W */ + if (smbus_read) + dev->data0 = smbus_read_block_cmd(smbus_addr, dev->cmd, dev->data, SMBUS_PIIX4_BLOCK_DATA_SIZE); + else + smbus_write_block_cmd(smbus_addr, dev->cmd, dev->data, dev->data0); + break; + + default: + /* other command protocols have undefined behavior, but raise DEV_ERR to be safe */ + dev->next_stat = 0x4; + break; + } + } + break; + case 0x03: + dev->cmd = val; + break; + case 0x04: + dev->addr = val; + break; + case 0x05: + dev->data0 = val; + break; + case 0x06: + dev->data1 = val; + break; + case 0x07: + dev->data[dev->index++] = val; + if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE) + dev->index = 0; + break; } /* if a status register update was given, dispatch it after 10ms to ensure nothing breaks */ if (dev->next_stat) { - dev->stat = 0x1; /* raise HOST_BUSY while waiting */ - timer_disable(&dev->response_timer); - timer_set_delay_u64(&dev->response_timer, 10 * TIMER_USEC); + dev->stat = 0x1; /* raise HOST_BUSY while waiting */ + timer_disable(&dev->response_timer); + timer_set_delay_u64(&dev->response_timer, 10 * TIMER_USEC); } } @@ -210,13 +211,13 @@ smbus_piix4_response(void *priv) void smbus_piix4_remap(smbus_piix4_t *dev, uint16_t new_io_base, uint8_t enable) { - if (dev->io_base != 0x0000) + if (dev->io_base) io_removehandler(dev->io_base, 0x10, smbus_piix4_read, NULL, NULL, smbus_piix4_write, NULL, NULL, dev); dev->io_base = new_io_base; - smbus_piix4_log("SMBus PIIX4: remap to %04Xh (enable %d)\n", dev->io_base, !!enable); + smbus_piix4_log("SMBus PIIX4: remap to %04Xh (%sabled)\n", dev->io_base, enable ? "en" : "dis"); - if ((enable) && (dev->io_base != 0x0000)) + if (enable && dev->io_base) io_sethandler(dev->io_base, 0x10, smbus_piix4_read, NULL, NULL, smbus_piix4_write, NULL, NULL, dev); } From 8629536be8a115242cec58b9c49ebc8fc958133a Mon Sep 17 00:00:00 2001 From: RichardG867 Date: Sun, 11 Oct 2020 21:04:29 -0300 Subject: [PATCH 2/6] Fix PostScript printer --- src/printer/prt_ps.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/printer/prt_ps.c b/src/printer/prt_ps.c index 03e7ea9b9..c1b39cf96 100644 --- a/src/printer/prt_ps.c +++ b/src/printer/prt_ps.c @@ -184,7 +184,7 @@ convert_to_pdf(ps_t *dev) static void -write_buffer(ps_t *dev, bool newline) +write_buffer(ps_t *dev, bool finish) { wchar_t path[1024]; FILE *fp; @@ -205,17 +205,19 @@ write_buffer(ps_t *dev, bool newline) fseek(fp, 0, SEEK_END); - fprintf(fp, "%.*s%s", POSTSCRIPT_BUFFER_LENGTH, dev->buffer, newline ? "\n" : ""); + fprintf(fp, "%.*s", POSTSCRIPT_BUFFER_LENGTH, dev->buffer); fclose(fp); dev->buffer[0] = 0; dev->buffer_pos = 0; - if (ghostscript_handle != NULL) - convert_to_pdf(dev); + if (finish) { + if (ghostscript_handle != NULL) + convert_to_pdf(dev); - dev->filename[0] = 0; + dev->filename[0] = 0; + } } @@ -224,7 +226,7 @@ timeout_timer(void *priv) { ps_t *dev = (ps_t *) priv; - write_buffer(dev, false); + write_buffer(dev, true); timer_disable(&dev->timeout_timer); } @@ -263,7 +265,7 @@ process_data(ps_t *dev) /* Ctrl+D (0x04) marks the end of the document */ case '\4': - write_buffer(dev, false); + write_buffer(dev, true); return; /* Don't bother with the others */ @@ -376,7 +378,7 @@ ps_close(void *p) return; if (dev->buffer[0] != 0) - write_buffer(dev, false); + write_buffer(dev, true); if (ghostscript_handle != NULL) { dynld_close(ghostscript_handle); From f6183ab1b89bb2fec44badb16b400d0a02a8aae2 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 13 Oct 2020 18:14:06 +0200 Subject: [PATCH 3/6] Committed a S3 ViRGE bug fix by tonioni - fixes vertical clipping. --- src/video/vid_s3_virge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/video/vid_s3_virge.c b/src/video/vid_s3_virge.c index b01d2e710..ab9ebc8c5 100644 --- a/src/video/vid_s3_virge.c +++ b/src/video/vid_s3_virge.c @@ -2784,7 +2784,7 @@ static void tri(virge_t *virge, s3d_t *s3d_tri, s3d_state_t *state, int yc, int3 state->x1 += (dx1 * diff_y); state->x2 += (dx2 * diff_y); state->y -= diff_y; - dest_offset -= s3d_tri->dest_str; + dest_offset -= s3d_tri->dest_str * diff_y; z_offset -= s3d_tri->z_str; y_count -= diff_y; } From 55920d8afd454838abe166a5d12eac818e45fa8c Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 13 Oct 2020 19:05:38 +0200 Subject: [PATCH 4/6] VIA SMI handling now also applies to the 596B. --- src/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/acpi.c b/src/acpi.c index 43529701c..2e7900889 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -85,7 +85,7 @@ acpi_raise_smi(void *priv) { acpi_t *dev = (acpi_t *) priv; - if (dev->vendor == VEN_VIA) { + if ((dev->vendor == VEN_VIA) || (dev->vendor == VEN_VIA_596B)) { if ((dev->regs.glbctl & 0x01) && (!dev->regs.smi_lock || !dev->regs.smi_active)) { smi_line = 1; dev->regs.smi_active = 1; From f465066ed2d4c9846fe81b597d89c66a3fce9d07 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 13 Oct 2020 21:49:55 +0200 Subject: [PATCH 5/6] The SMSC southbridge now initializes IDE regiters 0x45 and 0x46 to the correct values. --- src/chipset/intel_piix.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/chipset/intel_piix.c b/src/chipset/intel_piix.c index 2557c8a80..348cef814 100644 --- a/src/chipset/intel_piix.c +++ b/src/chipset/intel_piix.c @@ -1055,6 +1055,8 @@ piix_reset_hard(piix_t *dev) if (dev->type == 5) { fregs[0x3c] = 0x0e; fregs[0x3d] = 0x01; + fregs[0x45] = 0x55; + fregs[0x46] = 0x01; } if ((dev->type == 1) && (dev->rev == 2)) dev->max_func = 0; /* It starts with IDE disabled, then enables it. */ From a81f9514b6fd7e99608270990ca99ec97e1bdb6a Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 13 Oct 2020 22:44:22 +0200 Subject: [PATCH 6/6] Assorted fixes related to the SMSC southbridge - now all four IDE devices get UDMA-66. --- src/acpi.c | 3 ++- src/chipset/intel_piix.c | 6 ++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/acpi.c b/src/acpi.c index 2e7900889..dfd6bf9e8 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -1134,7 +1134,8 @@ acpi_reset(void *priv) int i; memset(&dev->regs, 0x00, sizeof(acpi_regs_t)); - dev->regs.gpireg[0] = dev->regs.gpireg[1] = dev->regs.gpireg[2] = 0xff; + dev->regs.gpireg[0] = 0xff; dev->regs.gpireg[1] = 0xff; + dev->regs.gpireg[2] = 0xf3; /* SMSC: Bit 2: 80-conductor cable on primary IDE (0 = yes, 1 = no), Bit 3: on secondary IDE. */ for (i = 0; i < 4; i++) dev->regs.gporeg[i] = dev->gporeg_default[i]; if (dev->vendor == VEN_VIA_596B) diff --git a/src/chipset/intel_piix.c b/src/chipset/intel_piix.c index 348cef814..85448bdde 100644 --- a/src/chipset/intel_piix.c +++ b/src/chipset/intel_piix.c @@ -1053,10 +1053,8 @@ piix_reset_hard(piix_t *dev) } fregs[0x20] = 0x01; if (dev->type == 5) { - fregs[0x3c] = 0x0e; - fregs[0x3d] = 0x01; - fregs[0x45] = 0x55; - fregs[0x46] = 0x01; + fregs[0x3c] = 0x0e; fregs[0x3d] = 0x01; + fregs[0x45] = 0x55; fregs[0x46] = 0x01; } if ((dev->type == 1) && (dev->rev == 2)) dev->max_func = 0; /* It starts with IDE disabled, then enables it. */