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Added more 82335 parts

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Registers are treated with an array instead of separate values.
Minor Shadowing changes and also implemented the chipset lock mechanism fixing the ADI soft reset issue properly.
This commit is contained in:
tiseno100
2020-09-10 23:56:51 +03:00
committed by GitHub
parent 54c569e5be
commit 2e7781505a
1 changed files with 26 additions and 89 deletions
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115
src/chipset/intel_82335.c
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@@ -12,25 +12,6 @@
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/chipset.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
@@ -50,20 +31,21 @@
#include <86box/port_92.h>
#include <86box/chipset.h>
#define enabled_shadow (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)
#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
#define rw_shadow (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)
#define ro_shadow (MEM_READ_INTERNAL | MEM_WRITE_DISABLED)
#define extended_granuality_enabled (dev->reg_2c & 0x01)
#define determine_video_ram_write_access ((dev->reg_22 & (0x08 << 8)) ? rw_shadow : ro_shadow)
#define extended_granuality_enabled (dev->regs[0x2c] & 0x01)
#define determine_video_ram_write_access ((dev->regs[0x22] & (0x08 << 8)) ? rw_shadow : ro_shadow)
#define ENABLE_INTEL_82335_LOG 1
typedef struct
{
uint16_t
reg_22, reg_24, reg_26, reg_28, reg_2a, reg_2c, reg_2e;
uint16_t regs[256],
cfg_locked;
} intel_82335_t;
@@ -88,58 +70,40 @@ static void
intel_82335_write(uint16_t addr, uint16_t val, void *priv)
{
intel_82335_t *dev = (intel_82335_t *) priv;
uint32_t base, i;
dev->regs[addr] = val;
dev->cfg_locked = (dev->regs[0x22] & (0x80 << 8));
if(!dev->cfg_locked)
{
intel_82335_log("Register %02x: Write %04x\n", addr, val);
switch (addr) {
case 0x22:
dev->reg_22 = val;
if (!extended_granuality_enabled)
{
mem_set_mem_state_both(0xa0000, 0x20000, (dev->reg_22 & (0x04 << 8)) ? determine_video_ram_write_access : disabled_shadow);
mem_set_mem_state_both(0xc0000, 0x20000, (dev->reg_22 & (0x02 << 8)) ? enabled_shadow : disabled_shadow);
mem_set_mem_state_both(0xe0000, 0x20000, (dev->reg_22 & 0x01) ? ro_shadow : disabled_shadow);
mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? determine_video_ram_write_access : disabled_shadow);
mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? rw_shadow : disabled_shadow);
mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? rw_shadow : disabled_shadow);
}
break;
case 0x24:
dev->reg_24 = val;
break;
case 0x26:
dev->reg_26 = val;
break;
case 0x28:
dev->reg_28 = val;
break;
case 0x2a:
dev->reg_2a = val;
break;
case 0x2c:
dev->reg_2c = val;
break;
case 0x2e:
dev->reg_2e = val;
if(extended_granuality_enabled)
{
for(i=0; i<8; i++)
{
base = 0xc0000 + (i << 15);
mem_set_mem_state_both(base, 0x8000, (dev->reg_2e & (1 << (i+8))) ? ((dev->reg_2e & (1 << i)) ? ro_shadow : rw_shadow) : disabled_shadow);
mem_set_mem_state_both(base, 0x8000, (dev->regs[0x2e] & (1 << (i+8))) ? ((dev->regs[0x2e] & (1 << i)) ? ro_shadow : rw_shadow) : disabled_shadow);
}
break;
}
}
}
}
@@ -150,32 +114,8 @@ intel_82335_read(uint16_t addr, void *priv)
intel_82335_log("Register %02x: Reading\n", addr);
switch (addr) {
case 0x22:
return dev->reg_22;
break;
case 0x24:
return dev->reg_24;
break;
case 0x26:
return dev->reg_26;
break;
case 0x28:
return dev->reg_28;
break;
case 0x2a:
return dev->reg_2a;
break;
case 0x2c:
return dev->reg_2c;
break;
case 0x2e:
return dev->reg_2e;
break;
default:
return 0xff;
break;
}
return dev->regs[addr];
}
static void
@@ -194,14 +134,11 @@ intel_82335_init(const device_t *info)
memset(dev, 0, sizeof(intel_82335_t));
device_add(&port_92_device);
memset(dev->regs, 0, sizeof(dev->regs));
dev->reg_22 = 0x00;
dev->reg_24 = 0x00;
dev->reg_26 = 0x00;
dev->reg_28 = 0xf9;
dev->reg_2a = 0x00;
dev->reg_2c = 0x00;
dev->reg_2e = 0x00;
dev->regs[0x28] = 0xf9;
dev->cfg_locked = 1;
/* Memory Configuration */
io_sethandler(0x0022, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);