From 306d0fe5bbeb8ba32db51307f708fec55ba59ca8 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Sat, 23 Jul 2016 15:35:51 +0200
Subject: [PATCH] Vision964/BT485: Set RS3 to 0 when RS2 is set per CRTC reg.
 43h bit 1.

---
 src/vid_s3.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/vid_s3.c b/src/vid_s3.c
index 3ebed6b8f..e17f5ae51 100644
--- a/src/vid_s3.c
+++ b/src/vid_s3.c
@@ -863,6 +863,7 @@ void s3_out(uint16_t addr, uint8_t val, void *p)
 					else
 					{
 						bt485_set_rs2(svga->crtc[0x43] & 2, &s3->bt485_ramdac);
+						bt485_set_rs3(0, &s3->bt485_ramdac);
 					}
 					pclog("RS2 is now %i, RS3 is now %i\n", s3->bt485_ramdac.rs2, s3->bt485_ramdac.rs3);
 				}