From cfa6f64716dd54f87aa25874021c3bf5cc8d3002 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 27 Dec 2022 13:49:10 -0500 Subject: [PATCH 1/3] Initial P2 Covington support --- src/cpu/cpu_table.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 6fc922b1e..6f4d06399 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -1066,6 +1066,16 @@ const cpu_family_t cpu_families[] = { {"450", CPU_PENTIUM2D, fpus_internal, 450000000, 4.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, {"", 0} } + }, { + .package = CPU_PKG_SLOT1, + .manufacturer = "Intel", + .name = "Celeron (Covington)", + .internal_name = "celeron_covington", + .cpus = (const CPU[]) { + {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + {"", 0} + } }, { .package = CPU_PKG_SLOT2, .manufacturer = "Intel", From bde453160606469de5a9313b544b8edb7c1e79d8 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 27 Dec 2022 14:03:16 -0500 Subject: [PATCH 2/3] Fix timings, as the Covington doesn't have L2 cache --- src/cpu/cpu_table.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 6f4d06399..01576decb 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -1072,8 +1072,8 @@ const cpu_family_t cpu_families[] = { .name = "Celeron (Covington)", .internal_name = "celeron_covington", .cpus = (const CPU[]) { - {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,24,24, 32}, + {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,25,25, 36}, {"", 0} } }, { From 239294b6e39d2750b7ea4a6984de8469bfc9be12 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Tue, 27 Dec 2022 15:27:06 -0500 Subject: [PATCH 3/3] Add out of spec underclocked models Matches how we handle the Deschutes --- src/cpu/cpu_table.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 01576decb..f9e86541c 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -1072,6 +1072,12 @@ const cpu_family_t cpu_families[] = { .name = "Celeron (Covington)", .internal_name = "celeron_covington", .cpus = (const CPU[]) { + {"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 6, 6, 8}, /* out of spec */ + {"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 9, 9, 12}, /* out of spec */ + {"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,12,12, 16}, /* out of spec */ + {"166", CPU_PENTIUM2D, fpus_internal, 166666666, 2.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,15,15, 20}, /* out of spec */ + {"200", CPU_PENTIUM2D, fpus_internal, 200000000, 3.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,18,18, 24}, /* out of spec */ + {"233", CPU_PENTIUM2D, fpus_internal, 233333333, 3.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,21,21, 28}, /* out of spec */ {"266", CPU_PENTIUM2D, fpus_internal, 266666666, 4.0, 2050, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,24,24, 32}, {"300", CPU_PENTIUM2D, fpus_internal, 300000000, 4.5, 2050, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,25,25, 36}, {"", 0}