diff --git a/src/network/net_3c503.c b/src/network/net_3c503.c index 2e5c97519..5123da265 100644 --- a/src/network/net_3c503.c +++ b/src/network/net_3c503.c @@ -63,131 +63,124 @@ #include <86box/bswap.h> typedef struct { - dp8390_t *dp8390; - mem_mapping_t ram_mapping; - uint32_t base_address; - int base_irq; - uint32_t bios_addr; - uint8_t maclocal[6]; /* configured MAC (local) address */ + dp8390_t *dp8390; + mem_mapping_t ram_mapping; + uint32_t base_address; + int base_irq; + uint32_t bios_addr; + uint8_t maclocal[6]; /* configured MAC (local) address */ struct { - uint8_t pstr; - uint8_t pspr; - uint8_t dqtr; - uint8_t bcfr; - uint8_t pcfr; - uint8_t gacfr; - uint8_t ctrl; - uint8_t streg; - uint8_t idcfr; - uint16_t da; - uint32_t vptr; - uint8_t rfmsb; - uint8_t rflsb; + uint8_t pstr; + uint8_t pspr; + uint8_t dqtr; + uint8_t bcfr; + uint8_t pcfr; + uint8_t gacfr; + uint8_t ctrl; + uint8_t streg; + uint8_t idcfr; + uint16_t da; + uint32_t vptr; + uint8_t rfmsb; + uint8_t rflsb; } regs; int dma_channel; } threec503_t; - #ifdef ENABLE_3COM503_LOG int threec503_do_log = ENABLE_3COM503_LOG; - static void threec503_log(const char *fmt, ...) { va_list ap; if (threec503_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define threec503_log(fmt, ...) +# define threec503_log(fmt, ...) #endif - static void threec503_interrupt(void *priv, int set) { threec503_t *dev = (threec503_t *) priv; switch (dev->base_irq) { - case 2: - dev->regs.idcfr = 0x10; - break; + case 2: + dev->regs.idcfr = 0x10; + break; - case 3: - dev->regs.idcfr = 0x20; - break; + case 3: + dev->regs.idcfr = 0x20; + break; - case 4: - dev->regs.idcfr = 0x40; - break; + case 4: + dev->regs.idcfr = 0x40; + break; - case 5: - dev->regs.idcfr = 0x80; - break; + case 5: + dev->regs.idcfr = 0x80; + break; } if (set) - picint(1 << dev->base_irq); + picint(1 << dev->base_irq); else - picintc(1 << dev->base_irq); + picintc(1 << dev->base_irq); } - static void threec503_ram_write(uint32_t addr, uint8_t val, void *priv) { - threec503_t *dev = (threec503_t *)priv; + threec503_t *dev = (threec503_t *) priv; if ((addr & 0x3fff) >= 0x2000) - return; + return; dev->dp8390->mem[addr & 0x1fff] = val; } - static uint8_t threec503_ram_read(uint32_t addr, void *priv) { - threec503_t *dev = (threec503_t *)priv; + threec503_t *dev = (threec503_t *) priv; if ((addr & 0x3fff) >= 0x2000) - return 0xff; + return 0xff; return dev->dp8390->mem[addr & 0x1fff]; } - static void threec503_set_drq(threec503_t *dev) { switch (dev->dma_channel) { - case 1: - dev->regs.idcfr = 1; - break; + case 1: + dev->regs.idcfr = 1; + break; - case 2: - dev->regs.idcfr = 2; - break; + case 2: + dev->regs.idcfr = 2; + break; - case 3: - dev->regs.idcfr = 4; - break; + case 3: + dev->regs.idcfr = 4; + break; } } - /* reset - restore state to power-up, cancelling all i/o */ static void threec503_reset(void *priv) { - threec503_t *dev = (threec503_t *)priv; + threec503_t *dev = (threec503_t *) priv; #ifdef ENABLE_3COM503_LOG threec503_log("3Com503: reset\n"); @@ -200,374 +193,370 @@ threec503_reset(void *priv) dev->regs.ctrl = 0x0a; } - static uint8_t threec503_nic_lo_read(uint16_t addr, void *priv) { - threec503_t *dev = (threec503_t *)priv; - uint8_t retval = 0; - int off = addr - dev->base_address; + threec503_t *dev = (threec503_t *) priv; + uint8_t retval = 0; + int off = addr - dev->base_address; switch ((dev->regs.ctrl >> 2) & 3) { - case 0x00: - threec503_log("Read offset=%04x\n", off); - if (off == 0x00) - retval = dp8390_read_cr(dev->dp8390); - else switch(dev->dp8390->CR.pgsel) { - case 0x00: - retval = dp8390_page0_read(dev->dp8390, off, 1); - break; + case 0x00: + threec503_log("Read offset=%04x\n", off); + if (off == 0x00) + retval = dp8390_read_cr(dev->dp8390); + else + switch (dev->dp8390->CR.pgsel) { + case 0x00: + retval = dp8390_page0_read(dev->dp8390, off, 1); + break; - case 0x01: - retval = dp8390_page1_read(dev->dp8390, off, 1); - break; + case 0x01: + retval = dp8390_page1_read(dev->dp8390, off, 1); + break; - case 0x02: - retval = dp8390_page2_read(dev->dp8390, off, 1); - break; + case 0x02: + retval = dp8390_page2_read(dev->dp8390, off, 1); + break; - case 0x03: - retval = 0xff; - break; - } - break; + case 0x03: + retval = 0xff; + break; + } + break; - case 0x01: - retval = dev->dp8390->macaddr[off]; - break; + case 0x01: + retval = dev->dp8390->macaddr[off]; + break; - case 0x02: - retval = dev->dp8390->macaddr[off + 0x10]; - break; + case 0x02: + retval = dev->dp8390->macaddr[off + 0x10]; + break; - case 0x03: - retval = 0xff; - break; + case 0x03: + retval = 0xff; + break; } - return(retval); + return (retval); } - static void threec503_nic_lo_write(uint16_t addr, uint8_t val, void *priv) { - threec503_t *dev = (threec503_t *)priv; - int off = addr - dev->base_address; + threec503_t *dev = (threec503_t *) priv; + int off = addr - dev->base_address; switch ((dev->regs.ctrl >> 2) & 3) { - case 0x00: - /* The high 16 bytes of i/o space are for the ne2000 asic - - the low 16 bytes are for the DS8390, with the current - page being selected by the PS0,PS1 registers in the - command register */ - if (off == 0x00) - dp8390_write_cr(dev->dp8390, val); - else switch(dev->dp8390->CR.pgsel) { - case 0x00: - dp8390_page0_write(dev->dp8390, off, val, 1); - break; + case 0x00: + /* The high 16 bytes of i/o space are for the ne2000 asic - + the low 16 bytes are for the DS8390, with the current + page being selected by the PS0,PS1 registers in the + command register */ + if (off == 0x00) + dp8390_write_cr(dev->dp8390, val); + else + switch (dev->dp8390->CR.pgsel) { + case 0x00: + dp8390_page0_write(dev->dp8390, off, val, 1); + break; - case 0x01: - dp8390_page1_write(dev->dp8390, off, val, 1); - break; + case 0x01: + dp8390_page1_write(dev->dp8390, off, val, 1); + break; - case 0x02: - dp8390_page2_write(dev->dp8390, off, val, 1); - break; + case 0x02: + dp8390_page2_write(dev->dp8390, off, val, 1); + break; - case 0x03: - break; - } - break; + case 0x03: + break; + } + break; - case 0x01: - case 0x02: - case 0x03: - break; + case 0x01: + case 0x02: + case 0x03: + break; } threec503_log("3Com503: write addr %x, value %x\n", addr, val); } - static uint8_t threec503_nic_hi_read(uint16_t addr, void *priv) { - threec503_t *dev = (threec503_t *)priv; + threec503_t *dev = (threec503_t *) priv; threec503_log("3Com503: Read GA address=%04x\n", addr); switch (addr & 0x0f) { - case 0x00: - return dev->regs.pstr; + case 0x00: + return dev->regs.pstr; - case 0x01: - return dev->regs.pspr; + case 0x01: + return dev->regs.pspr; - case 0x02: - return dev->regs.dqtr; + case 0x02: + return dev->regs.dqtr; - case 0x03: - switch (dev->base_address) { - default: - case 0x300: - dev->regs.bcfr = 0x80; - break; + case 0x03: + switch (dev->base_address) { + default: + case 0x300: + dev->regs.bcfr = 0x80; + break; - case 0x310: - dev->regs.bcfr = 0x40; - break; + case 0x310: + dev->regs.bcfr = 0x40; + break; - case 0x330: - dev->regs.bcfr = 0x20; - break; + case 0x330: + dev->regs.bcfr = 0x20; + break; - case 0x350: - dev->regs.bcfr = 0x10; - break; + case 0x350: + dev->regs.bcfr = 0x10; + break; - case 0x250: - dev->regs.bcfr = 0x08; - break; + case 0x250: + dev->regs.bcfr = 0x08; + break; - case 0x280: - dev->regs.bcfr = 0x04; - break; + case 0x280: + dev->regs.bcfr = 0x04; + break; - case 0x2a0: - dev->regs.bcfr = 0x02; - break; + case 0x2a0: + dev->regs.bcfr = 0x02; + break; - case 0x2e0: - dev->regs.bcfr = 0x01; - break; - } + case 0x2e0: + dev->regs.bcfr = 0x01; + break; + } - return dev->regs.bcfr; - break; + return dev->regs.bcfr; + break; - case 0x04: - switch (dev->bios_addr) { - case 0xdc000: - dev->regs.pcfr = 0x80; - break; + case 0x04: + switch (dev->bios_addr) { + case 0xdc000: + dev->regs.pcfr = 0x80; + break; - case 0xd8000: - dev->regs.pcfr = 0x40; - break; + case 0xd8000: + dev->regs.pcfr = 0x40; + break; - case 0xcc000: - dev->regs.pcfr = 0x20; - break; + case 0xcc000: + dev->regs.pcfr = 0x20; + break; - case 0xc8000: - dev->regs.pcfr = 0x10; - break; - } + case 0xc8000: + dev->regs.pcfr = 0x10; + break; + } - return dev->regs.pcfr; - break; + return dev->regs.pcfr; + break; - case 0x05: - return dev->regs.gacfr; + case 0x05: + return dev->regs.gacfr; - case 0x06: - return dev->regs.ctrl; + case 0x06: + return dev->regs.ctrl; - case 0x07: - return dev->regs.streg; + case 0x07: + return dev->regs.streg; - case 0x08: - return dev->regs.idcfr; + case 0x08: + return dev->regs.idcfr; - case 0x09: - return (dev->regs.da >> 8); + case 0x09: + return (dev->regs.da >> 8); - case 0x0a: - return (dev->regs.da & 0xff); + case 0x0a: + return (dev->regs.da & 0xff); - case 0x0b: - return (dev->regs.vptr >> 12) & 0xff; + case 0x0b: + return (dev->regs.vptr >> 12) & 0xff; - case 0x0c: - return (dev->regs.vptr >> 4) & 0xff; + case 0x0c: + return (dev->regs.vptr >> 4) & 0xff; - case 0x0d: - return (dev->regs.vptr & 0x0f) << 4; + case 0x0d: + return (dev->regs.vptr & 0x0f) << 4; - case 0x0e: - case 0x0f: - if (!(dev->regs.ctrl & 0x80)) - return 0xff; + case 0x0e: + case 0x0f: + if (!(dev->regs.ctrl & 0x80)) + return 0xff; - threec503_set_drq(dev); + threec503_set_drq(dev); - return dp8390_chipmem_read(dev->dp8390, dev->regs.da++, 1); + return dp8390_chipmem_read(dev->dp8390, dev->regs.da++, 1); } return 0; } - static void threec503_nic_hi_write(uint16_t addr, uint8_t val, void *priv) { - threec503_t *dev = (threec503_t *)priv; + threec503_t *dev = (threec503_t *) priv; threec503_log("3Com503: Write GA address=%04x, val=%04x\n", addr, val); switch (addr & 0x0f) { - case 0x00: - dev->regs.pstr = val; - break; + case 0x00: + dev->regs.pstr = val; + break; - case 0x01: - dev->regs.pspr = val; - break; + case 0x01: + dev->regs.pspr = val; + break; - case 0x02: - dev->regs.dqtr = val; - break; + case 0x02: + dev->regs.dqtr = val; + break; - case 0x05: - if ((dev->regs.gacfr & 0x0f) != (val & 0x0f)) { - switch (val & 0x0f) { - case 0: /*ROM mapping*/ - /* FIXME: Implement this when a BIOS is found/generated. */ - mem_mapping_disable(&dev->ram_mapping); - break; + case 0x05: + if ((dev->regs.gacfr & 0x0f) != (val & 0x0f)) { + switch (val & 0x0f) { + case 0: /*ROM mapping*/ + /* FIXME: Implement this when a BIOS is found/generated. */ + mem_mapping_disable(&dev->ram_mapping); + break; - case 9: /*RAM mapping*/ - mem_mapping_enable(&dev->ram_mapping); - break; + case 9: /*RAM mapping*/ + mem_mapping_enable(&dev->ram_mapping); + break; - default: /*No ROM mapping*/ - mem_mapping_disable(&dev->ram_mapping); - break; - } - } + default: /*No ROM mapping*/ + mem_mapping_disable(&dev->ram_mapping); + break; + } + } - if (!(val & 0x80)) - threec503_interrupt(dev, 1); - else - threec503_interrupt(dev, 0); + if (!(val & 0x80)) + threec503_interrupt(dev, 1); + else + threec503_interrupt(dev, 0); - dev->regs.gacfr = val; - break; + dev->regs.gacfr = val; + break; - case 0x06: - if (val & 1) { - threec503_reset(dev); - dev->dp8390->ISR.reset = 1; - dev->regs.ctrl = 0x0b; - return; - } + case 0x06: + if (val & 1) { + threec503_reset(dev); + dev->dp8390->ISR.reset = 1; + dev->regs.ctrl = 0x0b; + return; + } - if ((val & 0x80) != (dev->regs.ctrl & 0x80)) { - if (val & 0x80) - dev->regs.streg |= 0x88; - else - dev->regs.streg &= ~0x88; - dev->regs.streg &= ~0x10; - } - dev->regs.ctrl = val; - break; + if ((val & 0x80) != (dev->regs.ctrl & 0x80)) { + if (val & 0x80) + dev->regs.streg |= 0x88; + else + dev->regs.streg &= ~0x88; + dev->regs.streg &= ~0x10; + } + dev->regs.ctrl = val; + break; - case 0x08: - switch (val & 0xf0) { - case 0x00: - case 0x10: - case 0x20: - case 0x40: - case 0x80: - dev->regs.idcfr = (dev->regs.idcfr & 0x0f) | (val & 0xf0); - break; + case 0x08: + switch (val & 0xf0) { + case 0x00: + case 0x10: + case 0x20: + case 0x40: + case 0x80: + dev->regs.idcfr = (dev->regs.idcfr & 0x0f) | (val & 0xf0); + break; - default: - threec503_log("Trying to set multiple IRQs: %02x\n", val); - break; - } + default: + threec503_log("Trying to set multiple IRQs: %02x\n", val); + break; + } - switch (val & 0x0f) { - case 0x00: - case 0x01: - case 0x02: - case 0x04: - dev->regs.idcfr = (dev->regs.idcfr & 0xf0) | (val & 0x0f); - break; + switch (val & 0x0f) { + case 0x00: + case 0x01: + case 0x02: + case 0x04: + dev->regs.idcfr = (dev->regs.idcfr & 0xf0) | (val & 0x0f); + break; - case 0x08: - break; + case 0x08: + break; - default: - threec503_log("Trying to set multiple DMA channels: %02x\n", val); - break; - } - break; + default: + threec503_log("Trying to set multiple DMA channels: %02x\n", val); + break; + } + break; - case 0x09: - dev->regs.da = (val << 8) | (dev->regs.da & 0xff); - break; + case 0x09: + dev->regs.da = (val << 8) | (dev->regs.da & 0xff); + break; - case 0x0a: - dev->regs.da = (dev->regs.da & 0xff00) | val; - break; + case 0x0a: + dev->regs.da = (dev->regs.da & 0xff00) | val; + break; - case 0x0b: - dev->regs.vptr = (val << 12) | (dev->regs.vptr & 0xfff); - break; + case 0x0b: + dev->regs.vptr = (val << 12) | (dev->regs.vptr & 0xfff); + break; - case 0x0c: - dev->regs.vptr = (val << 4) | (dev->regs.vptr & 0xff00f); - break; + case 0x0c: + dev->regs.vptr = (val << 4) | (dev->regs.vptr & 0xff00f); + break; - case 0x0d: - dev->regs.vptr = (val << 4) | (dev->regs.vptr & 0xffff0); - break; + case 0x0d: + dev->regs.vptr = (val << 4) | (dev->regs.vptr & 0xffff0); + break; - case 0x0e: - case 0x0f: - if (!(dev->regs.ctrl & 0x80)) - return; + case 0x0e: + case 0x0f: + if (!(dev->regs.ctrl & 0x80)) + return; - threec503_set_drq(dev); + threec503_set_drq(dev); - dp8390_chipmem_write(dev->dp8390, dev->regs.da++, val, 1); - break; + dp8390_chipmem_write(dev->dp8390, dev->regs.da++, val, 1); + break; } } - static void threec503_nic_ioset(threec503_t *dev, uint16_t addr) { io_sethandler(addr, 0x10, - threec503_nic_lo_read, NULL, NULL, - threec503_nic_lo_write, NULL, NULL, dev); + threec503_nic_lo_read, NULL, NULL, + threec503_nic_lo_write, NULL, NULL, dev); - io_sethandler(addr+0x400, 0x10, - threec503_nic_hi_read, NULL, NULL, - threec503_nic_hi_write, NULL, NULL, dev); + io_sethandler(addr + 0x400, 0x10, + threec503_nic_hi_read, NULL, NULL, + threec503_nic_hi_write, NULL, NULL, dev); } - static void * threec503_nic_init(const device_t *info) { - uint32_t mac; + uint32_t mac; threec503_t *dev; dev = malloc(sizeof(threec503_t)); memset(dev, 0x00, sizeof(threec503_t)); - dev->maclocal[0] = 0x02; /* 02:60:8C (3Com OID) */ + dev->maclocal[0] = 0x02; /* 02:60:8C (3Com OID) */ dev->maclocal[1] = 0x60; dev->maclocal[2] = 0x8C; dev->base_address = device_get_config_hex16("base"); - dev->base_irq = device_get_config_int("irq"); - dev->dma_channel = device_get_config_int("dma"); - dev->bios_addr = device_get_config_hex20("bios_addr"); + dev->base_irq = device_get_config_int("irq"); + dev->dma_channel = device_get_config_int("dma"); + dev->bios_addr = device_get_config_hex20("bios_addr"); /* See if we have a local MAC address configured. */ mac = device_get_config_mac("mac", -1); @@ -580,22 +569,22 @@ threec503_nic_init(const device_t *info) /* Set up our BIA. */ if (mac & 0xff000000) { - /* Generate new local MAC. */ - dev->maclocal[3] = random_generate(); - dev->maclocal[4] = random_generate(); - dev->maclocal[5] = random_generate(); - mac = (((int) dev->maclocal[3]) << 16); - mac |= (((int) dev->maclocal[4]) << 8); - mac |= ((int) dev->maclocal[5]); - device_set_config_mac("mac", mac); + /* Generate new local MAC. */ + dev->maclocal[3] = random_generate(); + dev->maclocal[4] = random_generate(); + dev->maclocal[5] = random_generate(); + mac = (((int) dev->maclocal[3]) << 16); + mac |= (((int) dev->maclocal[4]) << 8); + mac |= ((int) dev->maclocal[5]); + device_set_config_mac("mac", mac); } else { - dev->maclocal[3] = (mac>>16) & 0xff; - dev->maclocal[4] = (mac>>8) & 0xff; - dev->maclocal[5] = (mac & 0xff); + dev->maclocal[3] = (mac >> 16) & 0xff; + dev->maclocal[4] = (mac >> 8) & 0xff; + dev->maclocal[5] = (mac & 0xff); } - dev->dp8390 = device_add_inst(&dp8390_device, dp3890_inst++); - dev->dp8390->priv = dev; + dev->dp8390 = device_add_inst(&dp8390_device, dp3890_inst++); + dev->dp8390->priv = dev; dev->dp8390->interrupt = threec503_interrupt; dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ); dp8390_mem_alloc(dev->dp8390, 0x2000, 0x2000); @@ -603,32 +592,31 @@ threec503_nic_init(const device_t *info) memcpy(dev->dp8390->physaddr, dev->maclocal, sizeof(dev->maclocal)); threec503_log("I/O=%04x, IRQ=%d, MAC=%02x:%02x:%02x:%02x:%02x:%02x\n", - dev->base_address, dev->base_irq, - dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2], - dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]); + dev->base_address, dev->base_irq, + dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2], + dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]); /* Reset the board. */ threec503_reset(dev); /* Map this system into the memory map. */ mem_mapping_add(&dev->ram_mapping, dev->bios_addr, 0x4000, - threec503_ram_read, NULL, NULL, - threec503_ram_write, NULL, NULL, - NULL, MEM_MAPPING_EXTERNAL, dev); + threec503_ram_read, NULL, NULL, + threec503_ram_write, NULL, NULL, + NULL, MEM_MAPPING_EXTERNAL, dev); // mem_mapping_disable(&dev->ram_mapping); - dev->regs.gacfr = 0x09; /* Start with RAM mapping enabled. */ + dev->regs.gacfr = 0x09; /* Start with RAM mapping enabled. */ /* Attach ourselves to the network module. */ dev->dp8390->card = network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL); - return(dev); + return (dev); } - static void threec503_nic_close(void *priv) { - threec503_t *dev = (threec503_t *)priv; + threec503_t *dev = (threec503_t *) priv; #ifdef ENABLE_3COM503_LOG threec503_log("3Com503: closed\n"); @@ -638,7 +626,7 @@ threec503_nic_close(void *priv) } static const device_config_t threec503_config[] = { -// clang-format off + // clang-format off { .name = "base", .description = "Address", diff --git a/src/network/net_dp8390.c b/src/network/net_dp8390.c index ad4345ae6..bc8f79843 100644 --- a/src/network/net_dp8390.c +++ b/src/network/net_dp8390.c @@ -30,10 +30,9 @@ #include <86box/network.h> #include <86box/net_dp8390.h> - -static void dp8390_tx(dp8390_t *dev, uint32_t val); -static int dp8390_rx_common(void *priv, uint8_t *buf, int io_len); -int dp8390_rx(void *priv, uint8_t *buf, int io_len); +static void dp8390_tx(dp8390_t *dev, uint32_t val); +static int dp8390_rx_common(void *priv, uint8_t *buf, int io_len); +int dp8390_rx(void *priv, uint8_t *buf, int io_len); int dp3890_inst = 0; @@ -45,17 +44,16 @@ dp8390_log(const char *fmt, ...) { va_list ap; -// if (dp8390_do_log >= lvl) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); -// } + // if (dp8390_do_log >= lvl) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + // } } #else -#define dp8390_log(lvl, fmt, ...) +# define dp8390_log(lvl, fmt, ...) #endif - /* * Return the 6-bit index into the multicast * table. Stolen unashamedly from FreeBSD's if_ed.c @@ -65,25 +63,24 @@ mcast_index(const void *dst) { #define POLYNOMIAL 0x04c11db6 uint32_t crc = 0xffffffffL; - int carry, i, j; - uint8_t b; - uint8_t *ep = (uint8_t *)dst; + int carry, i, j; + uint8_t b; + uint8_t *ep = (uint8_t *) dst; - for (i=6; --i>=0;) { - b = *ep++; - for (j = 8; --j >= 0;) { - carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); - crc <<= 1; - b >>= 1; - if (carry) - crc = ((crc ^ POLYNOMIAL) | carry); - } + for (i = 6; --i >= 0;) { + b = *ep++; + for (j = 8; --j >= 0;) { + carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); + crc <<= 1; + b >>= 1; + if (carry) + crc = ((crc ^ POLYNOMIAL) | carry); + } } - return(crc >> 26); + return (crc >> 26); #undef POLYNOMIAL } - /* * Access the 32K private RAM. * @@ -96,33 +93,32 @@ mcast_index(const void *dst) uint32_t dp8390_chipmem_read(dp8390_t *dev, uint32_t addr, unsigned int len) { - int i; + int i; uint32_t retval = 0; #ifdef ENABLE_DP8390_LOG if ((len > 1) && (addr & (len - 1))) - dp8390_log("DP8390: unaligned chipmem word read\n"); + dp8390_log("DP8390: unaligned chipmem word read\n"); #endif dp8390_log("DP8390: Chipmem Read Address=%04x\n", addr); /* ROM'd MAC address */ for (i = 0; i < len; i++) { - if ((addr >= dev->mem_start) && (addr < dev->mem_end)) - retval |= (uint32_t) (dev->mem[addr - dev->mem_start]) << (i << 3); - else if (addr < dev->macaddr_size) - retval |= ((uint32_t) dev->macaddr[addr & (dev->macaddr_size - 1)]) << (i << 3); - else { - dp8390_log("DP8390: out-of-bounds chipmem read, %04X\n", addr); - retval |= 0xff << (i << 3); - } - addr++; + if ((addr >= dev->mem_start) && (addr < dev->mem_end)) + retval |= (uint32_t) (dev->mem[addr - dev->mem_start]) << (i << 3); + else if (addr < dev->macaddr_size) + retval |= ((uint32_t) dev->macaddr[addr & (dev->macaddr_size - 1)]) << (i << 3); + else { + dp8390_log("DP8390: out-of-bounds chipmem read, %04X\n", addr); + retval |= 0xff << (i << 3); + } + addr++; } - return(retval); + return (retval); } - void dp8390_chipmem_write(dp8390_t *dev, uint32_t addr, uint32_t val, unsigned len) { @@ -130,41 +126,35 @@ dp8390_chipmem_write(dp8390_t *dev, uint32_t addr, uint32_t val, unsigned len) #ifdef ENABLE_DP8390_LOG if ((len > 1) && (addr & (len - 1))) - dp8390_log("DP8390: unaligned chipmem word write\n"); + dp8390_log("DP8390: unaligned chipmem word write\n"); #endif dp8390_log("DP8390: Chipmem Write Address=%04x\n", addr); for (i = 0; i < len; i++) { - if ((addr < dev->mem_start) || (addr >= dev->mem_end)) { - dp8390_log("DP8390: out-of-bounds chipmem write, %04X\n", addr); - return; - } + if ((addr < dev->mem_start) || (addr >= dev->mem_end)) { + dp8390_log("DP8390: out-of-bounds chipmem write, %04X\n", addr); + return; + } - dev->mem[addr - dev->mem_start] = val & 0xff; - val >>= 8; - addr++; + dev->mem[addr - dev->mem_start] = val & 0xff; + val >>= 8; + addr++; } } - /* Routines for handling reads/writes to the Command Register. */ uint32_t dp8390_read_cr(dp8390_t *dev) { uint32_t retval; - retval = (((dev->CR.pgsel & 0x03) << 6) | - ((dev->CR.rdma_cmd & 0x07) << 3) | - (dev->CR.tx_packet << 2) | - (dev->CR.start << 1) | - (dev->CR.stop)); + retval = (((dev->CR.pgsel & 0x03) << 6) | ((dev->CR.rdma_cmd & 0x07) << 3) | (dev->CR.tx_packet << 2) | (dev->CR.start << 1) | (dev->CR.stop)); dp8390_log("DP8390: read CR returns 0x%02x\n", retval); - return(retval); + return (retval); } - void dp8390_write_cr(dp8390_t *dev, uint32_t val) { @@ -173,17 +163,17 @@ dp8390_write_cr(dp8390_t *dev, uint32_t val) /* Validate remote-DMA */ if ((val & 0x38) == 0x00) { #ifdef ENABLE_DP8390_LOG - dp8390_log("DP8390: CR write - invalid rDMA value 0\n"); + dp8390_log("DP8390: CR write - invalid rDMA value 0\n"); #endif - val |= 0x20; /* dma_cmd == 4 is a safe default */ + val |= 0x20; /* dma_cmd == 4 is a safe default */ } /* Check for s/w reset */ if (val & 0x01) { - dev->ISR.reset = 1; - dev->CR.stop = 1; + dev->ISR.reset = 1; + dev->CR.stop = 1; } else { - dev->CR.stop = 0; + dev->CR.stop = 0; } dev->CR.rdma_cmd = (val & 0x38) >> 3; @@ -191,85 +181,82 @@ dp8390_write_cr(dp8390_t *dev, uint32_t val) /* If start command issued, the RST bit in the ISR */ /* must be cleared */ if ((val & 0x02) && !dev->CR.start) - dev->ISR.reset = 0; + dev->ISR.reset = 0; dev->CR.start = ((val & 0x02) == 0x02); dev->CR.pgsel = (val & 0xc0) >> 6; /* Check for send-packet command */ if (dev->CR.rdma_cmd == 3) { - /* Set up DMA read from receive ring */ - dev->remote_start = dev->remote_dma = dev->bound_ptr * 256; - dev->remote_bytes = (uint16_t) dp8390_chipmem_read(dev, dev->bound_ptr * 256 + 2, 2); - dp8390_log("DP8390: sending buffer #x%x length %d\n", - dev->remote_start, dev->remote_bytes); + /* Set up DMA read from receive ring */ + dev->remote_start = dev->remote_dma = dev->bound_ptr * 256; + dev->remote_bytes = (uint16_t) dp8390_chipmem_read(dev, dev->bound_ptr * 256 + 2, 2); + dp8390_log("DP8390: sending buffer #x%x length %d\n", + dev->remote_start, dev->remote_bytes); } /* Check for start-tx */ if ((val & 0x04) && dev->TCR.loop_cntl) { - if (dev->TCR.loop_cntl) { - dp8390_rx_common(dev, &dev->mem[(dev->tx_page_start * 256) - dev->mem_start], - dev->tx_bytes); - } + if (dev->TCR.loop_cntl) { + dp8390_rx_common(dev, &dev->mem[(dev->tx_page_start * 256) - dev->mem_start], + dev->tx_bytes); + } } else if (val & 0x04) { - if (dev->CR.stop || (!dev->CR.start && (dev->flags & DP8390_FLAG_CHECK_CR))) { - if (dev->tx_bytes == 0) /* njh@bandsman.co.uk */ - return; /* Solaris9 probe */ + if (dev->CR.stop || (!dev->CR.start && (dev->flags & DP8390_FLAG_CHECK_CR))) { + if (dev->tx_bytes == 0) /* njh@bandsman.co.uk */ + return; /* Solaris9 probe */ #ifdef ENABLE_DP8390_LOG - dp8390_log("DP8390: CR write - tx start, dev in reset\n"); + dp8390_log("DP8390: CR write - tx start, dev in reset\n"); #endif - } + } #ifdef ENABLE_DP8390_LOG - if (dev->tx_bytes == 0) - dp8390_log("DP8390: CR write - tx start, tx bytes == 0\n"); + if (dev->tx_bytes == 0) + dp8390_log("DP8390: CR write - tx start, tx bytes == 0\n"); #endif - /* Send the packet to the system driver */ - dev->CR.tx_packet = 1; + /* Send the packet to the system driver */ + dev->CR.tx_packet = 1; - /* TODO: report TX error to the driver ? */ - if (!(dev->card->link_state & NET_LINK_DOWN)) - network_tx(dev->card, &dev->mem[(dev->tx_page_start * 256) - dev->mem_start], dev->tx_bytes); + /* TODO: report TX error to the driver ? */ + if (!(dev->card->link_state & NET_LINK_DOWN)) + network_tx(dev->card, &dev->mem[(dev->tx_page_start * 256) - dev->mem_start], dev->tx_bytes); - /* some more debug */ + /* some more debug */ #ifdef ENABLE_DP8390_LOG - if (dev->tx_timer_active) - dp8390_log("DP8390: CR write, tx timer still active\n"); + if (dev->tx_timer_active) + dp8390_log("DP8390: CR write, tx timer still active\n"); #endif - dp8390_tx(dev, val); + dp8390_tx(dev, val); } /* Linux probes for an interrupt by setting up a remote-DMA read * of 0 bytes with remote-DMA completion interrupts enabled. * Detect this here */ - if ((dev->CR.rdma_cmd == 0x01) && dev->CR.start && - (dev->remote_bytes == 0)) { - dev->ISR.rdma_done = 1; - if (dev->IMR.rdma_inte && dev->interrupt) { - dev->interrupt(dev->priv, 1); - if (dev->flags & DP8390_FLAG_CLEAR_IRQ) - dev->interrupt(dev->priv, 0); - } + if ((dev->CR.rdma_cmd == 0x01) && dev->CR.start && (dev->remote_bytes == 0)) { + dev->ISR.rdma_done = 1; + if (dev->IMR.rdma_inte && dev->interrupt) { + dev->interrupt(dev->priv, 1); + if (dev->flags & DP8390_FLAG_CLEAR_IRQ) + dev->interrupt(dev->priv, 0); + } } } - static void dp8390_tx(dp8390_t *dev, uint32_t val) { dev->CR.tx_packet = 0; - dev->TSR.tx_ok = 1; - dev->ISR.pkt_tx = 1; + dev->TSR.tx_ok = 1; + dev->ISR.pkt_tx = 1; /* Generate an interrupt if not masked */ if (dev->IMR.tx_inte && dev->interrupt) - dev->interrupt(dev->priv, 1); + dev->interrupt(dev->priv, 1); dev->tx_timer_active = 0; } - /* * Called by the platform-specific code when an Ethernet frame * has been received. The destination address is tested to see @@ -279,32 +266,31 @@ dp8390_tx(dp8390_t *dev, uint32_t val) static int dp8390_rx_common(void *priv, uint8_t *buf, int io_len) { - dp8390_t *dev = (dp8390_t *)priv; - static uint8_t bcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff}; - uint8_t pkthdr[4]; - uint8_t *startptr; - int pages, avail; - int idx, nextpage; - int endbytes; + dp8390_t *dev = (dp8390_t *) priv; + static uint8_t bcast_addr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + uint8_t pkthdr[4]; + uint8_t *startptr; + int pages, avail; + int idx, nextpage; + int endbytes; if (io_len != 60) - dp8390_log("rx_frame with length %d\n", io_len); + dp8390_log("rx_frame with length %d\n", io_len); if ((dev->CR.stop != 0) || (dev->page_start == 0)) - return 0; + return 0; if (dev->card->link_state & NET_LINK_DOWN) - return 0; + return 0; /* * Add the pkt header + CRC to the length, and work * out how many 256-byte pages the frame would occupy. */ - pages = (io_len + sizeof(pkthdr) + sizeof(uint32_t) + 255)/256; + pages = (io_len + sizeof(pkthdr) + sizeof(uint32_t) + 255) / 256; if (dev->curr_page < dev->bound_ptr) { - avail = dev->bound_ptr - dev->curr_page; + avail = dev->bound_ptr - dev->curr_page; } else { - avail = (dev->page_stop - dev->page_start) - - (dev->curr_page - dev->bound_ptr); + avail = (dev->page_stop - dev->page_start) - (dev->curr_page - dev->bound_ptr); } /* @@ -312,128 +298,125 @@ dp8390_rx_common(void *priv, uint8_t *buf, int io_len) * not attempting to do partial receives. The emulation * to handle this condition seems particularly painful. */ - if ((avail < pages) + if ((avail < pages) #if DP8390_NEVER_FULL_RING - || (avail == pages) + || (avail == pages) #endif - ) { + ) { #ifdef ENABLE_DP8390_LOG - dp8390_log("DP8390: no space\n"); + dp8390_log("DP8390: no space\n"); #endif - return 0; + return 0; } - if ((io_len < 40/*60*/) && !dev->RCR.runts_ok) { + if ((io_len < 40 /*60*/) && !dev->RCR.runts_ok) { #ifdef ENABLE_DP8390_LOG - dp8390_log("DP8390: rejected small packet, length %d\n", io_len); + dp8390_log("DP8390: rejected small packet, length %d\n", io_len); #endif - return 1; + return 1; } /* Some computers don't care... */ if (io_len < 60) - io_len = 60; + io_len = 60; dp8390_log("DP8390: RX %x:%x:%x:%x:%x:%x > %x:%x:%x:%x:%x:%x len %d\n", - buf[6], buf[7], buf[8], buf[9], buf[10], buf[11], - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], - io_len); + buf[6], buf[7], buf[8], buf[9], buf[10], buf[11], + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], + io_len); /* Do address filtering if not in promiscuous mode. */ - if (! dev->RCR.promisc) { - /* If this is a broadcast frame.. */ - if (! memcmp(buf, bcast_addr, 6)) { - /* Broadcast not enabled, we're done. */ - if (! dev->RCR.broadcast) { + if (!dev->RCR.promisc) { + /* If this is a broadcast frame.. */ + if (!memcmp(buf, bcast_addr, 6)) { + /* Broadcast not enabled, we're done. */ + if (!dev->RCR.broadcast) { #ifdef ENABLE_DP8390_LOG - dp8390_log("DP8390: RX BC disabled\n"); + dp8390_log("DP8390: RX BC disabled\n"); #endif - return 1; - } - } + return 1; + } + } - /* If this is a multicast frame.. */ - else if (buf[0] & 0x01) { - /* Multicast not enabled, we're done. */ - if (! dev->RCR.multicast) { + /* If this is a multicast frame.. */ + else if (buf[0] & 0x01) { + /* Multicast not enabled, we're done. */ + if (!dev->RCR.multicast) { #ifdef ENABLE_DP8390_LOG - dp8390_log("DP8390: RX MC disabled\n"); + dp8390_log("DP8390: RX MC disabled\n"); #endif - return 1; - } + return 1; + } - /* Are we listening to this multicast address? */ - idx = mcast_index(buf); - if (! (dev->mchash[idx>>3] & (1<<(idx&0x7)))) { + /* Are we listening to this multicast address? */ + idx = mcast_index(buf); + if (!(dev->mchash[idx >> 3] & (1 << (idx & 0x7)))) { #ifdef ENABLE_DP8390_LOG - dp8390_log("DP8390: RX MC not listed\n"); + dp8390_log("DP8390: RX MC not listed\n"); #endif - return 1; - } - } + return 1; + } + } - /* Unicast, must be for us.. */ - else if (memcmp(buf, dev->physaddr, 6)) - return 1; + /* Unicast, must be for us.. */ + else if (memcmp(buf, dev->physaddr, 6)) + return 1; } else { #ifdef ENABLE_DP8390_LOG - dp8390_log("DP8390: RX promiscuous receive\n"); + dp8390_log("DP8390: RX promiscuous receive\n"); #endif } nextpage = dev->curr_page + pages; if (nextpage >= dev->page_stop) - nextpage -= (dev->page_stop - dev->page_start); + nextpage -= (dev->page_stop - dev->page_start); /* Set up packet header. */ - pkthdr[0] = 0x01; /* RXOK - packet is OK */ + pkthdr[0] = 0x01; /* RXOK - packet is OK */ if (buf[0] & 0x01) - pkthdr[0] |= 0x20; /* MULTICAST packet */ - pkthdr[1] = nextpage; /* ptr to next packet */ - pkthdr[2] = (io_len + sizeof(pkthdr))&0xff; /* length-low */ - pkthdr[3] = (io_len + sizeof(pkthdr))>>8; /* length-hi */ + pkthdr[0] |= 0x20; /* MULTICAST packet */ + pkthdr[1] = nextpage; /* ptr to next packet */ + pkthdr[2] = (io_len + sizeof(pkthdr)) & 0xff; /* length-low */ + pkthdr[3] = (io_len + sizeof(pkthdr)) >> 8; /* length-hi */ dp8390_log("DP8390: RX pkthdr [%02x %02x %02x %02x]\n", - pkthdr[0], pkthdr[1], pkthdr[2], pkthdr[3]); + pkthdr[0], pkthdr[1], pkthdr[2], pkthdr[3]); /* Copy into buffer, update curpage, and signal interrupt if config'd */ startptr = &dev->mem[(dev->curr_page * 256) - dev->mem_start]; memcpy(startptr, pkthdr, sizeof(pkthdr)); - if ((nextpage > dev->curr_page) || - ((dev->curr_page + pages) == dev->page_stop)) { - memcpy(startptr+sizeof(pkthdr), buf, io_len); + if ((nextpage > dev->curr_page) || ((dev->curr_page + pages) == dev->page_stop)) { + memcpy(startptr + sizeof(pkthdr), buf, io_len); } else { - endbytes = (dev->page_stop - dev->curr_page) * 256; - memcpy(startptr+sizeof(pkthdr), buf, endbytes-sizeof(pkthdr)); - startptr = &dev->mem[(dev->page_start * 256) - dev->mem_start]; - memcpy(startptr, buf+endbytes-sizeof(pkthdr), io_len-endbytes+8); + endbytes = (dev->page_stop - dev->curr_page) * 256; + memcpy(startptr + sizeof(pkthdr), buf, endbytes - sizeof(pkthdr)); + startptr = &dev->mem[(dev->page_start * 256) - dev->mem_start]; + memcpy(startptr, buf + endbytes - sizeof(pkthdr), io_len - endbytes + 8); } dev->curr_page = nextpage; - dev->RSR.rx_ok = 1; + dev->RSR.rx_ok = 1; dev->RSR.rx_mbit = (buf[0] & 0x01) ? 1 : 0; - dev->ISR.pkt_rx = 1; + dev->ISR.pkt_rx = 1; if (dev->IMR.rx_inte && dev->interrupt) - dev->interrupt(dev->priv, 1); + dev->interrupt(dev->priv, 1); return 1; } - int dp8390_rx(void *priv, uint8_t *buf, int io_len) { - dp8390_t *dev = (dp8390_t *)priv; + dp8390_t *dev = (dp8390_t *) priv; if ((dev->DCR.loop == 0) || (dev->TCR.loop_cntl != 0)) - return 0; + return 0; - return dp8390_rx_common(priv, buf, io_len); + return dp8390_rx_common(priv, buf, io_len); } - /* Handle reads/writes to the 'zeroth' page of the DS8390 register file. */ uint32_t dp8390_page0_read(dp8390_t *dev, uint32_t off, unsigned int len) @@ -441,547 +424,484 @@ dp8390_page0_read(dp8390_t *dev, uint32_t off, unsigned int len) uint8_t retval = 0; if (len > 1) { - /* encountered with win98 hardware probe */ - dp8390_log("DP8390: bad length! Page0 read from register 0x%02x, len=%u\n", - off, len); - return(retval); + /* encountered with win98 hardware probe */ + dp8390_log("DP8390: bad length! Page0 read from register 0x%02x, len=%u\n", + off, len); + return (retval); } - switch(off) { - case 0x01: /* CLDA0 */ - retval = (dev->local_dma & 0xff); - break; + switch (off) { + case 0x01: /* CLDA0 */ + retval = (dev->local_dma & 0xff); + break; - case 0x02: /* CLDA1 */ - retval = (dev->local_dma >> 8); - break; + case 0x02: /* CLDA1 */ + retval = (dev->local_dma >> 8); + break; - case 0x03: /* BNRY */ - retval = dev->bound_ptr; - break; + case 0x03: /* BNRY */ + retval = dev->bound_ptr; + break; - case 0x04: /* TSR */ - retval = ((dev->TSR.ow_coll << 7) | - (dev->TSR.cd_hbeat << 6) | - (dev->TSR.fifo_ur << 5) | - (dev->TSR.no_carrier << 4) | - (dev->TSR.aborted << 3) | - (dev->TSR.collided << 2) | - (dev->TSR.tx_ok)); - break; + case 0x04: /* TSR */ + retval = ((dev->TSR.ow_coll << 7) | (dev->TSR.cd_hbeat << 6) | (dev->TSR.fifo_ur << 5) | (dev->TSR.no_carrier << 4) | (dev->TSR.aborted << 3) | (dev->TSR.collided << 2) | (dev->TSR.tx_ok)); + break; - case 0x05: /* NCR */ - retval = dev->num_coll; - break; + case 0x05: /* NCR */ + retval = dev->num_coll; + break; - case 0x06: /* FIFO */ - /* reading FIFO is only valid in loopback mode */ + case 0x06: /* FIFO */ + /* reading FIFO is only valid in loopback mode */ #ifdef ENABLE_DP8390_LOG - dp8390_log("DP8390: reading FIFO not supported yet\n"); + dp8390_log("DP8390: reading FIFO not supported yet\n"); #endif - retval = dev->fifo; - break; + retval = dev->fifo; + break; - case 0x07: /* ISR */ - retval = ((dev->ISR.reset << 7) | - (dev->ISR.rdma_done << 6) | - (dev->ISR.cnt_oflow << 5) | - (dev->ISR.overwrite << 4) | - (dev->ISR.tx_err << 3) | - (dev->ISR.rx_err << 2) | - (dev->ISR.pkt_tx << 1) | - (dev->ISR.pkt_rx)); - break; + case 0x07: /* ISR */ + retval = ((dev->ISR.reset << 7) | (dev->ISR.rdma_done << 6) | (dev->ISR.cnt_oflow << 5) | (dev->ISR.overwrite << 4) | (dev->ISR.tx_err << 3) | (dev->ISR.rx_err << 2) | (dev->ISR.pkt_tx << 1) | (dev->ISR.pkt_rx)); + break; - case 0x08: /* CRDA0 */ - retval = (dev->remote_dma & 0xff); - break; + case 0x08: /* CRDA0 */ + retval = (dev->remote_dma & 0xff); + break; - case 0x09: /* CRDA1 */ - retval = (dev->remote_dma >> 8); - break; + case 0x09: /* CRDA1 */ + retval = (dev->remote_dma >> 8); + break; - case 0x0a: /* reserved / RTL8029ID0 */ - retval = dev->id0; - break; + case 0x0a: /* reserved / RTL8029ID0 */ + retval = dev->id0; + break; - case 0x0b: /* reserved / RTL8029ID1 */ - retval = dev->id1; - break; + case 0x0b: /* reserved / RTL8029ID1 */ + retval = dev->id1; + break; - case 0x0c: /* RSR */ - retval = ((dev->RSR.deferred << 7) | - (dev->RSR.rx_disabled << 6) | - (dev->RSR.rx_mbit << 5) | - (dev->RSR.rx_missed << 4) | - (dev->RSR.fifo_or << 3) | - (dev->RSR.bad_falign << 2) | - (dev->RSR.bad_crc << 1) | - (dev->RSR.rx_ok)); - break; + case 0x0c: /* RSR */ + retval = ((dev->RSR.deferred << 7) | (dev->RSR.rx_disabled << 6) | (dev->RSR.rx_mbit << 5) | (dev->RSR.rx_missed << 4) | (dev->RSR.fifo_or << 3) | (dev->RSR.bad_falign << 2) | (dev->RSR.bad_crc << 1) | (dev->RSR.rx_ok)); + break; - case 0x0d: /* CNTR0 */ - retval = dev->tallycnt_0; - break; + case 0x0d: /* CNTR0 */ + retval = dev->tallycnt_0; + break; - case 0x0e: /* CNTR1 */ - retval = dev->tallycnt_1; - break; + case 0x0e: /* CNTR1 */ + retval = dev->tallycnt_1; + break; - case 0x0f: /* CNTR2 */ - retval = dev->tallycnt_2; - break; + case 0x0f: /* CNTR2 */ + retval = dev->tallycnt_2; + break; - default: - dp8390_log("DP8390: Page0 register 0x%02x out of range\n", off); - break; + default: + dp8390_log("DP8390: Page0 register 0x%02x out of range\n", off); + break; } dp8390_log("DP8390: Page0 read from register 0x%02x, value=0x%02x\n", off, - retval); + retval); - return(retval); + return (retval); } - void dp8390_page0_write(dp8390_t *dev, uint32_t off, uint32_t val, unsigned len) { uint8_t val2; dp8390_log("DP839: Page0 write to register 0x%02x, value=0x%02x\n", - off, val); + off, val); - switch(off) { - case 0x01: /* PSTART */ - dev->page_start = val; - dp8390_log("DP8390: Starting RAM address: %04X\n", val << 8); - break; + switch (off) { + case 0x01: /* PSTART */ + dev->page_start = val; + dp8390_log("DP8390: Starting RAM address: %04X\n", val << 8); + break; - case 0x02: /* PSTOP */ - dev->page_stop = val; - dp8390_log("DP8390: Stopping RAM address: %04X\n", val << 8); - break; + case 0x02: /* PSTOP */ + dev->page_stop = val; + dp8390_log("DP8390: Stopping RAM address: %04X\n", val << 8); + break; - case 0x03: /* BNRY */ - dev->bound_ptr = val; - break; + case 0x03: /* BNRY */ + dev->bound_ptr = val; + break; - case 0x04: /* TPSR */ - dev->tx_page_start = val; - break; + case 0x04: /* TPSR */ + dev->tx_page_start = val; + break; - case 0x05: /* TBCR0 */ - /* Clear out low byte and re-insert */ - dev->tx_bytes &= 0xff00; - dev->tx_bytes |= (val & 0xff); - break; + case 0x05: /* TBCR0 */ + /* Clear out low byte and re-insert */ + dev->tx_bytes &= 0xff00; + dev->tx_bytes |= (val & 0xff); + break; - case 0x06: /* TBCR1 */ - /* Clear out high byte and re-insert */ - dev->tx_bytes &= 0x00ff; - dev->tx_bytes |= ((val & 0xff) << 8); - break; + case 0x06: /* TBCR1 */ + /* Clear out high byte and re-insert */ + dev->tx_bytes &= 0x00ff; + dev->tx_bytes |= ((val & 0xff) << 8); + break; - case 0x07: /* ISR */ - val &= 0x7f; /* clear RST bit - status-only bit */ - /* All other values are cleared iff the ISR bit is 1 */ - dev->ISR.pkt_rx &= !((int)((val & 0x01) == 0x01)); - dev->ISR.pkt_tx &= !((int)((val & 0x02) == 0x02)); - dev->ISR.rx_err &= !((int)((val & 0x04) == 0x04)); - dev->ISR.tx_err &= !((int)((val & 0x08) == 0x08)); - dev->ISR.overwrite &= !((int)((val & 0x10) == 0x10)); - dev->ISR.cnt_oflow &= !((int)((val & 0x20) == 0x20)); - dev->ISR.rdma_done &= !((int)((val & 0x40) == 0x40)); - val = ((dev->ISR.rdma_done << 6) | - (dev->ISR.cnt_oflow << 5) | - (dev->ISR.overwrite << 4) | - (dev->ISR.tx_err << 3) | - (dev->ISR.rx_err << 2) | - (dev->ISR.pkt_tx << 1) | - (dev->ISR.pkt_rx)); - val &= ((dev->IMR.rdma_inte << 6) | - (dev->IMR.cofl_inte << 5) | - (dev->IMR.overw_inte << 4) | - (dev->IMR.txerr_inte << 3) | - (dev->IMR.rxerr_inte << 2) | - (dev->IMR.tx_inte << 1) | - (dev->IMR.rx_inte)); - if ((val == 0x00) && dev->interrupt) - dev->interrupt(dev->priv, 0); - break; + case 0x07: /* ISR */ + val &= 0x7f; /* clear RST bit - status-only bit */ + /* All other values are cleared iff the ISR bit is 1 */ + dev->ISR.pkt_rx &= !((int) ((val & 0x01) == 0x01)); + dev->ISR.pkt_tx &= !((int) ((val & 0x02) == 0x02)); + dev->ISR.rx_err &= !((int) ((val & 0x04) == 0x04)); + dev->ISR.tx_err &= !((int) ((val & 0x08) == 0x08)); + dev->ISR.overwrite &= !((int) ((val & 0x10) == 0x10)); + dev->ISR.cnt_oflow &= !((int) ((val & 0x20) == 0x20)); + dev->ISR.rdma_done &= !((int) ((val & 0x40) == 0x40)); + val = ((dev->ISR.rdma_done << 6) | (dev->ISR.cnt_oflow << 5) | (dev->ISR.overwrite << 4) | (dev->ISR.tx_err << 3) | (dev->ISR.rx_err << 2) | (dev->ISR.pkt_tx << 1) | (dev->ISR.pkt_rx)); + val &= ((dev->IMR.rdma_inte << 6) | (dev->IMR.cofl_inte << 5) | (dev->IMR.overw_inte << 4) | (dev->IMR.txerr_inte << 3) | (dev->IMR.rxerr_inte << 2) | (dev->IMR.tx_inte << 1) | (dev->IMR.rx_inte)); + if ((val == 0x00) && dev->interrupt) + dev->interrupt(dev->priv, 0); + break; - case 0x08: /* RSAR0 */ - /* Clear out low byte and re-insert */ - dev->remote_start &= 0xff00; - dev->remote_start |= (val & 0xff); - dev->remote_dma = dev->remote_start; - break; + case 0x08: /* RSAR0 */ + /* Clear out low byte and re-insert */ + dev->remote_start &= 0xff00; + dev->remote_start |= (val & 0xff); + dev->remote_dma = dev->remote_start; + break; - case 0x09: /* RSAR1 */ - /* Clear out high byte and re-insert */ - dev->remote_start &= 0x00ff; - dev->remote_start |= ((val & 0xff) << 8); - dev->remote_dma = dev->remote_start; - break; + case 0x09: /* RSAR1 */ + /* Clear out high byte and re-insert */ + dev->remote_start &= 0x00ff; + dev->remote_start |= ((val & 0xff) << 8); + dev->remote_dma = dev->remote_start; + break; - case 0x0a: /* RBCR0 */ - /* Clear out low byte and re-insert */ - dev->remote_bytes &= 0xff00; - dev->remote_bytes |= (val & 0xff); - break; + case 0x0a: /* RBCR0 */ + /* Clear out low byte and re-insert */ + dev->remote_bytes &= 0xff00; + dev->remote_bytes |= (val & 0xff); + break; - case 0x0b: /* RBCR1 */ - /* Clear out high byte and re-insert */ - dev->remote_bytes &= 0x00ff; - dev->remote_bytes |= ((val & 0xff) << 8); - break; + case 0x0b: /* RBCR1 */ + /* Clear out high byte and re-insert */ + dev->remote_bytes &= 0x00ff; + dev->remote_bytes |= ((val & 0xff) << 8); + break; - case 0x0c: /* RCR */ - /* Check if the reserved bits are set */ + case 0x0c: /* RCR */ + /* Check if the reserved bits are set */ #ifdef ENABLE_DP8390_LOG - if (val & 0xc0) - dp8390_log("DP8390: RCR write, reserved bits set\n"); + if (val & 0xc0) + dp8390_log("DP8390: RCR write, reserved bits set\n"); #endif - /* Set all other bit-fields */ - dev->RCR.errors_ok = ((val & 0x01) == 0x01); - dev->RCR.runts_ok = ((val & 0x02) == 0x02); - dev->RCR.broadcast = ((val & 0x04) == 0x04); - dev->RCR.multicast = ((val & 0x08) == 0x08); - dev->RCR.promisc = ((val & 0x10) == 0x10); - dev->RCR.monitor = ((val & 0x20) == 0x20); + /* Set all other bit-fields */ + dev->RCR.errors_ok = ((val & 0x01) == 0x01); + dev->RCR.runts_ok = ((val & 0x02) == 0x02); + dev->RCR.broadcast = ((val & 0x04) == 0x04); + dev->RCR.multicast = ((val & 0x08) == 0x08); + dev->RCR.promisc = ((val & 0x10) == 0x10); + dev->RCR.monitor = ((val & 0x20) == 0x20); - /* Monitor bit is a little suspicious... */ + /* Monitor bit is a little suspicious... */ #ifdef ENABLE_DP8390_LOG - if (val & 0x20) - dp8390_log("DP8390: RCR write, monitor bit set!\n"); + if (val & 0x20) + dp8390_log("DP8390: RCR write, monitor bit set!\n"); #endif - break; + break; - case 0x0d: /* TCR */ - /* Check reserved bits */ + case 0x0d: /* TCR */ + /* Check reserved bits */ #ifdef ENABLE_DP8390_LOG - if (val & 0xe0) - dp8390_log("DP8390: TCR write, reserved bits set\n"); + if (val & 0xe0) + dp8390_log("DP8390: TCR write, reserved bits set\n"); #endif - /* Test loop mode (not supported) */ - if (val & 0x06) { - dev->TCR.loop_cntl = (val & 0x6) >> 1; - dp8390_log("DP8390: TCR write, loop mode %d not supported\n", - dev->TCR.loop_cntl); - } else - dev->TCR.loop_cntl = 0; + /* Test loop mode (not supported) */ + if (val & 0x06) { + dev->TCR.loop_cntl = (val & 0x6) >> 1; + dp8390_log("DP8390: TCR write, loop mode %d not supported\n", + dev->TCR.loop_cntl); + } else + dev->TCR.loop_cntl = 0; - /* Inhibit-CRC not supported. */ + /* Inhibit-CRC not supported. */ #ifdef ENABLE_DP8390_LOG - if (val & 0x01) - dp8390_log("DP8390: TCR write, inhibit-CRC not supported\n"); + if (val & 0x01) + dp8390_log("DP8390: TCR write, inhibit-CRC not supported\n"); #endif - /* Auto-transmit disable very suspicious */ + /* Auto-transmit disable very suspicious */ #ifdef ENABLE_DP8390_LOG - if (val & 0x08) - dp8390_log("DP8390: TCR write, auto transmit disable not supported\n"); + if (val & 0x08) + dp8390_log("DP8390: TCR write, auto transmit disable not supported\n"); #endif - /* Allow collision-offset to be set, although not used */ - dev->TCR.coll_prio = ((val & 0x08) == 0x08); - break; + /* Allow collision-offset to be set, although not used */ + dev->TCR.coll_prio = ((val & 0x08) == 0x08); + break; - case 0x0e: /* DCR */ - /* the loopback mode is not suppported yet */ + case 0x0e: /* DCR */ + /* the loopback mode is not suppported yet */ #ifdef ENABLE_DP8390_LOG - if (! (val & 0x08)) - dp8390_log("DP8390: DCR write, loopback mode selected\n"); + if (!(val & 0x08)) + dp8390_log("DP8390: DCR write, loopback mode selected\n"); #endif - /* It is questionable to set longaddr and auto_rx, since - * they are not supported on the NE2000. Print a warning - * and continue. */ + /* It is questionable to set longaddr and auto_rx, since + * they are not supported on the NE2000. Print a warning + * and continue. */ #ifdef ENABLE_DP8390_LOG - if (val & 0x04) - dp8390_log("DP8390: DCR write - LAS set ???\n"); - if (val & 0x10) - dp8390_log("DP8390: DCR write - AR set ???\n"); + if (val & 0x04) + dp8390_log("DP8390: DCR write - LAS set ???\n"); + if (val & 0x10) + dp8390_log("DP8390: DCR write - AR set ???\n"); #endif - /* Set other values. */ - dev->DCR.wdsize = ((val & 0x01) == 0x01); - dev->DCR.endian = ((val & 0x02) == 0x02); - dev->DCR.longaddr = ((val & 0x04) == 0x04); /* illegal ? */ - dev->DCR.loop = ((val & 0x08) == 0x08); - dev->DCR.auto_rx = ((val & 0x10) == 0x10); /* also illegal ? */ - dev->DCR.fifo_size = (val & 0x60) >> 5; - break; + /* Set other values. */ + dev->DCR.wdsize = ((val & 0x01) == 0x01); + dev->DCR.endian = ((val & 0x02) == 0x02); + dev->DCR.longaddr = ((val & 0x04) == 0x04); /* illegal ? */ + dev->DCR.loop = ((val & 0x08) == 0x08); + dev->DCR.auto_rx = ((val & 0x10) == 0x10); /* also illegal ? */ + dev->DCR.fifo_size = (val & 0x60) >> 5; + break; - case 0x0f: /* IMR */ - /* Check for reserved bit */ + case 0x0f: /* IMR */ + /* Check for reserved bit */ #ifdef ENABLE_DP8390_LOG - if (val & 0x80) - dp8390_log("DP8390: IMR write, reserved bit set\n"); + if (val & 0x80) + dp8390_log("DP8390: IMR write, reserved bit set\n"); #endif - /* Set other values */ - dev->IMR.rx_inte = ((val & 0x01) == 0x01); - dev->IMR.tx_inte = ((val & 0x02) == 0x02); - dev->IMR.rxerr_inte = ((val & 0x04) == 0x04); - dev->IMR.txerr_inte = ((val & 0x08) == 0x08); - dev->IMR.overw_inte = ((val & 0x10) == 0x10); - dev->IMR.cofl_inte = ((val & 0x20) == 0x20); - dev->IMR.rdma_inte = ((val & 0x40) == 0x40); - val2 = ((dev->ISR.rdma_done << 6) | - (dev->ISR.cnt_oflow << 5) | - (dev->ISR.overwrite << 4) | - (dev->ISR.tx_err << 3) | - (dev->ISR.rx_err << 2) | - (dev->ISR.pkt_tx << 1) | - (dev->ISR.pkt_rx)); - if (dev->interrupt) { - if (((val & val2) & 0x7f) == 0) - dev->interrupt(dev->priv, 0); - else - dev->interrupt(dev->priv, 1); - } - break; + /* Set other values */ + dev->IMR.rx_inte = ((val & 0x01) == 0x01); + dev->IMR.tx_inte = ((val & 0x02) == 0x02); + dev->IMR.rxerr_inte = ((val & 0x04) == 0x04); + dev->IMR.txerr_inte = ((val & 0x08) == 0x08); + dev->IMR.overw_inte = ((val & 0x10) == 0x10); + dev->IMR.cofl_inte = ((val & 0x20) == 0x20); + dev->IMR.rdma_inte = ((val & 0x40) == 0x40); + val2 = ((dev->ISR.rdma_done << 6) | (dev->ISR.cnt_oflow << 5) | (dev->ISR.overwrite << 4) | (dev->ISR.tx_err << 3) | (dev->ISR.rx_err << 2) | (dev->ISR.pkt_tx << 1) | (dev->ISR.pkt_rx)); + if (dev->interrupt) { + if (((val & val2) & 0x7f) == 0) + dev->interrupt(dev->priv, 0); + else + dev->interrupt(dev->priv, 1); + } + break; - default: - dp8390_log("DP8390: Page0 write, bad register 0x%02x\n", off); - break; + default: + dp8390_log("DP8390: Page0 write, bad register 0x%02x\n", off); + break; } } - /* Handle reads/writes to the first page of the DS8390 register file. */ uint32_t dp8390_page1_read(dp8390_t *dev, uint32_t off, unsigned int len) { dp8390_log("DP8390: Page1 read from register 0x%02x, len=%u\n", - off, len); + off, len); - switch(off) { - case 0x01: /* PAR0-5 */ - case 0x02: - case 0x03: - case 0x04: - case 0x05: - case 0x06: - return(dev->physaddr[off - 1]); + switch (off) { + case 0x01: /* PAR0-5 */ + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + return (dev->physaddr[off - 1]); - case 0x07: /* CURR */ - dp8390_log("DP8390: returning current page: 0x%02x\n", - (dev->curr_page)); - return(dev->curr_page); + case 0x07: /* CURR */ + dp8390_log("DP8390: returning current page: 0x%02x\n", + (dev->curr_page)); + return (dev->curr_page); - case 0x08: /* MAR0-7 */ - case 0x09: - case 0x0a: - case 0x0b: - case 0x0c: - case 0x0d: - case 0x0e: - case 0x0f: - return(dev->mchash[off - 8]); + case 0x08: /* MAR0-7 */ + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + return (dev->mchash[off - 8]); - default: - dp8390_log("DP8390: Page1 read register 0x%02x out of range\n", - off); - return(0); + default: + dp8390_log("DP8390: Page1 read register 0x%02x out of range\n", + off); + return (0); } } - void dp8390_page1_write(dp8390_t *dev, uint32_t off, uint32_t val, unsigned len) { dp8390_log("DP8390: Page1 write to register 0x%02x, len=%u, value=0x%04x\n", - off, len, val); + off, len, val); - switch(off) { - case 0x01: /* PAR0-5 */ - case 0x02: - case 0x03: - case 0x04: - case 0x05: - case 0x06: - dev->physaddr[off - 1] = val; - if (off == 6) - dp8390_log("DP8390: Physical address set to %02x:%02x:%02x:%02x:%02x:%02x\n", - dev->physaddr[0], dev->physaddr[1], - dev->physaddr[2], dev->physaddr[3], - dev->physaddr[4], dev->physaddr[5]); - break; + switch (off) { + case 0x01: /* PAR0-5 */ + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + dev->physaddr[off - 1] = val; + if (off == 6) + dp8390_log("DP8390: Physical address set to %02x:%02x:%02x:%02x:%02x:%02x\n", + dev->physaddr[0], dev->physaddr[1], + dev->physaddr[2], dev->physaddr[3], + dev->physaddr[4], dev->physaddr[5]); + break; - case 0x07: /* CURR */ - dev->curr_page = val; - break; + case 0x07: /* CURR */ + dev->curr_page = val; + break; - case 0x08: /* MAR0-7 */ - case 0x09: - case 0x0a: - case 0x0b: - case 0x0c: - case 0x0d: - case 0x0e: - case 0x0f: - dev->mchash[off - 8] = val; - break; + case 0x08: /* MAR0-7 */ + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + dev->mchash[off - 8] = val; + break; - default: - dp8390_log("DP8390: Page1 write register 0x%02x out of range\n", - off); - break; + default: + dp8390_log("DP8390: Page1 write register 0x%02x out of range\n", + off); + break; } } - /* Handle reads/writes to the second page of the DS8390 register file. */ uint32_t dp8390_page2_read(dp8390_t *dev, uint32_t off, unsigned int len) { dp8390_log("DP8390: Page2 read from register 0x%02x, len=%u\n", - off, len); + off, len); - switch(off) { - case 0x01: /* PSTART */ - return(dev->page_start); + switch (off) { + case 0x01: /* PSTART */ + return (dev->page_start); - case 0x02: /* PSTOP */ - return(dev->page_stop); + case 0x02: /* PSTOP */ + return (dev->page_stop); - case 0x03: /* Remote Next-packet pointer */ - return(dev->rempkt_ptr); + case 0x03: /* Remote Next-packet pointer */ + return (dev->rempkt_ptr); - case 0x04: /* TPSR */ - return(dev->tx_page_start); + case 0x04: /* TPSR */ + return (dev->tx_page_start); - case 0x05: /* Local Next-packet pointer */ - return(dev->localpkt_ptr); + case 0x05: /* Local Next-packet pointer */ + return (dev->localpkt_ptr); - case 0x06: /* Address counter (upper) */ - return(dev->address_cnt >> 8); + case 0x06: /* Address counter (upper) */ + return (dev->address_cnt >> 8); - case 0x07: /* Address counter (lower) */ - return(dev->address_cnt & 0xff); + case 0x07: /* Address counter (lower) */ + return (dev->address_cnt & 0xff); - case 0x08: /* Reserved */ - case 0x09: - case 0x0a: - case 0x0b: - dp8390_log("DP8390: reserved Page2 read - register 0x%02x\n", - off); - return(0xff); + case 0x08: /* Reserved */ + case 0x09: + case 0x0a: + case 0x0b: + dp8390_log("DP8390: reserved Page2 read - register 0x%02x\n", + off); + return (0xff); - case 0x0c: /* RCR */ - return ((dev->RCR.monitor << 5) | - (dev->RCR.promisc << 4) | - (dev->RCR.multicast << 3) | - (dev->RCR.broadcast << 2) | - (dev->RCR.runts_ok << 1) | - (dev->RCR.errors_ok)); + case 0x0c: /* RCR */ + return ((dev->RCR.monitor << 5) | (dev->RCR.promisc << 4) | (dev->RCR.multicast << 3) | (dev->RCR.broadcast << 2) | (dev->RCR.runts_ok << 1) | (dev->RCR.errors_ok)); - case 0x0d: /* TCR */ - return ((dev->TCR.coll_prio << 4) | - (dev->TCR.ext_stoptx << 3) | - ((dev->TCR.loop_cntl & 0x3) << 1) | - (dev->TCR.crc_disable)); + case 0x0d: /* TCR */ + return ((dev->TCR.coll_prio << 4) | (dev->TCR.ext_stoptx << 3) | ((dev->TCR.loop_cntl & 0x3) << 1) | (dev->TCR.crc_disable)); - case 0x0e: /* DCR */ - return (((dev->DCR.fifo_size & 0x3) << 5) | - (dev->DCR.auto_rx << 4) | - (dev->DCR.loop << 3) | - (dev->DCR.longaddr << 2) | - (dev->DCR.endian << 1) | - (dev->DCR.wdsize)); + case 0x0e: /* DCR */ + return (((dev->DCR.fifo_size & 0x3) << 5) | (dev->DCR.auto_rx << 4) | (dev->DCR.loop << 3) | (dev->DCR.longaddr << 2) | (dev->DCR.endian << 1) | (dev->DCR.wdsize)); - case 0x0f: /* IMR */ - return ((dev->IMR.rdma_inte << 6) | - (dev->IMR.cofl_inte << 5) | - (dev->IMR.overw_inte << 4) | - (dev->IMR.txerr_inte << 3) | - (dev->IMR.rxerr_inte << 2) | - (dev->IMR.tx_inte << 1) | - (dev->IMR.rx_inte)); + case 0x0f: /* IMR */ + return ((dev->IMR.rdma_inte << 6) | (dev->IMR.cofl_inte << 5) | (dev->IMR.overw_inte << 4) | (dev->IMR.txerr_inte << 3) | (dev->IMR.rxerr_inte << 2) | (dev->IMR.tx_inte << 1) | (dev->IMR.rx_inte)); - default: - dp8390_log("DP8390: Page2 register 0x%02x out of range\n", - off); - break; + default: + dp8390_log("DP8390: Page2 register 0x%02x out of range\n", + off); + break; } - return(0); + return (0); } - void dp8390_page2_write(dp8390_t *dev, uint32_t off, uint32_t val, unsigned len) { -/* Maybe all writes here should be BX_PANIC()'d, since they - affect internal operation, but let them through for now - and print a warning. */ + /* Maybe all writes here should be BX_PANIC()'d, since they + affect internal operation, but let them through for now + and print a warning. */ dp8390_log("DP8390: Page2 write to register 0x%02x, len=%u, value=0x%04x\n", - off, len, val); + off, len, val); - switch(off) { - case 0x01: /* CLDA0 */ - /* Clear out low byte and re-insert */ - dev->local_dma &= 0xff00; - dev->local_dma |= (val & 0xff); - break; + switch (off) { + case 0x01: /* CLDA0 */ + /* Clear out low byte and re-insert */ + dev->local_dma &= 0xff00; + dev->local_dma |= (val & 0xff); + break; - case 0x02: /* CLDA1 */ - /* Clear out high byte and re-insert */ - dev->local_dma &= 0x00ff; - dev->local_dma |= ((val & 0xff) << 8); - break; + case 0x02: /* CLDA1 */ + /* Clear out high byte and re-insert */ + dev->local_dma &= 0x00ff; + dev->local_dma |= ((val & 0xff) << 8); + break; - case 0x03: /* Remote Next-pkt pointer */ - dev->rempkt_ptr = val; - break; + case 0x03: /* Remote Next-pkt pointer */ + dev->rempkt_ptr = val; + break; - case 0x04: + case 0x04: #ifdef ENABLE_DP8390_LOG - dp8390_log("DP8390: Page 2 write to reserved register 0x04\n"); + dp8390_log("DP8390: Page 2 write to reserved register 0x04\n"); #endif - break; + break; - case 0x05: /* Local Next-packet pointer */ - dev->localpkt_ptr = val; - break; + case 0x05: /* Local Next-packet pointer */ + dev->localpkt_ptr = val; + break; - case 0x06: /* Address counter (upper) */ - /* Clear out high byte and re-insert */ - dev->address_cnt &= 0x00ff; - dev->address_cnt |= ((val & 0xff) << 8); - break; + case 0x06: /* Address counter (upper) */ + /* Clear out high byte and re-insert */ + dev->address_cnt &= 0x00ff; + dev->address_cnt |= ((val & 0xff) << 8); + break; - case 0x07: /* Address counter (lower) */ - /* Clear out low byte and re-insert */ - dev->address_cnt &= 0xff00; - dev->address_cnt |= (val & 0xff); - break; + case 0x07: /* Address counter (lower) */ + /* Clear out low byte and re-insert */ + dev->address_cnt &= 0xff00; + dev->address_cnt |= (val & 0xff); + break; - case 0x08: - case 0x09: - case 0x0a: - case 0x0b: - case 0x0c: - case 0x0d: - case 0x0e: - case 0x0f: - dp8390_log("DP8390: Page2 write to reserved register 0x%02x\n", - off); - break; + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + dp8390_log("DP8390: Page2 write to reserved register 0x%02x\n", + off); + break; - default: - dp8390_log("DP8390: Page2 write, illegal register 0x%02x\n", - off); - break; + default: + dp8390_log("DP8390: Page2 write, illegal register 0x%02x\n", + off); + break; } } - void dp8390_set_defaults(dp8390_t *dev, uint8_t flags) { @@ -990,19 +910,17 @@ dp8390_set_defaults(dp8390_t *dev, uint8_t flags) dev->flags = flags; } - void dp8390_mem_alloc(dp8390_t *dev, uint32_t start, uint32_t size) { dev->mem = (uint8_t *) malloc(size * sizeof(uint8_t)); memset(dev->mem, 0, size * sizeof(uint8_t)); dev->mem_start = start; - dev->mem_end = start + size; - dev->mem_size = size; + dev->mem_end = start + size; + dev->mem_size = size; dp8390_log("DP8390: Mapped %i bytes of memory at address %04X in the address space\n", size, start); } - void dp8390_set_id(dp8390_t *dev, uint8_t id0, uint8_t id1) { @@ -1010,27 +928,26 @@ dp8390_set_id(dp8390_t *dev, uint8_t id0, uint8_t id1) dev->id1 = id1; } - void dp8390_reset(dp8390_t *dev) { int i, max, shift = 0; if (dev->flags & DP8390_FLAG_EVEN_MAC) - shift = 1; + shift = 1; max = 16 << shift; /* Initialize the MAC address area by doubling the physical address */ for (i = 0; i < max; i++) { - if (i < (6 << shift)) - dev->macaddr[i] = dev->physaddr[i >> shift]; - else /* Signature */ - dev->macaddr[i] = 0x57; + if (i < (6 << shift)) + dev->macaddr[i] = dev->physaddr[i >> shift]; + else /* Signature */ + dev->macaddr[i] = 0x57; } /* Zero out registers and memory */ - memset(&dev->CR, 0x00, sizeof(dev->CR) ); + memset(&dev->CR, 0x00, sizeof(dev->CR)); memset(&dev->ISR, 0x00, sizeof(dev->ISR)); memset(&dev->IMR, 0x00, sizeof(dev->IMR)); memset(&dev->DCR, 0x00, sizeof(dev->DCR)); @@ -1038,16 +955,16 @@ dp8390_reset(dp8390_t *dev) memset(&dev->TSR, 0x00, sizeof(dev->TSR)); memset(&dev->RSR, 0x00, sizeof(dev->RSR)); dev->tx_timer_active = 0; - dev->local_dma = 0; - dev->page_start = 0; - dev->page_stop = 0; - dev->bound_ptr = 0; - dev->tx_page_start = 0; - dev->num_coll = 0; - dev->tx_bytes = 0; - dev->fifo = 0; - dev->remote_dma = 0; - dev->remote_start = 0; + dev->local_dma = 0; + dev->page_start = 0; + dev->page_stop = 0; + dev->bound_ptr = 0; + dev->tx_page_start = 0; + dev->num_coll = 0; + dev->tx_bytes = 0; + dev->fifo = 0; + dev->remote_dma = 0; + dev->remote_start = 0; dev->remote_bytes = 0; @@ -1070,10 +987,9 @@ dp8390_reset(dp8390_t *dev) dev->DCR.longaddr = 1; if (dev->interrupt) - dev->interrupt(dev->priv, 0); + dev->interrupt(dev->priv, 0); } - void dp8390_soft_reset(dp8390_t *dev) { @@ -1081,7 +997,6 @@ dp8390_soft_reset(dp8390_t *dev) dev->ISR.reset = 1; } - static void * dp8390_init(const device_t *info) { @@ -1100,34 +1015,33 @@ dp8390_init(const device_t *info) return dp8390; } - static void dp8390_close(void *priv) { dp8390_t *dp8390 = (dp8390_t *) priv; if (dp8390) { - if (dp8390->mem) - free(dp8390->mem); + if (dp8390->mem) + free(dp8390->mem); - if (dp8390->card) { - netcard_close(dp8390->card); - } + if (dp8390->card) { + netcard_close(dp8390->card); + } - free(dp8390); + free(dp8390); } } const device_t dp8390_device = { - .name = "DP8390 Network Interface Controller", + .name = "DP8390 Network Interface Controller", .internal_name = "dp8390", - .flags = 0, - .local = 0, - .init = dp8390_init, - .close = dp8390_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = dp8390_init, + .close = dp8390_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/network/net_event.c b/src/network/net_event.c index c0e915c8b..6e68f1fe3 100644 --- a/src/network/net_event.c +++ b/src/network/net_event.c @@ -1,19 +1,19 @@ #ifdef _WIN32 -#define WIN32_LEAN_AND_MEAN -#include +# define WIN32_LEAN_AND_MEAN +# include #else -#include -#include +# include +# include #endif #include <86box/net_event.h> - #ifndef _WIN32 -static void setup_fd(int fd) +static void +setup_fd(int fd) { - fcntl(fd, F_SETFD, FD_CLOEXEC); - fcntl(fd, F_SETFL, O_NONBLOCK); + fcntl(fd, F_SETFD, FD_CLOEXEC); + fcntl(fd, F_SETFL, O_NONBLOCK); } #endif diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index c7f1a0ccb..501c52f3c 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -69,63 +69,59 @@ #include <86box/bswap.h> #include <86box/isapnp.h> - /* ROM BIOS file paths. */ -#define ROM_PATH_NE1000 "roms/network/ne1000/ne1000.rom" -#define ROM_PATH_NE2000 "roms/network/ne2000/ne2000.rom" -#define ROM_PATH_RTL8019 "roms/network/rtl8019as/rtl8019as.rom" -#define ROM_PATH_RTL8029 "roms/network/rtl8029as/rtl8029as.rom" +#define ROM_PATH_NE1000 "roms/network/ne1000/ne1000.rom" +#define ROM_PATH_NE2000 "roms/network/ne2000/ne2000.rom" +#define ROM_PATH_RTL8019 "roms/network/rtl8019as/rtl8019as.rom" +#define ROM_PATH_RTL8029 "roms/network/rtl8029as/rtl8029as.rom" /* PCI info. */ -#define PCI_VENDID 0x10ec /* Realtek, Inc */ -#define PCI_DEVID 0x8029 /* RTL8029AS */ -#define PCI_REGSIZE 256 /* size of PCI space */ - +#define PCI_VENDID 0x10ec /* Realtek, Inc */ +#define PCI_DEVID 0x8029 /* RTL8029AS */ +#define PCI_REGSIZE 256 /* size of PCI space */ static uint8_t rtl8019as_pnp_rom[] = { - 0x4a, 0x8c, 0x80, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, /* RTL8019, dummy checksum (filled in by isapnp_add_card) */ - 0x0a, 0x10, 0x10, /* PnP version 1.0, vendor version 1.0 */ + 0x4a, 0x8c, 0x80, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, /* RTL8019, dummy checksum (filled in by isapnp_add_card) */ + 0x0a, 0x10, 0x10, /* PnP version 1.0, vendor version 1.0 */ 0x82, 0x22, 0x00, 'R', 'E', 'A', 'L', 'T', 'E', 'K', ' ', 'P', 'L', 'U', 'G', ' ', '&', ' ', 'P', 'L', 'A', 'Y', ' ', 'E', 'T', 'H', 'E', 'R', 'N', 'E', 'T', ' ', 'C', 'A', 'R', 'D', 0x00, /* ANSI identifier */ - 0x16, 0x4a, 0x8c, 0x80, 0x19, 0x02, 0x00, /* logical device RTL8019 */ - 0x1c, 0x41, 0xd0, 0x80, 0xd6, /* compatible device PNP80D6 */ - 0x47, 0x00, 0x20, 0x02, 0x80, 0x03, 0x20, 0x20, /* I/O 0x220-0x380, decodes 10-bit, 32-byte alignment, 32 addresses */ - 0x23, 0x38, 0x9e, 0x01, /* IRQ 3/4/5/9/10/11/12/15, high true edge sensitive */ + 0x16, 0x4a, 0x8c, 0x80, 0x19, 0x02, 0x00, /* logical device RTL8019 */ + 0x1c, 0x41, 0xd0, 0x80, 0xd6, /* compatible device PNP80D6 */ + 0x47, 0x00, 0x20, 0x02, 0x80, 0x03, 0x20, 0x20, /* I/O 0x220-0x380, decodes 10-bit, 32-byte alignment, 32 addresses */ + 0x23, 0x38, 0x9e, 0x01, /* IRQ 3/4/5/9/10/11/12/15, high true edge sensitive */ 0x79, 0x00 /* end tag, dummy checksum (filled in by isapnp_add_card) */ }; - typedef struct { - dp8390_t *dp8390; - const char *name; - int board; - int is_pci, is_mca, is_8bit; - uint32_t base_address; - int base_irq; - uint32_t bios_addr, - bios_size, - bios_mask; - int card; /* PCI card slot */ - int has_bios, pad; - bar_t pci_bar[2]; - uint8_t pci_regs[PCI_REGSIZE]; - uint8_t eeprom[128]; /* for RTL8029AS */ - rom_t bios_rom; - void *pnp_card; - uint8_t pnp_csnsav; - uint8_t maclocal[6]; /* configured MAC (local) address */ + dp8390_t *dp8390; + const char *name; + int board; + int is_pci, is_mca, is_8bit; + uint32_t base_address; + int base_irq; + uint32_t bios_addr, + bios_size, + bios_mask; + int card; /* PCI card slot */ + int has_bios, pad; + bar_t pci_bar[2]; + uint8_t pci_regs[PCI_REGSIZE]; + uint8_t eeprom[128]; /* for RTL8029AS */ + rom_t bios_rom; + void *pnp_card; + uint8_t pnp_csnsav; + uint8_t maclocal[6]; /* configured MAC (local) address */ /* RTL8019AS/RTL8029AS registers */ - uint8_t config0, config2, config3; - uint8_t _9346cr; - uint32_t pad0; + uint8_t config0, config2, config3; + uint8_t _9346cr; + uint32_t pad0; /* POS registers, MCA boards only */ uint8_t pos_regs[8]; } nic_t; - #ifdef ENABLE_NE2K_LOG int ne2k_do_log = ENABLE_NE2K_LOG; @@ -135,56 +131,52 @@ nelog(int lvl, const char *fmt, ...) va_list ap; if (ne2k_do_log >= lvl) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define nelog(lvl, fmt, ...) +# define nelog(lvl, fmt, ...) #endif - static void nic_interrupt(void *priv, int set) { nic_t *dev = (nic_t *) priv; if (dev->is_pci) { - if (set) - pci_set_irq(dev->card, PCI_INTA); - else - pci_clear_irq(dev->card, PCI_INTA); + if (set) + pci_set_irq(dev->card, PCI_INTA); + else + pci_clear_irq(dev->card, PCI_INTA); } else { - if (set) - picint(1<base_irq); - else - picintc(1<base_irq); - } + if (set) + picint(1 << dev->base_irq); + else + picintc(1 << dev->base_irq); + } } - /* reset - restore state to power-up, cancelling all i/o */ static void nic_reset(void *priv) { - nic_t *dev = (nic_t *)priv; + nic_t *dev = (nic_t *) priv; nelog(1, "%s: reset\n", dev->name); dp8390_reset(dev->dp8390); } - static void nic_soft_reset(void *priv) { - nic_t *dev = (nic_t *)priv; + nic_t *dev = (nic_t *) priv; dp8390_soft_reset(dev->dp8390); } - /* * Access the ASIC I/O space. * @@ -203,246 +195,241 @@ asic_read(nic_t *dev, uint32_t off, unsigned int len) { uint32_t retval = 0; - switch(off) { - case 0x00: /* Data register */ - /* A read remote-DMA command must have been issued, - and the source-address and length registers must - have been initialised. */ - if (len > dev->dp8390->remote_bytes) { - nelog(3, "%s: DMA read underrun iolen=%d remote_bytes=%d\n", - dev->name, len, dev->dp8390->remote_bytes); - } + switch (off) { + case 0x00: /* Data register */ + /* A read remote-DMA command must have been issued, + and the source-address and length registers must + have been initialised. */ + if (len > dev->dp8390->remote_bytes) { + nelog(3, "%s: DMA read underrun iolen=%d remote_bytes=%d\n", + dev->name, len, dev->dp8390->remote_bytes); + } - nelog(3, "%s: DMA read: addr=%4x remote_bytes=%d\n", - dev->name, dev->dp8390->remote_dma,dev->dp8390->remote_bytes); - retval = dp8390_chipmem_read(dev->dp8390, dev->dp8390->remote_dma, len); + nelog(3, "%s: DMA read: addr=%4x remote_bytes=%d\n", + dev->name, dev->dp8390->remote_dma, dev->dp8390->remote_bytes); + retval = dp8390_chipmem_read(dev->dp8390, dev->dp8390->remote_dma, len); - /* The 8390 bumps the address and decreases the byte count - by the selected word size after every access, not by - the amount of data requested by the host (io_len). */ - if (len == 4) { - dev->dp8390->remote_dma += len; - } else { - dev->dp8390->remote_dma += (dev->dp8390->DCR.wdsize + 1); - } + /* The 8390 bumps the address and decreases the byte count + by the selected word size after every access, not by + the amount of data requested by the host (io_len). */ + if (len == 4) { + dev->dp8390->remote_dma += len; + } else { + dev->dp8390->remote_dma += (dev->dp8390->DCR.wdsize + 1); + } - if (dev->dp8390->remote_dma == dev->dp8390->page_stop << 8) { - dev->dp8390->remote_dma = dev->dp8390->page_start << 8; - } + if (dev->dp8390->remote_dma == dev->dp8390->page_stop << 8) { + dev->dp8390->remote_dma = dev->dp8390->page_start << 8; + } - /* keep s.remote_bytes from underflowing */ - if (dev->dp8390->remote_bytes > dev->dp8390->DCR.wdsize) { - if (len == 4) { - dev->dp8390->remote_bytes -= len; - } else { - dev->dp8390->remote_bytes -= (dev->dp8390->DCR.wdsize + 1); - } - } else { - dev->dp8390->remote_bytes = 0; - } + /* keep s.remote_bytes from underflowing */ + if (dev->dp8390->remote_bytes > dev->dp8390->DCR.wdsize) { + if (len == 4) { + dev->dp8390->remote_bytes -= len; + } else { + dev->dp8390->remote_bytes -= (dev->dp8390->DCR.wdsize + 1); + } + } else { + dev->dp8390->remote_bytes = 0; + } - /* If all bytes have been written, signal remote-DMA complete */ - if (dev->dp8390->remote_bytes == 0) { - dev->dp8390->ISR.rdma_done = 1; - if (dev->dp8390->IMR.rdma_inte) - nic_interrupt(dev, 1); - } - break; + /* If all bytes have been written, signal remote-DMA complete */ + if (dev->dp8390->remote_bytes == 0) { + dev->dp8390->ISR.rdma_done = 1; + if (dev->dp8390->IMR.rdma_inte) + nic_interrupt(dev, 1); + } + break; - case 0x0f: /* Reset register */ - nic_soft_reset(dev); - break; + case 0x0f: /* Reset register */ + nic_soft_reset(dev); + break; - default: - nelog(3, "%s: ASIC read invalid address %04x\n", - dev->name, (unsigned)off); - break; + default: + nelog(3, "%s: ASIC read invalid address %04x\n", + dev->name, (unsigned) off); + break; } - return(retval); + return (retval); } static void asic_write(nic_t *dev, uint32_t off, uint32_t val, unsigned len) { nelog(3, "%s: ASIC write addr=0x%02x, value=0x%04x\n", - dev->name, (unsigned)off, (unsigned) val); + dev->name, (unsigned) off, (unsigned) val); - switch(off) { - case 0x00: /* Data register - see asic_read for a description */ - if ((len > 1) && (dev->dp8390->DCR.wdsize == 0)) { - nelog(3, "%s: DMA write length %d on byte mode operation\n", - dev->name, len); - break; - } - if (dev->dp8390->remote_bytes == 0) - nelog(3, "%s: DMA write, byte count 0\n", dev->name); + switch (off) { + case 0x00: /* Data register - see asic_read for a description */ + if ((len > 1) && (dev->dp8390->DCR.wdsize == 0)) { + nelog(3, "%s: DMA write length %d on byte mode operation\n", + dev->name, len); + break; + } + if (dev->dp8390->remote_bytes == 0) + nelog(3, "%s: DMA write, byte count 0\n", dev->name); - dp8390_chipmem_write(dev->dp8390, dev->dp8390->remote_dma, val, len); - if (len == 4) - dev->dp8390->remote_dma += len; - else - dev->dp8390->remote_dma += (dev->dp8390->DCR.wdsize + 1); + dp8390_chipmem_write(dev->dp8390, dev->dp8390->remote_dma, val, len); + if (len == 4) + dev->dp8390->remote_dma += len; + else + dev->dp8390->remote_dma += (dev->dp8390->DCR.wdsize + 1); - if (dev->dp8390->remote_dma == dev->dp8390->page_stop << 8) - dev->dp8390->remote_dma = dev->dp8390->page_start << 8; + if (dev->dp8390->remote_dma == dev->dp8390->page_stop << 8) + dev->dp8390->remote_dma = dev->dp8390->page_start << 8; - if (len == 4) - dev->dp8390->remote_bytes -= len; - else - dev->dp8390->remote_bytes -= (dev->dp8390->DCR.wdsize + 1); + if (len == 4) + dev->dp8390->remote_bytes -= len; + else + dev->dp8390->remote_bytes -= (dev->dp8390->DCR.wdsize + 1); - if (dev->dp8390->remote_bytes > dev->dp8390->mem_size) - dev->dp8390->remote_bytes = 0; + if (dev->dp8390->remote_bytes > dev->dp8390->mem_size) + dev->dp8390->remote_bytes = 0; - /* If all bytes have been written, signal remote-DMA complete */ - if (dev->dp8390->remote_bytes == 0) { - dev->dp8390->ISR.rdma_done = 1; - if (dev->dp8390->IMR.rdma_inte) - nic_interrupt(dev, 1); - } - break; + /* If all bytes have been written, signal remote-DMA complete */ + if (dev->dp8390->remote_bytes == 0) { + dev->dp8390->ISR.rdma_done = 1; + if (dev->dp8390->IMR.rdma_inte) + nic_interrupt(dev, 1); + } + break; - case 0x0f: /* Reset register */ - /* end of reset pulse */ - break; + case 0x0f: /* Reset register */ + /* end of reset pulse */ + break; - default: /* this is invalid, but happens under win95 device detection */ - nelog(3, "%s: ASIC write invalid address %04x, ignoring\n", - dev->name, (unsigned)off); - break; + default: /* this is invalid, but happens under win95 device detection */ + nelog(3, "%s: ASIC write invalid address %04x, ignoring\n", + dev->name, (unsigned) off); + break; } } - /* Writes to this page are illegal. */ static uint32_t page3_read(nic_t *dev, uint32_t off, unsigned int len) { - if (dev->board >= NE2K_RTL8019AS) switch(off) { - case 0x1: /* 9346CR */ - return(dev->_9346cr); + if (dev->board >= NE2K_RTL8019AS) + switch (off) { + case 0x1: /* 9346CR */ + return (dev->_9346cr); - case 0x3: /* CONFIG0 */ - return(0x00); /* Cable not BNC */ + case 0x3: /* CONFIG0 */ + return (0x00); /* Cable not BNC */ - case 0x5: /* CONFIG2 */ - return(dev->config2 & 0xe0); + case 0x5: /* CONFIG2 */ + return (dev->config2 & 0xe0); - case 0x6: /* CONFIG3 */ - return(dev->config3 & 0x46); + case 0x6: /* CONFIG3 */ + return (dev->config3 & 0x46); - case 0x8: /* CSNSAV */ - return((dev->board == NE2K_RTL8019AS) ? dev->pnp_csnsav : 0x00); + case 0x8: /* CSNSAV */ + return ((dev->board == NE2K_RTL8019AS) ? dev->pnp_csnsav : 0x00); - case 0xe: /* 8029ASID0 */ - if (dev->board == NE2K_RTL8029AS) - return(0x29); - break; + case 0xe: /* 8029ASID0 */ + if (dev->board == NE2K_RTL8029AS) + return (0x29); + break; - case 0xf: /* 8029ASID1 */ - if (dev->board == NE2K_RTL8029AS) - return(0x80); - break; + case 0xf: /* 8029ASID1 */ + if (dev->board == NE2K_RTL8029AS) + return (0x80); + break; - default: - break; - } + default: + break; + } nelog(3, "%s: Page3 read register 0x%02x attempted\n", dev->name, off); - return(0x00); + return (0x00); } - static void page3_write(nic_t *dev, uint32_t off, uint32_t val, unsigned len) { if (dev->board >= NE2K_RTL8019AS) { - nelog(3, "%s: Page2 write to register 0x%02x, len=%u, value=0x%04x\n", - dev->name, off, len, val); + nelog(3, "%s: Page2 write to register 0x%02x, len=%u, value=0x%04x\n", + dev->name, off, len, val); - switch(off) { - case 0x01: /* 9346CR */ - dev->_9346cr = (val & 0xfe); - break; + switch (off) { + case 0x01: /* 9346CR */ + dev->_9346cr = (val & 0xfe); + break; - case 0x05: /* CONFIG2 */ - dev->config2 = (val & 0xe0); - break; + case 0x05: /* CONFIG2 */ + dev->config2 = (val & 0xe0); + break; - case 0x06: /* CONFIG3 */ - dev->config3 = (val & 0x46); - break; + case 0x06: /* CONFIG3 */ + dev->config3 = (val & 0x46); + break; - case 0x09: /* HLTCLK */ - break; + case 0x09: /* HLTCLK */ + break; - default: - nelog(3, "%s: Page3 write to reserved register 0x%02x\n", - dev->name, off); - break; - } + default: + nelog(3, "%s: Page3 write to reserved register 0x%02x\n", + dev->name, off); + break; + } } else - nelog(3, "%s: Page3 write register 0x%02x attempted\n", dev->name, off); + nelog(3, "%s: Page3 write register 0x%02x attempted\n", dev->name, off); } - static uint32_t nic_read(nic_t *dev, uint32_t addr, unsigned len) { uint32_t retval = 0; - int off = addr - dev->base_address; + int off = addr - dev->base_address; nelog(3, "%s: read addr %x, len %d\n", dev->name, addr, len); if (off >= 0x10) - retval = asic_read(dev, off - 0x10, len); + retval = asic_read(dev, off - 0x10, len); else if (off == 0x00) - retval = dp8390_read_cr(dev->dp8390); - else switch(dev->dp8390->CR.pgsel) { - case 0x00: - retval = dp8390_page0_read(dev->dp8390, off, len); - break; - case 0x01: - retval = dp8390_page1_read(dev->dp8390, off, len); - break; - case 0x02: - retval = dp8390_page2_read(dev->dp8390, off, len); - break; - case 0x03: - retval = page3_read(dev, off, len); - break; - default: - nelog(3, "%s: unknown value of pgsel in read - %d\n", - dev->name, dev->dp8390->CR.pgsel); - break; - } + retval = dp8390_read_cr(dev->dp8390); + else + switch (dev->dp8390->CR.pgsel) { + case 0x00: + retval = dp8390_page0_read(dev->dp8390, off, len); + break; + case 0x01: + retval = dp8390_page1_read(dev->dp8390, off, len); + break; + case 0x02: + retval = dp8390_page2_read(dev->dp8390, off, len); + break; + case 0x03: + retval = page3_read(dev, off, len); + break; + default: + nelog(3, "%s: unknown value of pgsel in read - %d\n", + dev->name, dev->dp8390->CR.pgsel); + break; + } - return(retval); + return (retval); } - static uint8_t nic_readb(uint16_t addr, void *priv) { - return(nic_read((nic_t *)priv, addr, 1)); + return (nic_read((nic_t *) priv, addr, 1)); } - static uint16_t nic_readw(uint16_t addr, void *priv) { - return(nic_read((nic_t *)priv, addr, 2)); + return (nic_read((nic_t *) priv, addr, 2)); } - static uint32_t nic_readl(uint16_t addr, void *priv) { - return(nic_read((nic_t *)priv, addr, 4)); + return (nic_read((nic_t *) priv, addr, 4)); } - static void nic_write(nic_t *dev, uint32_t addr, uint32_t val, unsigned len) { @@ -455,76 +442,71 @@ nic_write(nic_t *dev, uint32_t addr, uint32_t val, unsigned len) page being selected by the PS0,PS1 registers in the command register */ if (off >= 0x10) - asic_write(dev, off - 0x10, val, len); + asic_write(dev, off - 0x10, val, len); else if (off == 0x00) - dp8390_write_cr(dev->dp8390, val); - else switch(dev->dp8390->CR.pgsel) { - case 0x00: - dp8390_page0_write(dev->dp8390, off, val, len); - break; - case 0x01: - dp8390_page1_write(dev->dp8390, off, val, len); - break; - case 0x02: - dp8390_page2_write(dev->dp8390, off, val, len); - break; - case 0x03: - page3_write(dev, off, val, len); - break; - default: - nelog(3, "%s: unknown value of pgsel in write - %d\n", - dev->name, dev->dp8390->CR.pgsel); - break; - } + dp8390_write_cr(dev->dp8390, val); + else + switch (dev->dp8390->CR.pgsel) { + case 0x00: + dp8390_page0_write(dev->dp8390, off, val, len); + break; + case 0x01: + dp8390_page1_write(dev->dp8390, off, val, len); + break; + case 0x02: + dp8390_page2_write(dev->dp8390, off, val, len); + break; + case 0x03: + page3_write(dev, off, val, len); + break; + default: + nelog(3, "%s: unknown value of pgsel in write - %d\n", + dev->name, dev->dp8390->CR.pgsel); + break; + } } - static void nic_writeb(uint16_t addr, uint8_t val, void *priv) { - nic_write((nic_t *)priv, addr, val, 1); + nic_write((nic_t *) priv, addr, val, 1); } - static void nic_writew(uint16_t addr, uint16_t val, void *priv) { - nic_write((nic_t *)priv, addr, val, 2); + nic_write((nic_t *) priv, addr, val, 2); } - static void nic_writel(uint16_t addr, uint32_t val, void *priv) { - nic_write((nic_t *)priv, addr, val, 4); + nic_write((nic_t *) priv, addr, val, 4); } - -static void nic_ioset(nic_t *dev, uint16_t addr); -static void nic_ioremove(nic_t *dev, uint16_t addr); - +static void nic_ioset(nic_t *dev, uint16_t addr); +static void nic_ioremove(nic_t *dev, uint16_t addr); static void nic_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv) { if (ld) - return; + return; nic_t *dev = (nic_t *) priv; if (dev->base_address) { - nic_ioremove(dev, dev->base_address); - dev->base_address = 0; + nic_ioremove(dev, dev->base_address); + dev->base_address = 0; } dev->base_address = config->io[0].base; - dev->base_irq = config->irq[0].irq; + dev->base_irq = config->irq[0].irq; if (config->activate && (dev->base_address != ISAPNP_IO_DISABLED)) - nic_ioset(dev, dev->base_address); + nic_ioset(dev, dev->base_address); } - static void nic_pnp_csn_changed(uint8_t csn, void *priv) { @@ -533,94 +515,89 @@ nic_pnp_csn_changed(uint8_t csn, void *priv) dev->pnp_csnsav = csn; } - static uint8_t nic_pnp_read_vendor_reg(uint8_t ld, uint8_t reg, void *priv) { if (ld != 0) - return 0x00; + return 0x00; nic_t *dev = (nic_t *) priv; switch (reg) { - case 0xF0: - return dev->config0; + case 0xF0: + return dev->config0; - case 0xF2: - return dev->config2; + case 0xF2: + return dev->config2; - case 0xF3: - return dev->config3; + case 0xF3: + return dev->config3; - case 0xF5: - return dev->pnp_csnsav; + case 0xF5: + return dev->pnp_csnsav; } return 0x00; } - static void nic_pnp_write_vendor_reg(uint8_t ld, uint8_t reg, uint8_t val, void *priv) { nic_t *dev = (nic_t *) priv; if ((ld == 0) && (reg == 0xf6) && (val & 0x04)) { - uint8_t csn = dev->pnp_csnsav; - isapnp_set_csn(dev->pnp_card, 0); - dev->pnp_csnsav = csn; + uint8_t csn = dev->pnp_csnsav; + isapnp_set_csn(dev->pnp_card, 0); + dev->pnp_csnsav = csn; } } - static void nic_ioset(nic_t *dev, uint16_t addr) { if (dev->is_pci) { - io_sethandler(addr, 32, - nic_readb, nic_readw, nic_readl, - nic_writeb, nic_writew, nic_writel, dev); + io_sethandler(addr, 32, + nic_readb, nic_readw, nic_readl, + nic_writeb, nic_writew, nic_writel, dev); } else { - io_sethandler(addr, 16, - nic_readb, NULL, NULL, - nic_writeb, NULL, NULL, dev); - if (dev->is_8bit) { - io_sethandler(addr+16, 16, - nic_readb, NULL, NULL, - nic_writeb, NULL, NULL, dev); - } else { - io_sethandler(addr+16, 16, - nic_readb, nic_readw, NULL, - nic_writeb, nic_writew, NULL, dev); - } + io_sethandler(addr, 16, + nic_readb, NULL, NULL, + nic_writeb, NULL, NULL, dev); + if (dev->is_8bit) { + io_sethandler(addr + 16, 16, + nic_readb, NULL, NULL, + nic_writeb, NULL, NULL, dev); + } else { + io_sethandler(addr + 16, 16, + nic_readb, nic_readw, NULL, + nic_writeb, nic_writew, NULL, dev); + } } } - static void nic_ioremove(nic_t *dev, uint16_t addr) { if (dev->is_pci) { - io_removehandler(addr, 32, - nic_readb, nic_readw, nic_readl, - nic_writeb, nic_writew, nic_writel, dev); + io_removehandler(addr, 32, + nic_readb, nic_readw, nic_readl, + nic_writeb, nic_writew, nic_writel, dev); } else { - io_removehandler(addr, 16, - nic_readb, NULL, NULL, - nic_writeb, NULL, NULL, dev); - if (dev->is_8bit) { - io_removehandler(addr+16, 16, - nic_readb, NULL, NULL, - nic_writeb, NULL, NULL, dev); - } else { - io_removehandler(addr+16, 16, - nic_readb, nic_readw, NULL, - nic_writeb, nic_writew, NULL, dev); - } + io_removehandler(addr, 16, + nic_readb, NULL, NULL, + nic_writeb, NULL, NULL, dev); + if (dev->is_8bit) { + io_removehandler(addr + 16, 16, + nic_readb, NULL, NULL, + nic_writeb, NULL, NULL, dev); + } else { + io_removehandler(addr + 16, 16, + nic_readb, nic_readw, NULL, + nic_writeb, nic_writew, NULL, dev); + } } } - static void nic_update_bios(nic_t *dev) { @@ -628,247 +605,250 @@ nic_update_bios(nic_t *dev) reg_bios_enable = 1; - if (! dev->has_bios) return; + if (!dev->has_bios) + return; if (dev->is_pci) - reg_bios_enable = dev->pci_bar[1].addr_regs[0] & 0x01; + reg_bios_enable = dev->pci_bar[1].addr_regs[0] & 0x01; /* PCI BIOS stuff, just enable_disable. */ if (reg_bios_enable) { - mem_mapping_set_addr(&dev->bios_rom.mapping, - dev->bios_addr, dev->bios_size); - nelog(1, "%s: BIOS now at: %06X\n", dev->name, dev->bios_addr); + mem_mapping_set_addr(&dev->bios_rom.mapping, + dev->bios_addr, dev->bios_size); + nelog(1, "%s: BIOS now at: %06X\n", dev->name, dev->bios_addr); } else { - nelog(1, "%s: BIOS disabled\n", dev->name); - mem_mapping_disable(&dev->bios_rom.mapping); + nelog(1, "%s: BIOS disabled\n", dev->name); + mem_mapping_disable(&dev->bios_rom.mapping); } } - static uint8_t nic_pci_read(int func, int addr, void *priv) { - nic_t *dev = (nic_t *)priv; + nic_t *dev = (nic_t *) priv; uint8_t ret = 0x00; - switch(addr) { - case 0x00: /* PCI_VID_LO */ - case 0x01: /* PCI_VID_HI */ - ret = dev->pci_regs[addr]; - break; + switch (addr) { + case 0x00: /* PCI_VID_LO */ + case 0x01: /* PCI_VID_HI */ + ret = dev->pci_regs[addr]; + break; - case 0x02: /* PCI_DID_LO */ - case 0x03: /* PCI_DID_HI */ - ret = dev->pci_regs[addr]; - break; + case 0x02: /* PCI_DID_LO */ + case 0x03: /* PCI_DID_HI */ + ret = dev->pci_regs[addr]; + break; - case 0x04: /* PCI_COMMAND_LO */ - case 0x05: /* PCI_COMMAND_HI */ - ret = dev->pci_regs[addr]; - break; + case 0x04: /* PCI_COMMAND_LO */ + case 0x05: /* PCI_COMMAND_HI */ + ret = dev->pci_regs[addr]; + break; - case 0x06: /* PCI_STATUS_LO */ - case 0x07: /* PCI_STATUS_HI */ - ret = dev->pci_regs[addr]; - break; + case 0x06: /* PCI_STATUS_LO */ + case 0x07: /* PCI_STATUS_HI */ + ret = dev->pci_regs[addr]; + break; - case 0x08: /* PCI_REVID */ - ret = 0x00; /* Rev. 00 */ - break; - case 0x09: /* PCI_PIFR */ - ret = 0x00; /* Rev. 00 */ - break; + case 0x08: /* PCI_REVID */ + ret = 0x00; /* Rev. 00 */ + break; + case 0x09: /* PCI_PIFR */ + ret = 0x00; /* Rev. 00 */ + break; - case 0x0A: /* PCI_SCR */ - ret = dev->pci_regs[addr]; - break; + case 0x0A: /* PCI_SCR */ + ret = dev->pci_regs[addr]; + break; - case 0x0B: /* PCI_BCR */ - ret = dev->pci_regs[addr]; - break; + case 0x0B: /* PCI_BCR */ + ret = dev->pci_regs[addr]; + break; - case 0x10: /* PCI_BAR 7:5 */ - ret = (dev->pci_bar[0].addr_regs[0] & 0xe0) | 0x01; - break; - case 0x11: /* PCI_BAR 15:8 */ - ret = dev->pci_bar[0].addr_regs[1]; - break; - case 0x12: /* PCI_BAR 23:16 */ - ret = dev->pci_bar[0].addr_regs[2]; - break; - case 0x13: /* PCI_BAR 31:24 */ - ret = dev->pci_bar[0].addr_regs[3]; - break; + case 0x10: /* PCI_BAR 7:5 */ + ret = (dev->pci_bar[0].addr_regs[0] & 0xe0) | 0x01; + break; + case 0x11: /* PCI_BAR 15:8 */ + ret = dev->pci_bar[0].addr_regs[1]; + break; + case 0x12: /* PCI_BAR 23:16 */ + ret = dev->pci_bar[0].addr_regs[2]; + break; + case 0x13: /* PCI_BAR 31:24 */ + ret = dev->pci_bar[0].addr_regs[3]; + break; - case 0x2C: /* PCI_SVID_LO */ - case 0x2D: /* PCI_SVID_HI */ - ret = dev->pci_regs[addr]; - break; + case 0x2C: /* PCI_SVID_LO */ + case 0x2D: /* PCI_SVID_HI */ + ret = dev->pci_regs[addr]; + break; - case 0x2E: /* PCI_SID_LO */ - case 0x2F: /* PCI_SID_HI */ - ret = dev->pci_regs[addr]; - break; + case 0x2E: /* PCI_SID_LO */ + case 0x2F: /* PCI_SID_HI */ + ret = dev->pci_regs[addr]; + break; - case 0x30: /* PCI_ROMBAR */ - ret = dev->pci_bar[1].addr_regs[0] & 0x01; - break; - case 0x31: /* PCI_ROMBAR 15:11 */ - ret = dev->pci_bar[1].addr_regs[1] & 0x80; - break; - case 0x32: /* PCI_ROMBAR 23:16 */ - ret = dev->pci_bar[1].addr_regs[2]; - break; - case 0x33: /* PCI_ROMBAR 31:24 */ - ret = dev->pci_bar[1].addr_regs[3]; - break; + case 0x30: /* PCI_ROMBAR */ + ret = dev->pci_bar[1].addr_regs[0] & 0x01; + break; + case 0x31: /* PCI_ROMBAR 15:11 */ + ret = dev->pci_bar[1].addr_regs[1] & 0x80; + break; + case 0x32: /* PCI_ROMBAR 23:16 */ + ret = dev->pci_bar[1].addr_regs[2]; + break; + case 0x33: /* PCI_ROMBAR 31:24 */ + ret = dev->pci_bar[1].addr_regs[3]; + break; - case 0x3C: /* PCI_ILR */ - ret = dev->pci_regs[addr]; - break; + case 0x3C: /* PCI_ILR */ + ret = dev->pci_regs[addr]; + break; - case 0x3D: /* PCI_IPR */ - ret = dev->pci_regs[addr]; - break; + case 0x3D: /* PCI_IPR */ + ret = dev->pci_regs[addr]; + break; } nelog(2, "%s: PCI_Read(%d, %04x) = %02x\n", dev->name, func, addr, ret); - return(ret); + return (ret); } - static void nic_pci_write(int func, int addr, uint8_t val, void *priv) { - nic_t *dev = (nic_t *)priv; + nic_t *dev = (nic_t *) priv; uint8_t valxor; nelog(2, "%s: PCI_Write(%d, %04x, %02x)\n", dev->name, func, addr, val); - switch(addr) { - case 0x04: /* PCI_COMMAND_LO */ - valxor = (val & 0x03) ^ dev->pci_regs[addr]; - if (valxor & PCI_COMMAND_IO) - { - nic_ioremove(dev, dev->base_address); - if ((dev->base_address != 0) && (val & PCI_COMMAND_IO)) - { - nic_ioset(dev, dev->base_address); - } - } - dev->pci_regs[addr] = val & 0x03; - break; + switch (addr) { + case 0x04: /* PCI_COMMAND_LO */ + valxor = (val & 0x03) ^ dev->pci_regs[addr]; + if (valxor & PCI_COMMAND_IO) { + nic_ioremove(dev, dev->base_address); + if ((dev->base_address != 0) && (val & PCI_COMMAND_IO)) { + nic_ioset(dev, dev->base_address); + } + } + dev->pci_regs[addr] = val & 0x03; + break; - case 0x10: /* PCI_BAR */ - val &= 0xe0; /* 0xe0 acc to RTL DS */ - val |= 0x01; /* re-enable IOIN bit */ - /*FALLTHROUGH*/ + case 0x10: /* PCI_BAR */ + val &= 0xe0; /* 0xe0 acc to RTL DS */ + val |= 0x01; /* re-enable IOIN bit */ + /*FALLTHROUGH*/ - case 0x11: /* PCI_BAR */ - case 0x12: /* PCI_BAR */ - case 0x13: /* PCI_BAR */ - /* Remove old I/O. */ - nic_ioremove(dev, dev->base_address); + case 0x11: /* PCI_BAR */ + case 0x12: /* PCI_BAR */ + case 0x13: /* PCI_BAR */ + /* Remove old I/O. */ + nic_ioremove(dev, dev->base_address); - /* Set new I/O as per PCI request. */ - dev->pci_bar[0].addr_regs[addr & 3] = val; + /* Set new I/O as per PCI request. */ + dev->pci_bar[0].addr_regs[addr & 3] = val; - /* Then let's calculate the new I/O base. */ - dev->base_address = dev->pci_bar[0].addr & 0xffe0; + /* Then let's calculate the new I/O base. */ + dev->base_address = dev->pci_bar[0].addr & 0xffe0; - /* Log the new base. */ - nelog(1, "%s: PCI: new I/O base is %04X\n", - dev->name, dev->base_address); - /* We're done, so get out of the here. */ - if (dev->pci_regs[4] & PCI_COMMAND_IO) - { - if (dev->base_address != 0) - { - nic_ioset(dev, dev->base_address); - } - } - break; + /* Log the new base. */ + nelog(1, "%s: PCI: new I/O base is %04X\n", + dev->name, dev->base_address); + /* We're done, so get out of the here. */ + if (dev->pci_regs[4] & PCI_COMMAND_IO) { + if (dev->base_address != 0) { + nic_ioset(dev, dev->base_address); + } + } + break; - case 0x30: /* PCI_ROMBAR */ - case 0x31: /* PCI_ROMBAR */ - case 0x32: /* PCI_ROMBAR */ - case 0x33: /* PCI_ROMBAR */ - dev->pci_bar[1].addr_regs[addr & 3] = val; - /* dev->pci_bar[1].addr_regs[1] &= dev->bios_mask; */ - dev->pci_bar[1].addr &= 0xffff8001; - dev->bios_addr = dev->pci_bar[1].addr & 0xffff8000; - nic_update_bios(dev); - return; + case 0x30: /* PCI_ROMBAR */ + case 0x31: /* PCI_ROMBAR */ + case 0x32: /* PCI_ROMBAR */ + case 0x33: /* PCI_ROMBAR */ + dev->pci_bar[1].addr_regs[addr & 3] = val; + /* dev->pci_bar[1].addr_regs[1] &= dev->bios_mask; */ + dev->pci_bar[1].addr &= 0xffff8001; + dev->bios_addr = dev->pci_bar[1].addr & 0xffff8000; + nic_update_bios(dev); + return; - case 0x3C: /* PCI_ILR */ - nelog(1, "%s: IRQ now: %i\n", dev->name, val); - dev->base_irq = val; - dev->pci_regs[addr] = dev->base_irq; - return; + case 0x3C: /* PCI_ILR */ + nelog(1, "%s: IRQ now: %i\n", dev->name, val); + dev->base_irq = val; + dev->pci_regs[addr] = dev->base_irq; + return; } } - static void nic_rom_init(nic_t *dev, char *s) { uint32_t temp; - FILE *f; + FILE *f; - if (s == NULL) return; + if (s == NULL) + return; - if (dev->bios_addr == 0) return; + if (dev->bios_addr == 0) + return; if ((f = rom_fopen(s, "rb")) != NULL) { - fseek(f, 0L, SEEK_END); - temp = ftell(f); - fclose(f); - dev->bios_size = 0x10000; - if (temp <= 0x8000) - dev->bios_size = 0x8000; - if (temp <= 0x4000) - dev->bios_size = 0x4000; - if (temp <= 0x2000) - dev->bios_size = 0x2000; - dev->bios_mask = (dev->bios_size >> 8) & 0xff; - dev->bios_mask = (0x100 - dev->bios_mask) & 0xff; + fseek(f, 0L, SEEK_END); + temp = ftell(f); + fclose(f); + dev->bios_size = 0x10000; + if (temp <= 0x8000) + dev->bios_size = 0x8000; + if (temp <= 0x4000) + dev->bios_size = 0x4000; + if (temp <= 0x2000) + dev->bios_size = 0x2000; + dev->bios_mask = (dev->bios_size >> 8) & 0xff; + dev->bios_mask = (0x100 - dev->bios_mask) & 0xff; } else { - dev->bios_addr = 0x00000; - dev->bios_size = 0; - return; + dev->bios_addr = 0x00000; + dev->bios_size = 0; + return; } /* Create a memory mapping for the space. */ rom_init(&dev->bios_rom, s, dev->bios_addr, - dev->bios_size, dev->bios_size-1, 0, MEM_MAPPING_EXTERNAL); + dev->bios_size, dev->bios_size - 1, 0, MEM_MAPPING_EXTERNAL); nelog(1, "%s: BIOS configured at %06lX (size %ld)\n", - dev->name, dev->bios_addr, dev->bios_size); + dev->name, dev->bios_addr, dev->bios_size); } static uint8_t nic_mca_read(int port, void *priv) { - nic_t *dev = (nic_t *)priv; + nic_t *dev = (nic_t *) priv; - return(dev->pos_regs[port & 7]); + return (dev->pos_regs[port & 7]); } -#define MCA_611F_IO_PORTS { 0x300, 0x340, 0x320, 0x360, 0x1300, 0x1340, \ - 0x1320, 0x1360 } +#define MCA_611F_IO_PORTS \ + { \ + 0x300, 0x340, 0x320, 0x360, 0x1300, 0x1340, \ + 0x1320, 0x1360 \ + } -#define MCA_611F_IRQS { 2, 3, 4, 5, 10, 11, 12, 15 } +#define MCA_611F_IRQS \ + { \ + 2, 3, 4, 5, 10, 11, 12, 15 \ + } static void nic_mca_write(int port, uint8_t val, void *priv) { - nic_t *dev = (nic_t *)priv; + nic_t *dev = (nic_t *) priv; uint16_t base[] = MCA_611F_IO_PORTS; - int8_t irq[] = MCA_611F_IRQS; + int8_t irq[] = MCA_611F_IRQS; /* MCA does not write registers below 0x0100. */ - if (port < 0x0102) return; + if (port < 0x0102) + return; /* Save the MCA register value. */ dev->pos_regs[port & 7] = val; @@ -876,14 +856,14 @@ nic_mca_write(int port, uint8_t val, void *priv) nic_ioremove(dev, dev->base_address); /* This is always necessary so that the old handler doesn't remain. */ - /* Get the new assigned I/O base address. */ - dev->base_address = base[(dev->pos_regs[2] & 0xE0) >> 4]; + /* Get the new assigned I/O base address. */ + dev->base_address = base[(dev->pos_regs[2] & 0xE0) >> 4]; - /* Save the new IRQ values. */ - dev->base_irq = irq[(dev->pos_regs[2] & 0xE) >> 1]; + /* Save the new IRQ values. */ + dev->base_irq = irq[(dev->pos_regs[2] & 0xE) >> 1]; - dev->bios_addr = 0x0000; - dev->has_bios = 0; + dev->bios_addr = 0x0000; + dev->has_bios = 0; /* * The PS/2 Model 80 BIOS always enables a card if it finds one, @@ -895,65 +875,61 @@ nic_mca_write(int port, uint8_t val, void *priv) /* Initialize the device if fully configured. */ if (dev->pos_regs[2] & 0x01) { - /* Card enabled; register (new) I/O handler. */ + /* Card enabled; register (new) I/O handler. */ - nic_ioset(dev, dev->base_address); + nic_ioset(dev, dev->base_address); - nic_reset(dev); - - nelog(2, "EtherNext/MC: Port=%04x, IRQ=%d\n", dev->base_address, dev->base_irq); + nic_reset(dev); + nelog(2, "EtherNext/MC: Port=%04x, IRQ=%d\n", dev->base_address, dev->base_irq); } } - static uint8_t nic_mca_feedb(void *priv) { - nic_t *dev = (nic_t *)priv; + nic_t *dev = (nic_t *) priv; return (dev->pos_regs[2] & 0x01); } - static void * nic_init(const device_t *info) { uint32_t mac; - char *rom; - nic_t *dev; + char *rom; + nic_t *dev; dev = malloc(sizeof(nic_t)); memset(dev, 0x00, sizeof(nic_t)); - dev->name = info->name; + dev->name = info->name; dev->board = info->local; - rom = NULL; + rom = NULL; if (dev->board >= NE2K_RTL8019AS) { - dev->base_address = 0x340; - dev->base_irq = 12; - if (dev->board == NE2K_RTL8029AS) { - dev->bios_addr = 0xD0000; - dev->has_bios = device_get_config_int("bios"); - } else { - dev->bios_addr = 0x00000; - dev->has_bios = 0; - } + dev->base_address = 0x340; + dev->base_irq = 12; + if (dev->board == NE2K_RTL8029AS) { + dev->bios_addr = 0xD0000; + dev->has_bios = device_get_config_int("bios"); + } else { + dev->bios_addr = 0x00000; + dev->has_bios = 0; + } } else { - if (dev->board != NE2K_ETHERNEXT_MC) { - dev->base_address = device_get_config_hex16("base"); - dev->base_irq = device_get_config_int("irq"); - if (dev->board == NE2K_NE2000) { - dev->bios_addr = device_get_config_hex20("bios_addr"); - dev->has_bios = !!dev->bios_addr; - } else { - dev->bios_addr = 0x00000; - dev->has_bios = 0; - } - } - else { - mca_add(nic_mca_read, nic_mca_write, nic_mca_feedb, NULL, dev); - } + if (dev->board != NE2K_ETHERNEXT_MC) { + dev->base_address = device_get_config_hex16("base"); + dev->base_irq = device_get_config_int("irq"); + if (dev->board == NE2K_NE2000) { + dev->bios_addr = device_get_config_hex20("bios_addr"); + dev->has_bios = !!dev->bios_addr; + } else { + dev->bios_addr = 0x00000; + dev->has_bios = 0; + } + } else { + mca_add(nic_mca_read, nic_mca_write, nic_mca_feedb, NULL, dev); + } } /* See if we have a local MAC address configured. */ @@ -961,180 +937,171 @@ nic_init(const device_t *info) /* Set up our BIA. */ if (mac & 0xff000000) { - /* Generate new local MAC. */ - dev->maclocal[3] = random_generate(); - dev->maclocal[4] = random_generate(); - dev->maclocal[5] = random_generate(); - mac = (((int) dev->maclocal[3]) << 16); - mac |= (((int) dev->maclocal[4]) << 8); - mac |= ((int) dev->maclocal[5]); - device_set_config_mac("mac", mac); + /* Generate new local MAC. */ + dev->maclocal[3] = random_generate(); + dev->maclocal[4] = random_generate(); + dev->maclocal[5] = random_generate(); + mac = (((int) dev->maclocal[3]) << 16); + mac |= (((int) dev->maclocal[4]) << 8); + mac |= ((int) dev->maclocal[5]); + device_set_config_mac("mac", mac); } else { - dev->maclocal[3] = (mac>>16) & 0xff; - dev->maclocal[4] = (mac>>8) & 0xff; - dev->maclocal[5] = (mac & 0xff); + dev->maclocal[3] = (mac >> 16) & 0xff; + dev->maclocal[4] = (mac >> 8) & 0xff; + dev->maclocal[5] = (mac & 0xff); } - dev->dp8390 = device_add_inst(&dp8390_device, dp3890_inst++); - dev->dp8390->priv = dev; + dev->dp8390 = device_add_inst(&dp8390_device, dp3890_inst++); + dev->dp8390->priv = dev; dev->dp8390->interrupt = nic_interrupt; - switch(dev->board) { - case NE2K_NE1000: - dev->maclocal[0] = 0x00; /* 00:00:D8 (Novell OID) */ - dev->maclocal[1] = 0x00; - dev->maclocal[2] = 0xD8; - dev->is_8bit = 1; - rom = NULL; - dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ); - dp8390_mem_alloc(dev->dp8390, 0x2000, 0x2000); - break; + switch (dev->board) { + case NE2K_NE1000: + dev->maclocal[0] = 0x00; /* 00:00:D8 (Novell OID) */ + dev->maclocal[1] = 0x00; + dev->maclocal[2] = 0xD8; + dev->is_8bit = 1; + rom = NULL; + dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ); + dp8390_mem_alloc(dev->dp8390, 0x2000, 0x2000); + break; - case NE2K_NE2000: - dev->maclocal[0] = 0x00; /* 00:00:D8 (Novell OID) */ - dev->maclocal[1] = 0x00; - dev->maclocal[2] = 0xD8; - rom = ROM_PATH_NE2000; - dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CHECK_CR | - DP8390_FLAG_CLEAR_IRQ); - dp8390_mem_alloc(dev->dp8390, 0x4000, 0x4000); - break; + case NE2K_NE2000: + dev->maclocal[0] = 0x00; /* 00:00:D8 (Novell OID) */ + dev->maclocal[1] = 0x00; + dev->maclocal[2] = 0xD8; + rom = ROM_PATH_NE2000; + dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ); + dp8390_mem_alloc(dev->dp8390, 0x4000, 0x4000); + break; - case NE2K_ETHERNEXT_MC: - dev->maclocal[0] = 0x00; /* 00:00:D8 (Networth Inc. OID) */ - dev->maclocal[1] = 0x00; - dev->maclocal[2] = 0x79; - dev->pos_regs[0] = 0x1F; - dev->pos_regs[1] = 0x61; - rom = NULL; - dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CHECK_CR | - DP8390_FLAG_CLEAR_IRQ); - dp8390_mem_alloc(dev->dp8390, 0x4000, 0x4000); - break; + case NE2K_ETHERNEXT_MC: + dev->maclocal[0] = 0x00; /* 00:00:D8 (Networth Inc. OID) */ + dev->maclocal[1] = 0x00; + dev->maclocal[2] = 0x79; + dev->pos_regs[0] = 0x1F; + dev->pos_regs[1] = 0x61; + rom = NULL; + dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ); + dp8390_mem_alloc(dev->dp8390, 0x4000, 0x4000); + break; - case NE2K_RTL8019AS: - case NE2K_RTL8029AS: - dev->is_pci = (dev->board == NE2K_RTL8029AS) ? 1 : 0; - dev->maclocal[0] = 0x00; /* 00:E0:4C (Realtek OID) */ - dev->maclocal[1] = 0xE0; - dev->maclocal[2] = 0x4C; - rom = (dev->board == NE2K_RTL8019AS) ? ROM_PATH_RTL8019 : ROM_PATH_RTL8029; - if (dev->is_pci) - dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC); - else - dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CLEAR_IRQ); - dp8390_set_id(dev->dp8390, 0x50, (dev->board == NE2K_RTL8019AS) ? 0x70 : 0x43); - dp8390_mem_alloc(dev->dp8390, 0x4000, 0x8000); - break; + case NE2K_RTL8019AS: + case NE2K_RTL8029AS: + dev->is_pci = (dev->board == NE2K_RTL8029AS) ? 1 : 0; + dev->maclocal[0] = 0x00; /* 00:E0:4C (Realtek OID) */ + dev->maclocal[1] = 0xE0; + dev->maclocal[2] = 0x4C; + rom = (dev->board == NE2K_RTL8019AS) ? ROM_PATH_RTL8019 : ROM_PATH_RTL8029; + if (dev->is_pci) + dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC); + else + dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CLEAR_IRQ); + dp8390_set_id(dev->dp8390, 0x50, (dev->board == NE2K_RTL8019AS) ? 0x70 : 0x43); + dp8390_mem_alloc(dev->dp8390, 0x4000, 0x8000); + break; } memcpy(dev->dp8390->physaddr, dev->maclocal, sizeof(dev->maclocal)); nelog(2, "%s: I/O=%04x, IRQ=%d, MAC=%02x:%02x:%02x:%02x:%02x:%02x\n", - dev->name, dev->base_address, dev->base_irq, - dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2], - dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]); + dev->name, dev->base_address, dev->base_irq, + dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2], + dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]); /* * Make this device known to the I/O system. * PnP and PCI devices start with address spaces inactive. */ if (dev->board < NE2K_RTL8019AS && dev->board != NE2K_ETHERNEXT_MC) - nic_ioset(dev, dev->base_address); + nic_ioset(dev, dev->base_address); /* Set up our BIOS ROM space, if any. */ nic_rom_init(dev, rom); if (dev->board >= NE2K_RTL8019AS) { - if (dev->is_pci) { - /* - * Configure the PCI space registers. - * - * We do this here, so the I/O routines are generic. - */ - memset(dev->pci_regs, 0, PCI_REGSIZE); + if (dev->is_pci) { + /* + * Configure the PCI space registers. + * + * We do this here, so the I/O routines are generic. + */ + memset(dev->pci_regs, 0, PCI_REGSIZE); - dev->pci_regs[0x00] = (PCI_VENDID&0xff); - dev->pci_regs[0x01] = (PCI_VENDID>>8); - dev->pci_regs[0x02] = (PCI_DEVID&0xff); - dev->pci_regs[0x03] = (PCI_DEVID>>8); + dev->pci_regs[0x00] = (PCI_VENDID & 0xff); + dev->pci_regs[0x01] = (PCI_VENDID >> 8); + dev->pci_regs[0x02] = (PCI_DEVID & 0xff); + dev->pci_regs[0x03] = (PCI_DEVID >> 8); - dev->pci_regs[0x04] = 0x03; /* IOEN */ - dev->pci_regs[0x05] = 0x00; - dev->pci_regs[0x07] = 0x02; /* DST0, medium devsel */ + dev->pci_regs[0x04] = 0x03; /* IOEN */ + dev->pci_regs[0x05] = 0x00; + dev->pci_regs[0x07] = 0x02; /* DST0, medium devsel */ - dev->pci_regs[0x09] = 0x00; /* PIFR */ + dev->pci_regs[0x09] = 0x00; /* PIFR */ - dev->pci_regs[0x0B] = 0x02; /* BCR: Network Controller */ - dev->pci_regs[0x0A] = 0x00; /* SCR: Ethernet */ + dev->pci_regs[0x0B] = 0x02; /* BCR: Network Controller */ + dev->pci_regs[0x0A] = 0x00; /* SCR: Ethernet */ - dev->pci_regs[0x2C] = (PCI_VENDID&0xff); - dev->pci_regs[0x2D] = (PCI_VENDID>>8); - dev->pci_regs[0x2E] = (PCI_DEVID&0xff); - dev->pci_regs[0x2F] = (PCI_DEVID>>8); + dev->pci_regs[0x2C] = (PCI_VENDID & 0xff); + dev->pci_regs[0x2D] = (PCI_VENDID >> 8); + dev->pci_regs[0x2E] = (PCI_DEVID & 0xff); + dev->pci_regs[0x2F] = (PCI_DEVID >> 8); - dev->pci_regs[0x3D] = PCI_INTA; /* PCI_IPR */ + dev->pci_regs[0x3D] = PCI_INTA; /* PCI_IPR */ - /* Enable our address space in PCI. */ - dev->pci_bar[0].addr_regs[0] = 0x01; + /* Enable our address space in PCI. */ + dev->pci_bar[0].addr_regs[0] = 0x01; - /* Enable our BIOS space in PCI, if needed. */ - if (dev->bios_addr > 0) { - dev->pci_bar[1].addr = 0xFFFF8000; - dev->pci_bar[1].addr_regs[1] = dev->bios_mask; - } else { - dev->pci_bar[1].addr = 0; - dev->bios_size = 0; - } + /* Enable our BIOS space in PCI, if needed. */ + if (dev->bios_addr > 0) { + dev->pci_bar[1].addr = 0xFFFF8000; + dev->pci_bar[1].addr_regs[1] = dev->bios_mask; + } else { + dev->pci_bar[1].addr = 0; + dev->bios_size = 0; + } - mem_mapping_disable(&dev->bios_rom.mapping); + mem_mapping_disable(&dev->bios_rom.mapping); - /* Add device to the PCI bus, keep its slot number. */ - dev->card = pci_add_card(PCI_ADD_NORMAL, - nic_pci_read, nic_pci_write, dev); - } + /* Add device to the PCI bus, keep its slot number. */ + dev->card = pci_add_card(PCI_ADD_NORMAL, + nic_pci_read, nic_pci_write, dev); + } - /* Initialize the RTL8029 EEPROM. */ + /* Initialize the RTL8029 EEPROM. */ memset(dev->eeprom, 0x00, sizeof(dev->eeprom)); - if (dev->board == NE2K_RTL8029AS) { - memcpy(&dev->eeprom[0x02], dev->maclocal, 6); + if (dev->board == NE2K_RTL8029AS) { + memcpy(&dev->eeprom[0x02], dev->maclocal, 6); - dev->eeprom[0x76] = - dev->eeprom[0x7A] = - dev->eeprom[0x7E] = (PCI_DEVID&0xff); - dev->eeprom[0x77] = - dev->eeprom[0x7B] = - dev->eeprom[0x7F] = (PCI_DEVID>>8); - dev->eeprom[0x78] = - dev->eeprom[0x7C] = (PCI_VENDID&0xff); - dev->eeprom[0x79] = - dev->eeprom[0x7D] = (PCI_VENDID>>8); - } else { - memcpy(&dev->eeprom[0x12], rtl8019as_pnp_rom, sizeof(rtl8019as_pnp_rom)); + dev->eeprom[0x76] = dev->eeprom[0x7A] = dev->eeprom[0x7E] = (PCI_DEVID & 0xff); + dev->eeprom[0x77] = dev->eeprom[0x7B] = dev->eeprom[0x7F] = (PCI_DEVID >> 8); + dev->eeprom[0x78] = dev->eeprom[0x7C] = (PCI_VENDID & 0xff); + dev->eeprom[0x79] = dev->eeprom[0x7D] = (PCI_VENDID >> 8); + } else { + memcpy(&dev->eeprom[0x12], rtl8019as_pnp_rom, sizeof(rtl8019as_pnp_rom)); - dev->pnp_card = isapnp_add_card(&dev->eeprom[0x12], sizeof(rtl8019as_pnp_rom), nic_pnp_config_changed, nic_pnp_csn_changed, nic_pnp_read_vendor_reg, nic_pnp_write_vendor_reg, dev); - } + dev->pnp_card = isapnp_add_card(&dev->eeprom[0x12], sizeof(rtl8019as_pnp_rom), nic_pnp_config_changed, nic_pnp_csn_changed, nic_pnp_read_vendor_reg, nic_pnp_write_vendor_reg, dev); + } } if (dev->board != NE2K_ETHERNEXT_MC) - /* Reset the board. */ - nic_reset(dev); + /* Reset the board. */ + nic_reset(dev); /* Attach ourselves to the network module. */ dev->dp8390->card = network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL); nelog(1, "%s: %s attached IO=0x%X IRQ=%d\n", dev->name, - dev->is_pci?"PCI":"ISA", dev->base_address, dev->base_irq); + dev->is_pci ? "PCI" : "ISA", dev->base_address, dev->base_irq); - return(dev); + return (dev); } - static void nic_close(void *priv) { - nic_t *dev = (nic_t *)priv; + nic_t *dev = (nic_t *) priv; nelog(1, "%s: closed\n", dev->name); @@ -1294,71 +1261,71 @@ static const device_config_t mca_mac_config[] = { // clang-format on const device_t ne1000_device = { - .name = "Novell NE1000", + .name = "Novell NE1000", .internal_name = "ne1k", - .flags = DEVICE_ISA, - .local = NE2K_NE1000, - .init = nic_init, - .close = nic_close, - .reset = NULL, + .flags = DEVICE_ISA, + .local = NE2K_NE1000, + .init = nic_init, + .close = nic_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = ne1000_config + .force_redraw = NULL, + .config = ne1000_config }; const device_t ne2000_device = { - .name = "Novell NE2000", + .name = "Novell NE2000", .internal_name = "ne2k", - .flags = DEVICE_ISA | DEVICE_AT, - .local = NE2K_NE2000, - .init = nic_init, - .close = nic_close, - .reset = NULL, + .flags = DEVICE_ISA | DEVICE_AT, + .local = NE2K_NE2000, + .init = nic_init, + .close = nic_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = ne2000_config + .force_redraw = NULL, + .config = ne2000_config }; const device_t ethernext_mc_device = { - .name = "NetWorth EtherNext/MC", + .name = "NetWorth EtherNext/MC", .internal_name = "ethernextmc", - .flags = DEVICE_MCA, - .local = NE2K_ETHERNEXT_MC, - .init = nic_init, - .close = nic_close, - .reset = NULL, + .flags = DEVICE_MCA, + .local = NE2K_ETHERNEXT_MC, + .init = nic_init, + .close = nic_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = mca_mac_config + .force_redraw = NULL, + .config = mca_mac_config }; const device_t rtl8019as_device = { - .name = "Realtek RTL8019AS", + .name = "Realtek RTL8019AS", .internal_name = "ne2kpnp", - .flags = DEVICE_ISA | DEVICE_AT, - .local = NE2K_RTL8019AS, - .init = nic_init, - .close = nic_close, - .reset = NULL, + .flags = DEVICE_ISA | DEVICE_AT, + .local = NE2K_RTL8019AS, + .init = nic_init, + .close = nic_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = rtl8019as_config + .force_redraw = NULL, + .config = rtl8019as_config }; const device_t rtl8029as_device = { - .name = "Realtek RTL8029AS", + .name = "Realtek RTL8029AS", .internal_name = "ne2kpci", - .flags = DEVICE_PCI, - .local = NE2K_RTL8029AS, - .init = nic_init, - .close = nic_close, - .reset = NULL, + .flags = DEVICE_PCI, + .local = NE2K_RTL8029AS, + .init = nic_init, + .close = nic_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = rtl8029as_config + .force_redraw = NULL, + .config = rtl8029as_config }; diff --git a/src/network/net_pcap.c b/src/network/net_pcap.c index 9aa486316..69dc2ca14 100644 --- a/src/network/net_pcap.c +++ b/src/network/net_pcap.c @@ -52,14 +52,14 @@ #include #include #ifdef _WIN32 -#define WIN32_LEAN_AND_MEAN -#include -#include +# define WIN32_LEAN_AND_MEAN +# include +# include #else -#include -#include -#include -#include +# include +# include +# include +# include #endif #define HAVE_STDARG_H @@ -82,45 +82,45 @@ enum { }; #ifdef __APPLE__ -#include +# include #else -typedef int bpf_int32; +typedef int bpf_int32; typedef unsigned int bpf_u_int32; /* * The instruction data structure. */ struct bpf_insn { - unsigned short code; - unsigned char jt; - unsigned char jf; - bpf_u_int32 k; + unsigned short code; + unsigned char jt; + unsigned char jf; + bpf_u_int32 k; }; /* * Structure for "pcap_compile()", "pcap_setfilter()", etc.. */ struct bpf_program { - unsigned int bf_len; + unsigned int bf_len; struct bpf_insn *bf_insns; }; -typedef struct pcap_if pcap_if_t; +typedef struct pcap_if pcap_if_t; -#define PCAP_ERRBUF_SIZE 256 +# define PCAP_ERRBUF_SIZE 256 struct pcap_pkthdr { - struct timeval ts; - bpf_u_int32 caplen; - bpf_u_int32 len; + struct timeval ts; + bpf_u_int32 caplen; + bpf_u_int32 len; }; struct pcap_if { struct pcap_if *next; - char *name; - char *description; - void *addresses; - bpf_u_int32 flags; + char *name; + char *description; + void *addresses; + bpf_u_int32 flags; }; struct pcap_send_queue { @@ -154,39 +154,39 @@ typedef struct { uint8_t *mac_addr; } net_pcap_params_t; -static volatile void *libpcap_handle; /* handle to WinPcap DLL */ +static volatile void *libpcap_handle; /* handle to WinPcap DLL */ /* Pointers to the real functions. */ -static const char *(*f_pcap_lib_version)(void); -static int (*f_pcap_findalldevs)(pcap_if_t **,char *); -static void (*f_pcap_freealldevs)(void *); -static void *(*f_pcap_open_live)(const char *,int,int,int,char *); -static int (*f_pcap_compile)(void *,void *, const char *,int,bpf_u_int32); -static int (*f_pcap_setfilter)(void *,void *); +static const char *(*f_pcap_lib_version)(void); +static int (*f_pcap_findalldevs)(pcap_if_t **, char *); +static void (*f_pcap_freealldevs)(void *); +static void *(*f_pcap_open_live)(const char *, int, int, int, char *); +static int (*f_pcap_compile)(void *, void *, const char *, int, bpf_u_int32); +static int (*f_pcap_setfilter)(void *, void *); static const unsigned char - *(*f_pcap_next)(void *,void *); -static int (*f_pcap_sendpacket)(void *,const unsigned char *,int); -static void (*f_pcap_close)(void *); -static int (*f_pcap_setnonblock)(void*, int, char*); -static int (*f_pcap_set_immediate_mode)(void *, int); -static int (*f_pcap_set_promisc)(void *, int); -static int (*f_pcap_set_snaplen)(void *, int); -static int (*f_pcap_dispatch)(void *, int, pcap_handler callback, u_char *user); -static void *(*f_pcap_create)(const char *, char*); -static int (*f_pcap_activate)(void *); -static void *(*f_pcap_geterr)(void *); + *(*f_pcap_next)(void *, void *); +static int (*f_pcap_sendpacket)(void *, const unsigned char *, int); +static void (*f_pcap_close)(void *); +static int (*f_pcap_setnonblock)(void *, int, char *); +static int (*f_pcap_set_immediate_mode)(void *, int); +static int (*f_pcap_set_promisc)(void *, int); +static int (*f_pcap_set_snaplen)(void *, int); +static int (*f_pcap_dispatch)(void *, int, pcap_handler callback, u_char *user); +static void *(*f_pcap_create)(const char *, char *); +static int (*f_pcap_activate)(void *); +static void *(*f_pcap_geterr)(void *); #ifdef _WIN32 static HANDLE (*f_pcap_getevent)(void *); -static int (*f_pcap_sendqueue_queue)(void *, void *, void *); -static u_int (*f_pcap_sendqueue_transmit)(void *, void *, int sync); -static void *(*f_pcap_sendqueue_alloc)(u_int memsize); -static void (*f_pcap_sendqueue_destroy)(void *); +static int (*f_pcap_sendqueue_queue)(void *, void *, void *); +static u_int (*f_pcap_sendqueue_transmit)(void *, void *, int sync); +static void *(*f_pcap_sendqueue_alloc)(u_int memsize); +static void (*f_pcap_sendqueue_destroy)(void *); #else -static int (*f_pcap_get_selectable_fd)(void *); +static int (*f_pcap_get_selectable_fd)(void *); #endif static dllimp_t pcap_imports[] = { - { "pcap_lib_version", &f_pcap_lib_version }, + {"pcap_lib_version", &f_pcap_lib_version }, { "pcap_findalldevs", &f_pcap_findalldevs }, { "pcap_freealldevs", &f_pcap_freealldevs }, { "pcap_open_live", &f_pcap_open_live }, @@ -210,7 +210,7 @@ static dllimp_t pcap_imports[] = { { "pcap_sendqueue_alloc", &f_pcap_sendqueue_alloc }, { "pcap_sendqueue_destroy", &f_pcap_sendqueue_destroy }, #else - { "pcap_get_selectable_fd", &f_pcap_get_selectable_fd }, + { "pcap_get_selectable_fd", &f_pcap_get_selectable_fd }, #endif { NULL, NULL }, }; @@ -224,20 +224,19 @@ pcap_log(const char *fmt, ...) va_list ap; if (pcap_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define pcap_log(fmt, ...) +# define pcap_log(fmt, ...) #endif - static void net_pcap_rx_handler(uint8_t *user, const struct pcap_pkthdr *h, const uint8_t *bytes) { - net_pcap_t *pcap = (net_pcap_t*)user; + net_pcap_t *pcap = (net_pcap_t *) user; memcpy(pcap->pkt.data, bytes, h->caplen); pcap->pkt.len = h->caplen; network_rx_put_pkt(pcap->card, &pcap->pkt); @@ -248,15 +247,15 @@ void net_pcap_in(void *pcap, uint8_t *bufp, int len) { if (pcap == NULL) - return; + return; - f_pcap_sendpacket((void *)pcap, bufp, len); + f_pcap_sendpacket((void *) pcap, bufp, len); } void net_pcap_in_available(void *priv) { - net_pcap_t *pcap = (net_pcap_t *)priv; + net_pcap_t *pcap = (net_pcap_t *) priv; net_event_set(&pcap->tx_event); } @@ -264,14 +263,14 @@ net_pcap_in_available(void *priv) static void net_pcap_thread(void *priv) { - net_pcap_t *pcap = (net_pcap_t*)priv; + net_pcap_t *pcap = (net_pcap_t *) priv; pcap_log("PCAP: polling started.\n"); HANDLE events[NET_EVENT_MAX]; events[NET_EVENT_STOP] = net_event_get_handle(&pcap->stop_event); - events[NET_EVENT_TX] = net_event_get_handle(&pcap->tx_event); - events[NET_EVENT_RX] = f_pcap_getevent((void *)pcap->pcap); + events[NET_EVENT_TX] = net_event_get_handle(&pcap->tx_event); + events[NET_EVENT_RX] = f_pcap_getevent((void *) pcap->pcap); bool run = true; @@ -297,7 +296,7 @@ net_pcap_thread(void *priv) break; case NET_EVENT_RX: - f_pcap_dispatch(pcap->pcap, PCAP_PKT_BATCH, net_pcap_rx_handler, (u_char *)pcap); + f_pcap_dispatch(pcap->pcap, PCAP_PKT_BATCH, net_pcap_rx_handler, (u_char *) pcap); break; } } @@ -308,7 +307,7 @@ net_pcap_thread(void *priv) static void net_pcap_thread(void *priv) { - net_pcap_t *pcap = (net_pcap_t*)priv; + net_pcap_t *pcap = (net_pcap_t *) priv; pcap_log("PCAP: polling started.\n"); @@ -341,9 +340,8 @@ net_pcap_thread(void *priv) } if (pfd[NET_EVENT_RX].revents & POLLIN) { - f_pcap_dispatch(pcap->pcap, PCAP_PKT_BATCH, net_pcap_rx_handler, (u_char *)pcap); + f_pcap_dispatch(pcap->pcap, PCAP_PKT_BATCH, net_pcap_rx_handler, (u_char *) pcap); } - } pcap_log("PCAP: polling stopped.\n"); @@ -360,9 +358,9 @@ net_pcap_thread(void *priv) int net_pcap_prepare(netdev_t *list) { - char errbuf[PCAP_ERRBUF_SIZE]; + char errbuf[PCAP_ERRBUF_SIZE]; pcap_if_t *devlist, *dev; - int i = 0; + int i = 0; /* Try loading the DLL. */ #ifdef _WIN32 @@ -374,44 +372,44 @@ net_pcap_prepare(netdev_t *list) #endif if (libpcap_handle == NULL) { pcap_log("PCAP: error loading pcap module\n"); - return(-1); + return (-1); } /* Retrieve the device list from the local machine */ if (f_pcap_findalldevs(&devlist, errbuf) == -1) { - pcap_log("PCAP: error in pcap_findalldevs: %s\n", errbuf); - return(-1); + pcap_log("PCAP: error in pcap_findalldevs: %s\n", errbuf); + return (-1); } - for (dev=devlist; dev!=NULL; dev=dev->next) { - if (i >= (NET_HOST_INTF_MAX - 1)) - break; + for (dev = devlist; dev != NULL; dev = dev->next) { + if (i >= (NET_HOST_INTF_MAX - 1)) + break; - /** - * we initialize the strings to NULL first for strncpy - */ + /** + * we initialize the strings to NULL first for strncpy + */ - memset(list->device, '\0', sizeof(list->device)); - memset(list->description, '\0', sizeof(list->description)); + memset(list->device, '\0', sizeof(list->device)); + memset(list->description, '\0', sizeof(list->description)); - strncpy(list->device, dev->name, sizeof(list->device) - 1); - if (dev->description) { - strncpy(list->description, dev->description, sizeof(list->description) - 1); - } else { - /* if description is NULL, set the name. This allows pcap to display *something* useful under WINE */ - strncpy(list->description, dev->name, sizeof(list->description) - 1); - } + strncpy(list->device, dev->name, sizeof(list->device) - 1); + if (dev->description) { + strncpy(list->description, dev->description, sizeof(list->description) - 1); + } else { + /* if description is NULL, set the name. This allows pcap to display *something* useful under WINE */ + strncpy(list->description, dev->name, sizeof(list->description) - 1); + } - list++; i++; + list++; + i++; } /* Release the memory. */ f_pcap_freealldevs(devlist); - return(i); + return (i); } - /* * Initialize (Win)Pcap for use. * @@ -422,12 +420,12 @@ net_pcap_prepare(netdev_t *list) void * net_pcap_init(const netcard_t *card, const uint8_t *mac_addr, void *priv) { - char errbuf[PCAP_ERRBUF_SIZE]; - char *str; - char filter_exp[255]; + char errbuf[PCAP_ERRBUF_SIZE]; + char *str; + char filter_exp[255]; struct bpf_program fp; - char *intf_name = (char*)priv; + char *intf_name = (char *) priv; /* Did we already load the library? */ if (libpcap_handle == NULL) { @@ -451,7 +449,7 @@ net_pcap_init(const netcard_t *card, const uint8_t *mac_addr, void *priv) pcap_log("PCAP: interface: %s\n", intf_name); net_pcap_t *pcap = calloc(1, sizeof(net_pcap_t)); - pcap->card = (netcard_t *)card; + pcap->card = (netcard_t *) card; memcpy(pcap->mac_addr, mac_addr, sizeof(pcap->mac_addr)); if ((pcap->pcap = f_pcap_create(intf_name, errbuf)) == NULL) { @@ -494,7 +492,7 @@ net_pcap_init(const netcard_t *card, const uint8_t *mac_addr, void *priv) return NULL; } } else { - pcap_log("PCAP: could not compile filter (%s) : %s!\n", filter_exp, f_pcap_geterr((void*)pcap->pcap)); + pcap_log("PCAP: could not compile filter (%s) : %s!\n", filter_exp, f_pcap_geterr((void *) pcap->pcap)); f_pcap_close((void *) pcap->pcap); free(pcap); return NULL; @@ -523,7 +521,7 @@ net_pcap_close(void *priv) if (!priv) return; - net_pcap_t *pcap = (net_pcap_t *)priv; + net_pcap_t *pcap = (net_pcap_t *) priv; pcap_log("PCAP: closing.\n"); @@ -541,10 +539,10 @@ net_pcap_close(void *priv) free(pcap->pkt.data); #ifdef _WIN32 - f_pcap_sendqueue_destroy((void*)pcap->pcap_queue); + f_pcap_sendqueue_destroy((void *) pcap->pcap_queue); #endif /* OK, now shut down Pcap itself. */ - f_pcap_close((void*)pcap->pcap); + f_pcap_close((void *) pcap->pcap); net_event_close(&pcap->tx_event); net_event_close(&pcap->stop_event); diff --git a/src/network/net_pcnet.c b/src/network/net_pcnet.c index 340b056d3..1ee1d1276 100644 --- a/src/network/net_pcnet.c +++ b/src/network/net_pcnet.c @@ -17,9 +17,9 @@ * Copyright 2016-2019 Miran Grca. */ #ifdef _WIN32 -#include +# include #else -#include +# include #endif #include #include @@ -49,104 +49,103 @@ #include <86box/bswap.h> /* PCI info. */ -#define PCI_VENDID 0x1022 /* AMD */ -#define PCI_DEVID 0x2000 /* PCnet-PCI II (Am79c970A) */ -#define PCI_REGSIZE 256 /* size of PCI space */ +#define PCI_VENDID 0x1022 /* AMD */ +#define PCI_DEVID 0x2000 /* PCnet-PCI II (Am79c970A) */ +#define PCI_REGSIZE 256 /* size of PCI space */ #pragma pack(1) -typedef struct RTNETETHERHDR -{ - uint8_t DstMac[6]; - uint8_t SrcMac[6]; +typedef struct RTNETETHERHDR { + uint8_t DstMac[6]; + uint8_t SrcMac[6]; /** Ethernet frame type or frame size, depending on the kind of ethernet. * This is big endian on the wire. */ - uint16_t EtherType; + uint16_t EtherType; } RTNETETHERHDR; #pragma pack() -#define BCR_MAX_RAP 50 -#define MII_MAX_REG 32 -#define CSR_MAX_REG 128 +#define BCR_MAX_RAP 50 +#define MII_MAX_REG 32 +#define CSR_MAX_REG 128 /** Maximum number of times we report a link down to the guest (failure to send frame) */ -#define PCNET_MAX_LINKDOWN_REPORTED 3 +#define PCNET_MAX_LINKDOWN_REPORTED 3 /** Maximum frame size we handle */ -#define MAX_FRAME 1536 +#define MAX_FRAME 1536 /** @name Bus configuration registers * @{ */ -#define BCR_MSRDA 0 -#define BCR_MSWRA 1 -#define BCR_MC 2 -#define BCR_RESERVED3 3 -#define BCR_LNKST 4 -#define BCR_LED1 5 -#define BCR_LED2 6 -#define BCR_LED3 7 -#define BCR_SWCONFIG 8 -#define BCR_FDC 9 +#define BCR_MSRDA 0 +#define BCR_MSWRA 1 +#define BCR_MC 2 +#define BCR_RESERVED3 3 +#define BCR_LNKST 4 +#define BCR_LED1 5 +#define BCR_LED2 6 +#define BCR_LED3 7 +#define BCR_SWCONFIG 8 +#define BCR_FDC 9 /* 10 - 15 = reserved */ -#define BCR_IOBASEL 16 /* Reserved */ -#define BCR_IOBASEU 16 /* Reserved */ -#define BCR_BSBC 18 -#define BCR_EECAS 19 -#define BCR_SWS 20 -#define BCR_INTCON 21 /* Reserved */ -#define BCR_PLAT 22 -#define BCR_PCISVID 23 -#define BCR_PCISID 24 -#define BCR_SRAMSIZ 25 -#define BCR_SRAMB 26 -#define BCR_SRAMIC 27 -#define BCR_EBADDRL 28 -#define BCR_EBADDRU 29 -#define BCR_EBD 30 -#define BCR_STVAL 31 -#define BCR_MIICAS 32 -#define BCR_MIIADDR 33 -#define BCR_MIIMDR 34 -#define BCR_PCIVID 35 -#define BCR_PMC_A 36 -#define BCR_DATA0 37 -#define BCR_DATA1 38 -#define BCR_DATA2 39 -#define BCR_DATA3 40 -#define BCR_DATA4 41 -#define BCR_DATA5 42 -#define BCR_DATA6 43 -#define BCR_DATA7 44 -#define BCR_PMR1 45 -#define BCR_PMR2 46 -#define BCR_PMR3 47 +#define BCR_IOBASEL 16 /* Reserved */ +#define BCR_IOBASEU 16 /* Reserved */ +#define BCR_BSBC 18 +#define BCR_EECAS 19 +#define BCR_SWS 20 +#define BCR_INTCON 21 /* Reserved */ +#define BCR_PLAT 22 +#define BCR_PCISVID 23 +#define BCR_PCISID 24 +#define BCR_SRAMSIZ 25 +#define BCR_SRAMB 26 +#define BCR_SRAMIC 27 +#define BCR_EBADDRL 28 +#define BCR_EBADDRU 29 +#define BCR_EBD 30 +#define BCR_STVAL 31 +#define BCR_MIICAS 32 +#define BCR_MIIADDR 33 +#define BCR_MIIMDR 34 +#define BCR_PCIVID 35 +#define BCR_PMC_A 36 +#define BCR_DATA0 37 +#define BCR_DATA1 38 +#define BCR_DATA2 39 +#define BCR_DATA3 40 +#define BCR_DATA4 41 +#define BCR_DATA5 42 +#define BCR_DATA6 43 +#define BCR_DATA7 44 +#define BCR_PMR1 45 +#define BCR_PMR2 46 +#define BCR_PMR3 47 /** @} */ /** @name Bus configuration sub register accessors. * @{ */ -#define BCR_DWIO(S) !!((S)->aBCR[BCR_BSBC] & 0x0080) -#define BCR_SSIZE32(S) !!((S)->aBCR[BCR_SWS ] & 0x0100) -#define BCR_SWSTYLE(S) ((S)->aBCR[BCR_SWS ] & 0x00FF) +#define BCR_DWIO(S) !!((S)->aBCR[BCR_BSBC] & 0x0080) +#define BCR_SSIZE32(S) !!((S)->aBCR[BCR_SWS] & 0x0100) +#define BCR_SWSTYLE(S) ((S)->aBCR[BCR_SWS] & 0x00FF) /** @} */ /** @name CSR subregister accessors. * @{ */ -#define CSR_INIT(S) !!((S)->aCSR[0] & 0x0001) /**< Init assertion */ -#define CSR_STRT(S) !!((S)->aCSR[0] & 0x0002) /**< Start assertion */ -#define CSR_STOP(S) !!((S)->aCSR[0] & 0x0004) /**< Stop assertion */ -#define CSR_TDMD(S) !!((S)->aCSR[0] & 0x0008) /**< Transmit demand. (perform xmit poll now (readable, settable, not clearable) */ -#define CSR_TXON(S) !!((S)->aCSR[0] & 0x0010) /**< Transmit on (readonly) */ -#define CSR_RXON(S) !!((S)->aCSR[0] & 0x0020) /**< Receive On */ -#define CSR_INEA(S) !!((S)->aCSR[0] & 0x0040) /**< Interrupt Enable */ -#define CSR_LAPPEN(S) !!((S)->aCSR[3] & 0x0020) /**< Look Ahead Packet Processing Enable */ -#define CSR_DXSUFLO(S) !!((S)->aCSR[3] & 0x0040) /**< Disable Transmit Stop on Underflow error */ -#define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400) /**< Auto Strip Receive */ -#define CSR_DPOLL(S) !!((S)->aCSR[4] & 0x1000) /**< Disable Transmit Polling */ -#define CSR_SPND(S) !!((S)->aCSR[5] & 0x0001) /**< Suspend */ -#define CSR_LTINTEN(S) !!((S)->aCSR[5] & 0x4000) /**< Last Transmit Interrupt Enable */ -#define CSR_TOKINTD(S) !!((S)->aCSR[5] & 0x8000) /**< Transmit OK Interrupt Disable */ +#define CSR_INIT(S) !!((S)->aCSR[0] & 0x0001) /**< Init assertion */ +#define CSR_STRT(S) !!((S)->aCSR[0] & 0x0002) /**< Start assertion */ +#define CSR_STOP(S) !!((S)->aCSR[0] & 0x0004) /**< Stop assertion */ +#define CSR_TDMD(S) !!((S)->aCSR[0] & 0x0008) /**< Transmit demand. (perform xmit poll now (readable, settable, not clearable) */ +#define CSR_TXON(S) !!((S)->aCSR[0] & 0x0010) /**< Transmit on (readonly) */ +#define CSR_RXON(S) !!((S)->aCSR[0] & 0x0020) /**< Receive On */ +#define CSR_INEA(S) !!((S)->aCSR[0] & 0x0040) /**< Interrupt Enable */ +#define CSR_LAPPEN(S) !!((S)->aCSR[3] & 0x0020) /**< Look Ahead Packet Processing Enable */ +#define CSR_DXSUFLO(S) !!((S)->aCSR[3] & 0x0040) /**< Disable Transmit Stop on Underflow error */ +#define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400) /**< Auto Strip Receive */ +#define CSR_DPOLL(S) !!((S)->aCSR[4] & 0x1000) /**< Disable Transmit Polling */ +#define CSR_SPND(S) !!((S)->aCSR[5] & 0x0001) /**< Suspend */ +#define CSR_LTINTEN(S) !!((S)->aCSR[5] & 0x4000) /**< Last Transmit Interrupt Enable */ +#define CSR_TOKINTD(S) !!((S)->aCSR[5] & 0x8000) /**< Transmit OK Interrupt Disable */ -#define CSR_STINT !!((S)->aCSR[7] & 0x0800) /**< Software Timer Interrupt */ -#define CSR_STINTE !!((S)->aCSR[7] & 0x0400) /**< Software Timer Interrupt Enable */ +#define CSR_STINT !!((S)->aCSR[7] & 0x0800) /**< Software Timer Interrupt */ +#define CSR_STINTE !!((S)->aCSR[7] & 0x0400) /**< Software Timer Interrupt Enable */ #define CSR_DRX(S) !!((S)->aCSR[15] & 0x0001) /**< Disable Receiver */ #define CSR_DTX(S) !!((S)->aCSR[15] & 0x0002) /**< Disable Transmit */ @@ -157,73 +156,71 @@ typedef struct RTNETETHERHDR /** @name CSR register accessors. * @{ */ -#define CSR_IADR(S) (*(uint32_t*)((S)->aCSR + 1)) /**< Initialization Block Address */ -#define CSR_CRBA(S) (*(uint32_t*)((S)->aCSR + 18)) /**< Current Receive Buffer Address */ -#define CSR_CXBA(S) (*(uint32_t*)((S)->aCSR + 20)) /**< Current Transmit Buffer Address */ -#define CSR_NRBA(S) (*(uint32_t*)((S)->aCSR + 22)) /**< Next Receive Buffer Address */ -#define CSR_BADR(S) (*(uint32_t*)((S)->aCSR + 24)) /**< Base Address of Receive Ring */ -#define CSR_NRDA(S) (*(uint32_t*)((S)->aCSR + 26)) /**< Next Receive Descriptor Address */ -#define CSR_CRDA(S) (*(uint32_t*)((S)->aCSR + 28)) /**< Current Receive Descriptor Address */ -#define CSR_BADX(S) (*(uint32_t*)((S)->aCSR + 30)) /**< Base Address of Transmit Descriptor */ -#define CSR_NXDA(S) (*(uint32_t*)((S)->aCSR + 32)) /**< Next Transmit Descriptor Address */ -#define CSR_CXDA(S) (*(uint32_t*)((S)->aCSR + 34)) /**< Current Transmit Descriptor Address */ -#define CSR_NNRD(S) (*(uint32_t*)((S)->aCSR + 36)) /**< Next Next Receive Descriptor Address */ -#define CSR_NNXD(S) (*(uint32_t*)((S)->aCSR + 38)) /**< Next Next Transmit Descriptor Address */ -#define CSR_CRBC(S) ((S)->aCSR[40]) /**< Current Receive Byte Count */ -#define CSR_CRST(S) ((S)->aCSR[41]) /**< Current Receive Status */ -#define CSR_CXBC(S) ((S)->aCSR[42]) /**< Current Transmit Byte Count */ -#define CSR_CXST(S) ((S)->aCSR[43]) /**< Current transmit status */ -#define CSR_NRBC(S) ((S)->aCSR[44]) /**< Next Receive Byte Count */ -#define CSR_NRST(S) ((S)->aCSR[45]) /**< Next Receive Status */ -#define CSR_POLL(S) ((S)->aCSR[46]) /**< Transmit Poll Time Counter */ -#define CSR_PINT(S) ((S)->aCSR[47]) /**< Transmit Polling Interval */ -#define CSR_PXDA(S) (*(uint32_t*)((S)->aCSR + 60)) /**< Previous Transmit Descriptor Address*/ -#define CSR_PXBC(S) ((S)->aCSR[62]) /**< Previous Transmit Byte Count */ -#define CSR_PXST(S) ((S)->aCSR[63]) /**< Previous Transmit Status */ -#define CSR_NXBA(S) (*(uint32_t*)((S)->aCSR + 64)) /**< Next Transmit Buffer Address */ -#define CSR_NXBC(S) ((S)->aCSR[66]) /**< Next Transmit Byte Count */ -#define CSR_NXST(S) ((S)->aCSR[67]) /**< Next Transmit Status */ -#define CSR_RCVRC(S) ((S)->aCSR[72]) /**< Receive Descriptor Ring Counter */ -#define CSR_XMTRC(S) ((S)->aCSR[74]) /**< Transmit Descriptor Ring Counter */ -#define CSR_RCVRL(S) ((S)->aCSR[76]) /**< Receive Descriptor Ring Length */ -#define CSR_XMTRL(S) ((S)->aCSR[78]) /**< Transmit Descriptor Ring Length */ -#define CSR_MISSC(S) ((S)->aCSR[112]) /**< Missed Frame Count */ +#define CSR_IADR(S) (*(uint32_t *) ((S)->aCSR + 1)) /**< Initialization Block Address */ +#define CSR_CRBA(S) (*(uint32_t *) ((S)->aCSR + 18)) /**< Current Receive Buffer Address */ +#define CSR_CXBA(S) (*(uint32_t *) ((S)->aCSR + 20)) /**< Current Transmit Buffer Address */ +#define CSR_NRBA(S) (*(uint32_t *) ((S)->aCSR + 22)) /**< Next Receive Buffer Address */ +#define CSR_BADR(S) (*(uint32_t *) ((S)->aCSR + 24)) /**< Base Address of Receive Ring */ +#define CSR_NRDA(S) (*(uint32_t *) ((S)->aCSR + 26)) /**< Next Receive Descriptor Address */ +#define CSR_CRDA(S) (*(uint32_t *) ((S)->aCSR + 28)) /**< Current Receive Descriptor Address */ +#define CSR_BADX(S) (*(uint32_t *) ((S)->aCSR + 30)) /**< Base Address of Transmit Descriptor */ +#define CSR_NXDA(S) (*(uint32_t *) ((S)->aCSR + 32)) /**< Next Transmit Descriptor Address */ +#define CSR_CXDA(S) (*(uint32_t *) ((S)->aCSR + 34)) /**< Current Transmit Descriptor Address */ +#define CSR_NNRD(S) (*(uint32_t *) ((S)->aCSR + 36)) /**< Next Next Receive Descriptor Address */ +#define CSR_NNXD(S) (*(uint32_t *) ((S)->aCSR + 38)) /**< Next Next Transmit Descriptor Address */ +#define CSR_CRBC(S) ((S)->aCSR[40]) /**< Current Receive Byte Count */ +#define CSR_CRST(S) ((S)->aCSR[41]) /**< Current Receive Status */ +#define CSR_CXBC(S) ((S)->aCSR[42]) /**< Current Transmit Byte Count */ +#define CSR_CXST(S) ((S)->aCSR[43]) /**< Current transmit status */ +#define CSR_NRBC(S) ((S)->aCSR[44]) /**< Next Receive Byte Count */ +#define CSR_NRST(S) ((S)->aCSR[45]) /**< Next Receive Status */ +#define CSR_POLL(S) ((S)->aCSR[46]) /**< Transmit Poll Time Counter */ +#define CSR_PINT(S) ((S)->aCSR[47]) /**< Transmit Polling Interval */ +#define CSR_PXDA(S) (*(uint32_t *) ((S)->aCSR + 60)) /**< Previous Transmit Descriptor Address*/ +#define CSR_PXBC(S) ((S)->aCSR[62]) /**< Previous Transmit Byte Count */ +#define CSR_PXST(S) ((S)->aCSR[63]) /**< Previous Transmit Status */ +#define CSR_NXBA(S) (*(uint32_t *) ((S)->aCSR + 64)) /**< Next Transmit Buffer Address */ +#define CSR_NXBC(S) ((S)->aCSR[66]) /**< Next Transmit Byte Count */ +#define CSR_NXST(S) ((S)->aCSR[67]) /**< Next Transmit Status */ +#define CSR_RCVRC(S) ((S)->aCSR[72]) /**< Receive Descriptor Ring Counter */ +#define CSR_XMTRC(S) ((S)->aCSR[74]) /**< Transmit Descriptor Ring Counter */ +#define CSR_RCVRL(S) ((S)->aCSR[76]) /**< Receive Descriptor Ring Length */ +#define CSR_XMTRL(S) ((S)->aCSR[78]) /**< Transmit Descriptor Ring Length */ +#define CSR_MISSC(S) ((S)->aCSR[112]) /**< Missed Frame Count */ /** Calculates the full physical address. */ -#define PHYSADDR(S,A) ((A) | (S)->GCUpperPhys) - +#define PHYSADDR(S, A) ((A) | (S)->GCUpperPhys) static const uint8_t am79c961_pnp_rom[] = { - 0x04, 0x96, 0x55, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, /* ADV55AA, dummy checksum (filled in by isapnp_add_card) */ - 0x0a, 0x10, 0x00, /* PnP version 1.0, vendor version 0.0 */ + 0x04, 0x96, 0x55, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, /* ADV55AA, dummy checksum (filled in by isapnp_add_card) */ + 0x0a, 0x10, 0x00, /* PnP version 1.0, vendor version 0.0 */ 0x82, 0x1c, 0x00, 'A', 'M', 'D', ' ', 'E', 't', 'h', 'e', 'r', 'n', 'e', 't', ' ', 'N', 'e', 't', 'w', 'o', 'r', 'k', ' ', 'A', 'd', 'a', 'p', 't', 'e', 'r', /* ANSI identifier */ - 0x16, 0x04, 0x96, 0x55, 0xaa, 0x00, 0xbd, /* logical device ADV55AA, supports vendor-specific registers 0x38/0x3A/0x3B/0x3C/0x3D/0x3F */ - 0x1c, 0x41, 0xd0, 0x82, 0x8c, /* compatible device PNP828C */ - 0x47, 0x00, 0x00, 0x02, 0xe0, 0x03, 0x20, 0x18, /* I/O 0x200-0x3E0, decodes 10-bit, 32-byte alignment, 24 addresses */ - 0x2a, 0xe8, 0x02, /* DMA 3/5/6/7, compatibility, no count by word, no count by byte, not bus master, 16-bit only */ - 0x23, 0x38, 0x9e, 0x09, /* IRQ 3/4/5/9/10/11/12/15, low true level sensitive, high true edge sensitive */ + 0x16, 0x04, 0x96, 0x55, 0xaa, 0x00, 0xbd, /* logical device ADV55AA, supports vendor-specific registers 0x38/0x3A/0x3B/0x3C/0x3D/0x3F */ + 0x1c, 0x41, 0xd0, 0x82, 0x8c, /* compatible device PNP828C */ + 0x47, 0x00, 0x00, 0x02, 0xe0, 0x03, 0x20, 0x18, /* I/O 0x200-0x3E0, decodes 10-bit, 32-byte alignment, 24 addresses */ + 0x2a, 0xe8, 0x02, /* DMA 3/5/6/7, compatibility, no count by word, no count by byte, not bus master, 16-bit only */ + 0x23, 0x38, 0x9e, 0x09, /* IRQ 3/4/5/9/10/11/12/15, low true level sensitive, high true edge sensitive */ 0x79, 0x00 /* end tag, dummy checksum (filled in by isapnp_add_card) */ }; - typedef struct { - mem_mapping_t mmio_mapping; - const char *name; - int board; - int is_pci, is_vlb, is_isa; - int PCIBase; - int MMIOBase; - uint32_t base_address; - int base_irq; - int dma_channel; - int card; /* PCI card slot */ - int xmit_pos; + mem_mapping_t mmio_mapping; + const char *name; + int board; + int is_pci, is_vlb, is_isa; + int PCIBase; + int MMIOBase; + uint32_t base_address; + int base_irq; + int dma_channel; + int card; /* PCI card slot */ + int xmit_pos; /** Register Address Pointer */ uint32_t u32RAP; /** Internal interrupt service */ - int32_t iISR; + int32_t iISR; /** ??? */ uint32_t u32Lnkst; /** Address of the RX descriptor table (ring). Loaded at init. */ @@ -239,7 +236,7 @@ typedef struct { /** The recv buffer. */ uint8_t abRecvBuf[4096]; /** Size of a RX/TX descriptor (8 or 16 bytes according to SWSTYLE */ - int iLog2DescSize; + int iLog2DescSize; /** Bits 16..23 in 16-bit mode */ uint32_t GCUpperPhys; /** We are waiting/about to start waiting for more receive buffers. */ @@ -258,17 +255,16 @@ typedef struct { /** Number of times we've reported the link down. */ uint32_t cLinkDownReported; /** MS to wait before we enable the link. */ - uint32_t cMsLinkUpDelay; - int transfer_size; - uint8_t maclocal[6]; /* configured MAC (local) address */ + uint32_t cMsLinkUpDelay; + int transfer_size; + uint8_t maclocal[6]; /* configured MAC (local) address */ pc_timer_t timer, timer_soft_int, timer_restore; netcard_t *netcard; } nic_t; /** @todo All structs: big endian? */ -struct INITBLK16 -{ +struct INITBLK16 { uint16_t mode; /**< copied into csr15 */ uint16_t padr1; /**< MAC 0..15 */ uint16_t padr2; /**< MAC 16..32 */ @@ -277,125 +273,121 @@ struct INITBLK16 uint16_t ladrf2; /**< logical address filter 16..31 */ uint16_t ladrf3; /**< logical address filter 32..47 */ uint16_t ladrf4; /**< logical address filter 48..63 */ - uint32_t rdra:24; /**< address of receive descriptor ring */ - uint32_t res1:5; /**< reserved */ - uint32_t rlen:3; /**< number of receive descriptor ring entries */ - uint32_t tdra:24; /**< address of transmit descriptor ring */ - uint32_t res2:5; /**< reserved */ - uint32_t tlen:3; /**< number of transmit descriptor ring entries */ + uint32_t rdra : 24; /**< address of receive descriptor ring */ + uint32_t res1 : 5; /**< reserved */ + uint32_t rlen : 3; /**< number of receive descriptor ring entries */ + uint32_t tdra : 24; /**< address of transmit descriptor ring */ + uint32_t res2 : 5; /**< reserved */ + uint32_t tlen : 3; /**< number of transmit descriptor ring entries */ }; /** bird: I've changed the type for the bitfields. They should only be 16-bit all together. * frank: I've changed the bitfiled types to uint32_t to prevent compiler warnings. */ -struct INITBLK32 -{ - uint16_t mode; /**< copied into csr15 */ - uint16_t res1:4; /**< reserved */ - uint16_t rlen:4; /**< number of receive descriptor ring entries */ - uint16_t res2:4; /**< reserved */ - uint16_t tlen:4; /**< number of transmit descriptor ring entries */ - uint16_t padr1; /**< MAC 0..15 */ - uint16_t padr2; /**< MAC 16..31 */ - uint16_t padr3; /**< MAC 32..47 */ - uint16_t res3; /**< reserved */ - uint16_t ladrf1; /**< logical address filter 0..15 */ - uint16_t ladrf2; /**< logical address filter 16..31 */ - uint16_t ladrf3; /**< logical address filter 32..47 */ - uint16_t ladrf4; /**< logical address filter 48..63 */ - uint32_t rdra; /**< address of receive descriptor ring */ - uint32_t tdra; /**< address of transmit descriptor ring */ +struct INITBLK32 { + uint16_t mode; /**< copied into csr15 */ + uint16_t res1 : 4; /**< reserved */ + uint16_t rlen : 4; /**< number of receive descriptor ring entries */ + uint16_t res2 : 4; /**< reserved */ + uint16_t tlen : 4; /**< number of transmit descriptor ring entries */ + uint16_t padr1; /**< MAC 0..15 */ + uint16_t padr2; /**< MAC 16..31 */ + uint16_t padr3; /**< MAC 32..47 */ + uint16_t res3; /**< reserved */ + uint16_t ladrf1; /**< logical address filter 0..15 */ + uint16_t ladrf2; /**< logical address filter 16..31 */ + uint16_t ladrf3; /**< logical address filter 32..47 */ + uint16_t ladrf4; /**< logical address filter 48..63 */ + uint32_t rdra; /**< address of receive descriptor ring */ + uint32_t tdra; /**< address of transmit descriptor ring */ }; /** Transmit Message Descriptor */ -typedef struct TMD -{ +typedef struct TMD { struct { - uint32_t tbadr; /**< transmit buffer address */ + uint32_t tbadr; /**< transmit buffer address */ } tmd0; struct { - uint32_t bcnt:12; /**< buffer byte count (two's complement) */ - uint32_t ones:4; /**< must be 1111b */ - uint32_t res:7; /**< reserved */ - uint32_t bpe:1; /**< bus parity error */ - uint32_t enp:1; /**< end of packet */ - uint32_t stp:1; /**< start of packet */ - uint32_t def:1; /**< deferred */ - uint32_t one:1; /**< exactly one retry was needed to transmit a frame */ - uint32_t ltint:1; /**< suppress interrupts after successful transmission */ - uint32_t nofcs:1; /**< when set, the state of DXMTFCS is ignored and - transmitter FCS generation is activated. */ - uint32_t err:1; /**< error occurred */ - uint32_t own:1; /**< 0=owned by guest driver, 1=owned by controller */ + uint32_t bcnt : 12; /**< buffer byte count (two's complement) */ + uint32_t ones : 4; /**< must be 1111b */ + uint32_t res : 7; /**< reserved */ + uint32_t bpe : 1; /**< bus parity error */ + uint32_t enp : 1; /**< end of packet */ + uint32_t stp : 1; /**< start of packet */ + uint32_t def : 1; /**< deferred */ + uint32_t one : 1; /**< exactly one retry was needed to transmit a frame */ + uint32_t ltint : 1; /**< suppress interrupts after successful transmission */ + uint32_t nofcs : 1; /**< when set, the state of DXMTFCS is ignored and + transmitter FCS generation is activated. */ + uint32_t err : 1; /**< error occurred */ + uint32_t own : 1; /**< 0=owned by guest driver, 1=owned by controller */ } tmd1; struct { - uint32_t trc:4; /**< transmit retry count */ - uint32_t res:12; /**< reserved */ - uint32_t tdr:10; /**< ??? */ - uint32_t rtry:1; /**< retry error */ - uint32_t lcar:1; /**< loss of carrier */ - uint32_t lcol:1; /**< late collision */ - uint32_t exdef:1; /**< excessive deferral */ - uint32_t uflo:1; /**< underflow error */ - uint32_t buff:1; /**< out of buffers (ENP not found) */ + uint32_t trc : 4; /**< transmit retry count */ + uint32_t res : 12; /**< reserved */ + uint32_t tdr : 10; /**< ??? */ + uint32_t rtry : 1; /**< retry error */ + uint32_t lcar : 1; /**< loss of carrier */ + uint32_t lcol : 1; /**< late collision */ + uint32_t exdef : 1; /**< excessive deferral */ + uint32_t uflo : 1; /**< underflow error */ + uint32_t buff : 1; /**< out of buffers (ENP not found) */ } tmd2; struct { - uint32_t res; /**< reserved for user defined space */ + uint32_t res; /**< reserved for user defined space */ } tmd3; } TMD; /** Receive Message Descriptor */ -typedef struct RMD -{ +typedef struct RMD { struct { - uint32_t rbadr; /**< receive buffer address */ + uint32_t rbadr; /**< receive buffer address */ } rmd0; struct { - uint32_t bcnt:12; /**< buffer byte count (two's complement) */ - uint32_t ones:4; /**< must be 1111b */ - uint32_t res:4; /**< reserved */ - uint32_t bam:1; /**< broadcast address match */ - uint32_t lafm:1; /**< logical filter address match */ - uint32_t pam:1; /**< physical address match */ - uint32_t bpe:1; /**< bus parity error */ - uint32_t enp:1; /**< end of packet */ - uint32_t stp:1; /**< start of packet */ - uint32_t buff:1; /**< buffer error */ - uint32_t crc:1; /**< crc error on incoming frame */ - uint32_t oflo:1; /**< overflow error (lost all or part of incoming frame) */ - uint32_t fram:1; /**< frame error */ - uint32_t err:1; /**< error occurred */ - uint32_t own:1; /**< 0=owned by guest driver, 1=owned by controller */ + uint32_t bcnt : 12; /**< buffer byte count (two's complement) */ + uint32_t ones : 4; /**< must be 1111b */ + uint32_t res : 4; /**< reserved */ + uint32_t bam : 1; /**< broadcast address match */ + uint32_t lafm : 1; /**< logical filter address match */ + uint32_t pam : 1; /**< physical address match */ + uint32_t bpe : 1; /**< bus parity error */ + uint32_t enp : 1; /**< end of packet */ + uint32_t stp : 1; /**< start of packet */ + uint32_t buff : 1; /**< buffer error */ + uint32_t crc : 1; /**< crc error on incoming frame */ + uint32_t oflo : 1; /**< overflow error (lost all or part of incoming frame) */ + uint32_t fram : 1; /**< frame error */ + uint32_t err : 1; /**< error occurred */ + uint32_t own : 1; /**< 0=owned by guest driver, 1=owned by controller */ } rmd1; struct { - uint32_t mcnt:12; /**< message byte count */ - uint32_t zeros:4; /**< 0000b */ - uint32_t rpc:8; /**< receive frame tag */ - uint32_t rcc:8; /**< receive frame tag + reserved */ + uint32_t mcnt : 12; /**< message byte count */ + uint32_t zeros : 4; /**< 0000b */ + uint32_t rpc : 8; /**< receive frame tag */ + uint32_t rcc : 8; /**< receive frame tag + reserved */ } rmd2; struct { - uint32_t res; /**< reserved for user defined space */ + uint32_t res; /**< reserved for user defined space */ } rmd3; } RMD; -static bar_t pcnet_pci_bar[3]; -static uint8_t pcnet_pci_regs[PCI_REGSIZE]; +static bar_t pcnet_pci_bar[3]; +static uint8_t pcnet_pci_regs[PCI_REGSIZE]; static void pcnetAsyncTransmit(nic_t *dev); static void pcnetPollRxTx(nic_t *dev); static void pcnetUpdateIrq(nic_t *dev); -static uint16_t pcnet_bcr_readw(nic_t *dev, uint16_t rap); -static void pcnet_bcr_writew(nic_t *dev, uint16_t rap, uint16_t val); -static void pcnet_csr_writew(nic_t *dev, uint16_t rap, uint16_t val); -static int pcnetCanReceive(nic_t *dev); - +static uint16_t pcnet_bcr_readw(nic_t *dev, uint16_t rap); +static void pcnet_bcr_writew(nic_t *dev, uint16_t rap, uint16_t val); +static void pcnet_csr_writew(nic_t *dev, uint16_t rap, uint16_t val); +static int pcnetCanReceive(nic_t *dev); #ifdef ENABLE_PCNET_LOG int pcnet_do_log = ENABLE_PCNET_LOG; @@ -406,30 +398,29 @@ pcnetlog(int lvl, const char *fmt, ...) va_list ap; if (pcnet_do_log >= lvl) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define pcnetlog(lvl, fmt, ...) +# define pcnetlog(lvl, fmt, ...) #endif - static void pcnet_do_irq(nic_t *dev, int issue) { - if (dev->is_pci) { - if (issue) - pci_set_irq(dev->card, PCI_INTA); - else - pci_clear_irq(dev->card, PCI_INTA); - } else { - if (issue) - picint(1<base_irq); - else - picintc(1<base_irq); - } + if (dev->is_pci) { + if (issue) + pci_set_irq(dev->card, PCI_INTA); + else + pci_clear_irq(dev->card, PCI_INTA); + } else { + if (issue) + picint(1 << dev->base_irq); + else + picintc(1 << dev->base_irq); + } } /** @@ -443,7 +434,6 @@ pcnetIsLinkUp(nic_t *dev) return !dev->fLinkTempDown && dev->fLinkUp; } - /** * Load transmit message descriptor * Make sure we read the own flag first. @@ -456,36 +446,36 @@ pcnetIsLinkUp(nic_t *dev) static __inline int pcnetTmdLoad(nic_t *dev, TMD *tmd, uint32_t addr, int fRetIfNotOwn) { - uint8_t ownbyte, bytes[4] = { 0, 0, 0, 0 }; + uint8_t ownbyte, bytes[4] = { 0, 0, 0, 0 }; uint16_t xda[4]; uint32_t xda32[4]; if (BCR_SWSTYLE(dev) == 0) { - dma_bm_read(addr, (uint8_t *) bytes, 4, dev->transfer_size); - ownbyte = bytes[3]; + dma_bm_read(addr, (uint8_t *) bytes, 4, dev->transfer_size); + ownbyte = bytes[3]; if (!(ownbyte & 0x80) && fRetIfNotOwn) return 0; - dma_bm_read(addr, (uint8_t*)&xda[0], sizeof(xda), dev->transfer_size); - ((uint32_t *)tmd)[0] = (uint32_t)xda[0] | ((uint32_t)(xda[1] & 0x00ff) << 16); - ((uint32_t *)tmd)[1] = (uint32_t)xda[2] | ((uint32_t)(xda[1] & 0xff00) << 16); - ((uint32_t *)tmd)[2] = (uint32_t)xda[3] << 16; - ((uint32_t *)tmd)[3] = 0; + dma_bm_read(addr, (uint8_t *) &xda[0], sizeof(xda), dev->transfer_size); + ((uint32_t *) tmd)[0] = (uint32_t) xda[0] | ((uint32_t) (xda[1] & 0x00ff) << 16); + ((uint32_t *) tmd)[1] = (uint32_t) xda[2] | ((uint32_t) (xda[1] & 0xff00) << 16); + ((uint32_t *) tmd)[2] = (uint32_t) xda[3] << 16; + ((uint32_t *) tmd)[3] = 0; } else if (BCR_SWSTYLE(dev) != 3) { - dma_bm_read(addr + 4, (uint8_t *) bytes, 4, dev->transfer_size); - ownbyte = bytes[3]; + dma_bm_read(addr + 4, (uint8_t *) bytes, 4, dev->transfer_size); + ownbyte = bytes[3]; if (!(ownbyte & 0x80) && fRetIfNotOwn) return 0; - dma_bm_read(addr, (uint8_t*)tmd, 16, dev->transfer_size); + dma_bm_read(addr, (uint8_t *) tmd, 16, dev->transfer_size); } else { - dma_bm_read(addr + 4, (uint8_t *) bytes, 4, dev->transfer_size); - ownbyte = bytes[3]; + dma_bm_read(addr + 4, (uint8_t *) bytes, 4, dev->transfer_size); + ownbyte = bytes[3]; if (!(ownbyte & 0x80) && fRetIfNotOwn) return 0; - dma_bm_read(addr, (uint8_t*)&xda32[0], sizeof(xda32), dev->transfer_size); - ((uint32_t *)tmd)[0] = xda32[2]; - ((uint32_t *)tmd)[1] = xda32[1]; - ((uint32_t *)tmd)[2] = xda32[0]; - ((uint32_t *)tmd)[3] = xda32[3]; + dma_bm_read(addr, (uint8_t *) &xda32[0], sizeof(xda32), dev->transfer_size); + ((uint32_t *) tmd)[0] = xda32[2]; + ((uint32_t *) tmd)[1] = xda32[1]; + ((uint32_t *) tmd)[2] = xda32[0]; + ((uint32_t *) tmd)[3] = xda32[3]; } /* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */ if (tmd->tmd1.own == 1 && !(ownbyte & 0x80)) @@ -496,7 +486,6 @@ pcnetTmdLoad(nic_t *dev, TMD *tmd, uint32_t addr, int fRetIfNotOwn) return !!tmd->tmd1.own; } - /** * Store transmit message descriptor and hand it over to the host (the VM guest). * Make sure that all data are transmitted before we clear the own flag. @@ -508,37 +497,36 @@ pcnetTmdStorePassHost(nic_t *dev, TMD *tmd, uint32_t addr) uint32_t xda32[3]; if (BCR_SWSTYLE(dev) == 0) { - xda[0] = ((uint32_t *)tmd)[0] & 0xffff; - xda[1] = ((((uint32_t *)tmd)[0] >> 16) & 0xff) | ((((uint32_t *)tmd)[1]>>16) & 0xff00); - xda[2] = ((uint32_t *)tmd)[1] & 0xffff; - xda[3] = ((uint32_t *)tmd)[2] >> 16; + xda[0] = ((uint32_t *) tmd)[0] & 0xffff; + xda[1] = ((((uint32_t *) tmd)[0] >> 16) & 0xff) | ((((uint32_t *) tmd)[1] >> 16) & 0xff00); + xda[2] = ((uint32_t *) tmd)[1] & 0xffff; + xda[3] = ((uint32_t *) tmd)[2] >> 16; #if 0 xda[1] |= 0x8000; dma_bm_write(addr, (uint8_t*)&xda[0], sizeof(xda), dev->transfer_size); #endif xda[1] &= ~0x8000; - dma_bm_write(addr, (uint8_t*)&xda[0], sizeof(xda), dev->transfer_size); + dma_bm_write(addr, (uint8_t *) &xda[0], sizeof(xda), dev->transfer_size); } else if (BCR_SWSTYLE(dev) != 3) { #if 0 ((uint32_t*)tmd)[1] |= 0x80000000; dma_bm_write(addr, (uint8_t*)tmd, 12, dev->transfer_size); #endif - ((uint32_t*)tmd)[1] &= ~0x80000000; - dma_bm_write(addr, (uint8_t*)tmd, 12, dev->transfer_size); + ((uint32_t *) tmd)[1] &= ~0x80000000; + dma_bm_write(addr, (uint8_t *) tmd, 12, dev->transfer_size); } else { - xda32[0] = ((uint32_t *)tmd)[2]; - xda32[1] = ((uint32_t *)tmd)[1]; - xda32[2] = ((uint32_t *)tmd)[0]; + xda32[0] = ((uint32_t *) tmd)[2]; + xda32[1] = ((uint32_t *) tmd)[1]; + xda32[2] = ((uint32_t *) tmd)[0]; #if 0 xda32[1] |= 0x80000000; dma_bm_write(addr, (uint8_t*)&xda32[0], sizeof(xda32), dev->transfer_size); #endif xda32[1] &= ~0x80000000; - dma_bm_write(addr, (uint8_t*)&xda32[0], sizeof(xda32), dev->transfer_size); + dma_bm_write(addr, (uint8_t *) &xda32[0], sizeof(xda32), dev->transfer_size); } } - /** * Load receive message descriptor * Make sure we read the own flag first. @@ -551,36 +539,36 @@ pcnetTmdStorePassHost(nic_t *dev, TMD *tmd, uint32_t addr) static __inline int pcnetRmdLoad(nic_t *dev, RMD *rmd, uint32_t addr, int fRetIfNotOwn) { - uint8_t ownbyte, bytes[4] = { 0, 0, 0, 0 }; + uint8_t ownbyte, bytes[4] = { 0, 0, 0, 0 }; uint16_t rda[4]; uint32_t rda32[4]; if (BCR_SWSTYLE(dev) == 0) { dma_bm_read(addr, (uint8_t *) bytes, 4, dev->transfer_size); - ownbyte = bytes[3]; + ownbyte = bytes[3]; if (!(ownbyte & 0x80) && fRetIfNotOwn) return 0; - dma_bm_read(addr, (uint8_t*)&rda[0], sizeof(rda), dev->transfer_size); - ((uint32_t *)rmd)[0] = (uint32_t)rda[0] | ((rda[1] & 0x00ff) << 16); - ((uint32_t *)rmd)[1] = (uint32_t)rda[2] | ((rda[1] & 0xff00) << 16); - ((uint32_t *)rmd)[2] = (uint32_t)rda[3]; - ((uint32_t *)rmd)[3] = 0; + dma_bm_read(addr, (uint8_t *) &rda[0], sizeof(rda), dev->transfer_size); + ((uint32_t *) rmd)[0] = (uint32_t) rda[0] | ((rda[1] & 0x00ff) << 16); + ((uint32_t *) rmd)[1] = (uint32_t) rda[2] | ((rda[1] & 0xff00) << 16); + ((uint32_t *) rmd)[2] = (uint32_t) rda[3]; + ((uint32_t *) rmd)[3] = 0; } else if (BCR_SWSTYLE(dev) != 3) { dma_bm_read(addr + 4, (uint8_t *) bytes, 4, dev->transfer_size); - ownbyte = bytes[3]; + ownbyte = bytes[3]; if (!(ownbyte & 0x80) && fRetIfNotOwn) return 0; - dma_bm_read(addr, (uint8_t*)rmd, 16, dev->transfer_size); + dma_bm_read(addr, (uint8_t *) rmd, 16, dev->transfer_size); } else { dma_bm_read(addr + 4, (uint8_t *) bytes, 4, dev->transfer_size); - ownbyte = bytes[3]; + ownbyte = bytes[3]; if (!(ownbyte & 0x80) && fRetIfNotOwn) return 0; - dma_bm_read(addr, (uint8_t*)&rda32[0], sizeof(rda32), dev->transfer_size); - ((uint32_t *)rmd)[0] = rda32[2]; - ((uint32_t *)rmd)[1] = rda32[1]; - ((uint32_t *)rmd)[2] = rda32[0]; - ((uint32_t *)rmd)[3] = rda32[3]; + dma_bm_read(addr, (uint8_t *) &rda32[0], sizeof(rda32), dev->transfer_size); + ((uint32_t *) rmd)[0] = rda32[2]; + ((uint32_t *) rmd)[1] = rda32[1]; + ((uint32_t *) rmd)[2] = rda32[0]; + ((uint32_t *) rmd)[3] = rda32[3]; } /* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */ if (rmd->rmd1.own == 1 && !(ownbyte & 0x80)) @@ -592,7 +580,6 @@ pcnetRmdLoad(nic_t *dev, RMD *rmd, uint32_t addr, int fRetIfNotOwn) return !!rmd->rmd1.own; } - /** * Store receive message descriptor and hand it over to the host (the VM guest). * Make sure that all data are transmitted before we clear the own flag. @@ -604,52 +591,51 @@ pcnetRmdStorePassHost(nic_t *dev, RMD *rmd, uint32_t addr) uint32_t rda32[3]; if (BCR_SWSTYLE(dev) == 0) { - rda[0] = ((uint32_t *)rmd)[0] & 0xffff; - rda[1] = ((((uint32_t *)rmd)[0]>>16) & 0xff) | ((((uint32_t *)rmd)[1]>>16) & 0xff00); - rda[2] = ((uint32_t *)rmd)[1] & 0xffff; - rda[3] = ((uint32_t *)rmd)[2] & 0xffff; + rda[0] = ((uint32_t *) rmd)[0] & 0xffff; + rda[1] = ((((uint32_t *) rmd)[0] >> 16) & 0xff) | ((((uint32_t *) rmd)[1] >> 16) & 0xff00); + rda[2] = ((uint32_t *) rmd)[1] & 0xffff; + rda[3] = ((uint32_t *) rmd)[2] & 0xffff; #if 0 rda[1] |= 0x8000; dma_bm_write(addr, (uint8_t*)&rda[0], sizeof(rda), dev->transfer_size); #endif rda[1] &= ~0x8000; - dma_bm_write(addr, (uint8_t*)&rda[0], sizeof(rda), dev->transfer_size); + dma_bm_write(addr, (uint8_t *) &rda[0], sizeof(rda), dev->transfer_size); } else if (BCR_SWSTYLE(dev) != 3) { #if 0 ((uint32_t*)rmd)[1] |= 0x80000000; dma_bm_write(addr, (uint8_t*)rmd, 12, dev->transfer_size); #endif - ((uint32_t*)rmd)[1] &= ~0x80000000; - dma_bm_write(addr, (uint8_t*)rmd, 12, dev->transfer_size); + ((uint32_t *) rmd)[1] &= ~0x80000000; + dma_bm_write(addr, (uint8_t *) rmd, 12, dev->transfer_size); } else { - rda32[0] = ((uint32_t *)rmd)[2]; - rda32[1] = ((uint32_t *)rmd)[1]; - rda32[2] = ((uint32_t *)rmd)[0]; + rda32[0] = ((uint32_t *) rmd)[2]; + rda32[1] = ((uint32_t *) rmd)[1]; + rda32[2] = ((uint32_t *) rmd)[0]; #if 0 rda32[1] |= 0x80000000; dma_bm_write(addr, (uint8_t*)&rda32[0], sizeof(rda32), dev->transfer_size); #endif rda32[1] &= ~0x80000000; - dma_bm_write(addr, (uint8_t*)&rda32[0], sizeof(rda32), dev->transfer_size); + dma_bm_write(addr, (uint8_t *) &rda32[0], sizeof(rda32), dev->transfer_size); } } - /** Checks if it's a bad (as in invalid) RMD.*/ -#define IS_RMD_BAD(rmd) ((rmd).rmd1.ones != 15) +#define IS_RMD_BAD(rmd) ((rmd).rmd1.ones != 15) /** The network card is the owner of the RDTE/TDTE, actually it is this driver */ -#define CARD_IS_OWNER(desc) (((desc) & 0x8000)) +#define CARD_IS_OWNER(desc) (((desc) &0x8000)) /** The host is the owner of the RDTE/TDTE -- actually the VM guest. */ -#define HOST_IS_OWNER(desc) (!((desc) & 0x8000)) +#define HOST_IS_OWNER(desc) (!((desc) &0x8000)) #ifndef ETHER_IS_MULTICAST /* Net/Open BSD macro it seems */ -#define ETHER_IS_MULTICAST(a) ((*(uint8_t *)(a)) & 1) +# define ETHER_IS_MULTICAST(a) ((*(uint8_t *) (a)) & 1) #endif #define ETHER_ADDR_LEN ETH_ALEN -#define ETH_ALEN 6 +#define ETH_ALEN 6 #pragma pack(1) struct ether_header /** @todo Use RTNETETHERHDR */ { @@ -659,22 +645,20 @@ struct ether_header /** @todo Use RTNETETHERHDR */ }; #pragma pack() -#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff]) +#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff]) #define MULTICAST_FILTER_LEN 8 static __inline uint32_t lnc_mchash(const uint8_t *ether_addr) { -#define LNC_POLYNOMIAL 0xEDB88320UL +#define LNC_POLYNOMIAL 0xEDB88320UL uint32_t crc = 0xFFFFFFFF; - int idx, bit; - uint8_t data; + int idx, bit; + uint8_t data; - for (idx = 0; idx < ETHER_ADDR_LEN; idx++) - { - for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++) - { + for (idx = 0; idx < ETHER_ADDR_LEN; idx++) { + for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++) { crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0); data >>= 1; } @@ -683,7 +667,7 @@ lnc_mchash(const uint8_t *ether_addr) #undef LNC_POLYNOMIAL } -#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff]) +#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff]) /* generated using the AUTODIN II polynomial * x^32 + x^26 + x^23 + x^22 + x^16 + @@ -757,48 +741,46 @@ static const uint32_t crctab[256] = 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d, }; - static __inline int padr_match(nic_t *dev, const uint8_t *buf, int size) { - struct ether_header *hdr = (struct ether_header *)buf; - int result; - uint8_t padr[6]; + struct ether_header *hdr = (struct ether_header *) buf; + int result; + uint8_t padr[6]; padr[0] = dev->aCSR[12] & 0xff; padr[1] = dev->aCSR[12] >> 8; padr[2] = dev->aCSR[13] & 0xff; padr[3] = dev->aCSR[13] >> 8; padr[4] = dev->aCSR[14] & 0xff; padr[5] = dev->aCSR[14] >> 8; - result = !CSR_DRCVPA(dev) && !memcmp(hdr->ether_dhost, padr, 6); + result = !CSR_DRCVPA(dev) && !memcmp(hdr->ether_dhost, padr, 6); pcnetlog(3, "%s: packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, " - "padr=%02x:%02x:%02x:%02x:%02x:%02x => %d\n", dev->name, - hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], - hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], - padr[0],padr[1],padr[2],padr[3],padr[4],padr[5], result); + "padr=%02x:%02x:%02x:%02x:%02x:%02x => %d\n", + dev->name, + hdr->ether_dhost[0], hdr->ether_dhost[1], hdr->ether_dhost[2], + hdr->ether_dhost[3], hdr->ether_dhost[4], hdr->ether_dhost[5], + padr[0], padr[1], padr[2], padr[3], padr[4], padr[5], result); return result; } - static __inline int padr_bcast(nic_t *dev, const uint8_t *buf, size_t size) { - static uint8_t aBCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; - struct ether_header *hdr = (struct ether_header *)buf; - int result = !CSR_DRCVBC(dev) && !memcmp(hdr->ether_dhost, aBCAST, 6); + static uint8_t aBCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + struct ether_header *hdr = (struct ether_header *) buf; + int result = !CSR_DRCVBC(dev) && !memcmp(hdr->ether_dhost, aBCAST, 6); pcnetlog(3, "%s: padr_bcast result=%d\n", dev->name, result); - return result; + return result; } - static int ladr_match(nic_t *dev, const uint8_t *buf, size_t size) { - struct ether_header *hdr = (struct ether_header *)buf; - if ((hdr->ether_dhost[0] & 0x01) && ((uint64_t *)&dev->aCSR[8])[0] != 0LL) { - int index; + struct ether_header *hdr = (struct ether_header *) buf; + if ((hdr->ether_dhost[0] & 0x01) && ((uint64_t *) &dev->aCSR[8])[0] != 0LL) { + int index; uint8_t ladr[8]; ladr[0] = dev->aCSR[8] & 0xff; ladr[1] = dev->aCSR[8] >> 8; @@ -808,13 +790,12 @@ ladr_match(nic_t *dev, const uint8_t *buf, size_t size) ladr[5] = dev->aCSR[10] >> 8; ladr[6] = dev->aCSR[11] & 0xff; ladr[7] = dev->aCSR[11] >> 8; - index = lnc_mchash(hdr->ether_dhost) >> 26; + index = lnc_mchash(hdr->ether_dhost) >> 26; return (ladr[index >> 3] & (1 << (index & 7))); - } + } return 0; } - /** * Get the receive descriptor ring address with a given index. */ @@ -824,7 +805,6 @@ pcnetRdraAddr(nic_t *dev, int idx) return dev->GCRDRA + ((CSR_RCVRL(dev) - idx) << dev->iLog2DescSize); } - /** * Get the transmit descriptor ring address with a given index. */ @@ -834,7 +814,6 @@ pcnetTdraAddr(nic_t *dev, int idx) return dev->GCTDRA + ((CSR_XMTRL(dev) - idx) << dev->iLog2DescSize); } - static void pcnetSoftReset(nic_t *dev) { @@ -845,18 +824,18 @@ pcnetSoftReset(nic_t *dev) dev->GCTDRA = 0; dev->u32RAP = 0; - dev->aCSR[0] = 0x0004; - dev->aCSR[3] = 0x0000; - dev->aCSR[4] = 0x0115; - dev->aCSR[5] = 0x0000; - dev->aCSR[6] = 0x0000; - dev->aCSR[8] = 0; - dev->aCSR[9] = 0; - dev->aCSR[10] = 0; - dev->aCSR[11] = 0; - dev->aCSR[12] = le16_to_cpu(((uint16_t *)&dev->aPROM[0])[0]); - dev->aCSR[13] = le16_to_cpu(((uint16_t *)&dev->aPROM[0])[1]); - dev->aCSR[14] = le16_to_cpu(((uint16_t *)&dev->aPROM[0])[2]); + dev->aCSR[0] = 0x0004; + dev->aCSR[3] = 0x0000; + dev->aCSR[4] = 0x0115; + dev->aCSR[5] = 0x0000; + dev->aCSR[6] = 0x0000; + dev->aCSR[8] = 0; + dev->aCSR[9] = 0; + dev->aCSR[10] = 0; + dev->aCSR[11] = 0; + dev->aCSR[12] = le16_to_cpu(((uint16_t *) &dev->aPROM[0])[0]); + dev->aCSR[13] = le16_to_cpu(((uint16_t *) &dev->aPROM[0])[1]); + dev->aCSR[14] = le16_to_cpu(((uint16_t *) &dev->aPROM[0])[2]); dev->aCSR[15] &= 0x21c4; CSR_RCVRC(dev) = 1; CSR_XMTRC(dev) = 1; @@ -865,21 +844,21 @@ pcnetSoftReset(nic_t *dev) dev->aCSR[80] = 0x1410; switch (dev->board) { - case DEV_AM79C970A: - dev->aCSR[88] = 0x1003; - dev->aCSR[89] = 0x0262; - break; - case DEV_AM79C973: - dev->aCSR[88] = 0x5003; - dev->aCSR[89] = 0x0262; - break; - case DEV_AM79C960: - case DEV_AM79C960_EB: - case DEV_AM79C960_VLB: - case DEV_AM79C961: - dev->aCSR[88] = 0x3003; - dev->aCSR[89] = 0x0262; - break; + case DEV_AM79C970A: + dev->aCSR[88] = 0x1003; + dev->aCSR[89] = 0x0262; + break; + case DEV_AM79C973: + dev->aCSR[88] = 0x5003; + dev->aCSR[89] = 0x0262; + break; + case DEV_AM79C960: + case DEV_AM79C960_EB: + case DEV_AM79C960_VLB: + case DEV_AM79C961: + dev->aCSR[88] = 0x3003; + dev->aCSR[89] = 0x0262; + break; } dev->aCSR[94] = 0x0000; @@ -891,42 +870,39 @@ pcnetSoftReset(nic_t *dev) dev->aCSR[124] = 0x0000; } - static void pcnetUpdateIrq(nic_t *dev) { - int iISR = 0; + int iISR = 0; uint16_t csr0; csr0 = dev->aCSR[0]; csr0 &= ~0x0080; /* clear INTR */ - if (((csr0 & ~dev->aCSR[3]) & 0x5f00) || - (((dev->aCSR[4]>>1) & ~dev->aCSR[4]) & 0x0115) || - (((dev->aCSR[5]>>1) & dev->aCSR[5]) & 0x0048)) { - iISR = !!(csr0 & 0x0040); /* CSR_INEA */ - csr0 |= 0x0080; /* set INTR */ + if (((csr0 & ~dev->aCSR[3]) & 0x5f00) || (((dev->aCSR[4] >> 1) & ~dev->aCSR[4]) & 0x0115) || (((dev->aCSR[5] >> 1) & dev->aCSR[5]) & 0x0048)) { + iISR = !!(csr0 & 0x0040); /* CSR_INEA */ + csr0 |= 0x0080; /* set INTR */ } if (dev->aCSR[4] & 0x0080) { /* UINTCMD */ - dev->aCSR[4] &= ~0x0080; /* clear UINTCMD */ - dev->aCSR[4] |= 0x0040; /* set UINT */ - pcnetlog(2, "%s: user int\n", dev->name); + dev->aCSR[4] &= ~0x0080; /* clear UINTCMD */ + dev->aCSR[4] |= 0x0040; /* set UINT */ + pcnetlog(2, "%s: user int\n", dev->name); } if (dev->aCSR[4] & csr0 & 0x0040 /* CSR_INEA */) { - csr0 |= 0x0080; /* set INTR */ - iISR = 1; + csr0 |= 0x0080; /* set INTR */ + iISR = 1; } - if (((dev->aCSR[5]>>1) & dev->aCSR[5]) & 0x0500) { - iISR = 1; - csr0 |= 0x0080; /* set INTR */ + if (((dev->aCSR[5] >> 1) & dev->aCSR[5]) & 0x0500) { + iISR = 1; + csr0 |= 0x0080; /* set INTR */ } if ((dev->aCSR[7] & 0x0c00) == 0x0c00) /* STINT + STINTE */ - iISR = 1; + iISR = 1; dev->aCSR[0] = csr0; @@ -936,7 +912,6 @@ pcnetUpdateIrq(nic_t *dev) dev->iISR = iISR; } - static void pcnetInit(nic_t *dev) { @@ -945,48 +920,49 @@ pcnetInit(nic_t *dev) /** @todo Documentation says that RCVRL and XMTRL are stored as two's complement! * Software is allowed to write these registers directly. */ -#define PCNET_INIT() do { \ - dma_bm_read(PHYSADDR(dev, CSR_IADR(dev)), \ - (uint8_t *)&initblk, sizeof(initblk), dev->transfer_size); \ - dev->aCSR[15] = le16_to_cpu(initblk.mode); \ - CSR_RCVRL(dev) = (initblk.rlen < 9) ? (1 << initblk.rlen) : 512; \ - CSR_XMTRL(dev) = (initblk.tlen < 9) ? (1 << initblk.tlen) : 512; \ - dev->aCSR[ 6] = (initblk.tlen << 12) | (initblk.rlen << 8); \ - dev->aCSR[ 8] = le16_to_cpu(initblk.ladrf1); \ - dev->aCSR[ 9] = le16_to_cpu(initblk.ladrf2); \ - dev->aCSR[10] = le16_to_cpu(initblk.ladrf3); \ - dev->aCSR[11] = le16_to_cpu(initblk.ladrf4); \ - dev->aCSR[12] = le16_to_cpu(initblk.padr1); \ - dev->aCSR[13] = le16_to_cpu(initblk.padr2); \ - dev->aCSR[14] = le16_to_cpu(initblk.padr3); \ - dev->GCRDRA = PHYSADDR(dev, initblk.rdra); \ - dev->GCTDRA = PHYSADDR(dev, initblk.tdra); \ -} while (0) +#define PCNET_INIT() \ + do { \ + dma_bm_read(PHYSADDR(dev, CSR_IADR(dev)), \ + (uint8_t *) &initblk, sizeof(initblk), dev->transfer_size); \ + dev->aCSR[15] = le16_to_cpu(initblk.mode); \ + CSR_RCVRL(dev) = (initblk.rlen < 9) ? (1 << initblk.rlen) : 512; \ + CSR_XMTRL(dev) = (initblk.tlen < 9) ? (1 << initblk.tlen) : 512; \ + dev->aCSR[6] = (initblk.tlen << 12) | (initblk.rlen << 8); \ + dev->aCSR[8] = le16_to_cpu(initblk.ladrf1); \ + dev->aCSR[9] = le16_to_cpu(initblk.ladrf2); \ + dev->aCSR[10] = le16_to_cpu(initblk.ladrf3); \ + dev->aCSR[11] = le16_to_cpu(initblk.ladrf4); \ + dev->aCSR[12] = le16_to_cpu(initblk.padr1); \ + dev->aCSR[13] = le16_to_cpu(initblk.padr2); \ + dev->aCSR[14] = le16_to_cpu(initblk.padr3); \ + dev->GCRDRA = PHYSADDR(dev, initblk.rdra); \ + dev->GCTDRA = PHYSADDR(dev, initblk.tdra); \ + } while (0) if (BCR_SSIZE32(dev)) { struct INITBLK32 initblk; dev->GCUpperPhys = 0; PCNET_INIT(); pcnetlog(3, "%s: initblk.rlen=%#04x, initblk.tlen=%#04x\n", - dev->name, initblk.rlen, initblk.tlen); + dev->name, initblk.rlen, initblk.tlen); } else { struct INITBLK16 initblk; - dev->GCUpperPhys = (0xff00 & (uint32_t)dev->aCSR[2]) << 16; + dev->GCUpperPhys = (0xff00 & (uint32_t) dev->aCSR[2]) << 16; PCNET_INIT(); pcnetlog(3, "%s: initblk.rlen=%#04x, initblk.tlen=%#04x\n", - dev->name, initblk.rlen, initblk.tlen); + dev->name, initblk.rlen, initblk.tlen); } #undef PCNET_INIT size_t cbRxBuffers = 0; for (i = CSR_RCVRL(dev); i >= 1; i--) { - RMD rmd; + RMD rmd; uint32_t rdaddr = PHYSADDR(dev, pcnetRdraAddr(dev, i)); /* At this time it is not guaranteed that the buffers are already initialized. */ if (pcnetRmdLoad(dev, &rmd, rdaddr, 0)) { - uint32_t cbBuf = 4096U-rmd.rmd1.bcnt; + uint32_t cbBuf = 4096U - rmd.rmd1.bcnt; cbRxBuffers += cbBuf; } } @@ -999,7 +975,7 @@ pcnetInit(nic_t *dev) * usually 1536 bytes and should therefore not run into condition. If they are still * short in RX buffers we notify this condition. */ - dev->fSignalRxMiss = (cbRxBuffers == 0 || cbRxBuffers >= 32*1024); + dev->fSignalRxMiss = (cbRxBuffers == 0 || cbRxBuffers >= 32 * 1024); CSR_RCVRC(dev) = CSR_RCVRL(dev); CSR_XMTRC(dev) = CSR_XMTRL(dev); @@ -1009,20 +985,19 @@ pcnetInit(nic_t *dev) CSR_CXST(dev) = CSR_CXBC(dev) = CSR_NXST(dev) = CSR_NXBC(dev) = 0; pcnetlog(1, "%s: Init: SWSTYLE=%d GCRDRA=%#010x[%d] GCTDRA=%#010x[%d]%s\n", - dev->name, BCR_SWSTYLE(dev), - dev->GCRDRA, CSR_RCVRL(dev), dev->GCTDRA, CSR_XMTRL(dev), - !dev->fSignalRxMiss ? " (CSR0_MISS disabled)" : ""); + dev->name, BCR_SWSTYLE(dev), + dev->GCRDRA, CSR_RCVRL(dev), dev->GCTDRA, CSR_XMTRL(dev), + !dev->fSignalRxMiss ? " (CSR0_MISS disabled)" : ""); if (dev->GCRDRA & (dev->iLog2DescSize - 1)) pcnetlog(1, "%s: Warning: Misaligned RDRA\n", dev->name); if (dev->GCTDRA & (dev->iLog2DescSize - 1)) pcnetlog(1, "%s: Warning: Misaligned TDRA\n", dev->name); - dev->aCSR[0] |= 0x0101; /* Initialization done */ - dev->aCSR[0] &= ~0x0004; /* clear STOP bit */ + dev->aCSR[0] |= 0x0101; /* Initialization done */ + dev->aCSR[0] &= ~0x0004; /* clear STOP bit */ } - /** * Start RX/TX operation. */ @@ -1036,15 +1011,14 @@ pcnetStart(nic_t *dev) CSR_CRBC(dev) = CSR_NRBC(dev) = CSR_CRST(dev) = 0; if (!CSR_DTX(dev)) - dev->aCSR[0] |= 0x0010; /* set TXON */ + dev->aCSR[0] |= 0x0010; /* set TXON */ if (!CSR_DRX(dev)) - dev->aCSR[0] |= 0x0020; /* set RXON */ - dev->aCSR[0] &= ~0x0004; /* clear STOP bit */ - dev->aCSR[0] |= 0x0002; /* STRT */ + dev->aCSR[0] |= 0x0020; /* set RXON */ + dev->aCSR[0] &= ~0x0004; /* clear STOP bit */ + dev->aCSR[0] |= 0x0002; /* STRT */ timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC); } - /** * Stop RX/TX operation. */ @@ -1058,7 +1032,6 @@ pcnetStop(nic_t *dev) timer_disable(&dev->timer); } - /** * Poll Receive Descriptor Table Entry and cache the results in the appropriate registers. * Note: Once a descriptor belongs to the network card (this driver), it cannot be changed @@ -1075,49 +1048,49 @@ pcnetRdtePoll(nic_t *dev) /* * The current receive message descriptor. */ - RMD rmd; - int i = CSR_RCVRC(dev); - uint32_t addr; + RMD rmd; + int i = CSR_RCVRC(dev); + uint32_t addr; if (i < 1) i = CSR_RCVRL(dev); - addr = pcnetRdraAddr(dev, i); - CSR_CRDA(dev) = CSR_CRBA(dev) = 0; - CSR_CRBC(dev) = CSR_CRST(dev) = 0; - if (!pcnetRmdLoad(dev, &rmd, PHYSADDR(dev, addr), 1)) - return; - if (!IS_RMD_BAD(rmd)) { - CSR_CRDA(dev) = addr; /* Receive Descriptor Address */ - CSR_CRBA(dev) = rmd.rmd0.rbadr; /* Receive Buffer Address */ - CSR_CRBC(dev) = rmd.rmd1.bcnt; /* Receive Byte Count */ - CSR_CRST(dev) = ((uint32_t *)&rmd)[1] >> 16; /* Receive Status */ - } else { - /* This is not problematic since we don't own the descriptor - * We actually do own it, otherwise pcnetRmdLoad would have returned false. - * Don't flood the release log with errors. - */ - if (++dev->uCntBadRMD < 50) - pcnetlog(1, "%s: BAD RMD ENTRIES AT %#010x (i=%d)\n", - dev->name, addr, i); - return; - } + addr = pcnetRdraAddr(dev, i); + CSR_CRDA(dev) = CSR_CRBA(dev) = 0; + CSR_CRBC(dev) = CSR_CRST(dev) = 0; + if (!pcnetRmdLoad(dev, &rmd, PHYSADDR(dev, addr), 1)) + return; + if (!IS_RMD_BAD(rmd)) { + CSR_CRDA(dev) = addr; /* Receive Descriptor Address */ + CSR_CRBA(dev) = rmd.rmd0.rbadr; /* Receive Buffer Address */ + CSR_CRBC(dev) = rmd.rmd1.bcnt; /* Receive Byte Count */ + CSR_CRST(dev) = ((uint32_t *) &rmd)[1] >> 16; /* Receive Status */ + } else { + /* This is not problematic since we don't own the descriptor + * We actually do own it, otherwise pcnetRmdLoad would have returned false. + * Don't flood the release log with errors. + */ + if (++dev->uCntBadRMD < 50) + pcnetlog(1, "%s: BAD RMD ENTRIES AT %#010x (i=%d)\n", + dev->name, addr, i); + return; + } /* * The next descriptor. */ if (--i < 1) i = CSR_RCVRL(dev); - addr = pcnetRdraAddr(dev, i); + addr = pcnetRdraAddr(dev, i); CSR_NRDA(dev) = CSR_NRBA(dev) = 0; - CSR_NRBC(dev) = 0; + CSR_NRBC(dev) = 0; if (!pcnetRmdLoad(dev, &rmd, PHYSADDR(dev, addr), 1)) return; if (!IS_RMD_BAD(rmd)) { CSR_NRDA(dev) = addr; /* Receive Descriptor Address */ CSR_NRBA(dev) = rmd.rmd0.rbadr; /* Receive Buffer Address */ CSR_NRBC(dev) = rmd.rmd1.bcnt; /* Receive Byte Count */ - CSR_NRST(dev) = ((uint32_t *)&rmd)[1] >> 16; /* Receive Status */ + CSR_NRST(dev) = ((uint32_t *) &rmd)[1] >> 16; /* Receive Status */ } else { /* This is not problematic since we don't own the descriptor * We actually do own it, otherwise pcnetRmdLoad would have returned false. @@ -1125,7 +1098,7 @@ pcnetRdtePoll(nic_t *dev) */ if (++dev->uCntBadRMD < 50) pcnetlog(1, "%s: BAD RMD ENTRIES + AT %#010x (i=%d)\n", - dev->name, addr, i); + dev->name, addr, i); return; } @@ -1138,7 +1111,6 @@ pcnetRdtePoll(nic_t *dev) } } - /** * Poll Transmit Descriptor Table Entry * @return true if transmit descriptors available @@ -1154,7 +1126,7 @@ pcnetTdtePoll(nic_t *dev, TMD *tmd) if (tmd->tmd1.ones != 15) { pcnetlog(1, "%s: BAD TMD XDA=%#010x\n", - dev->name, PHYSADDR(dev, cxda)); + dev->name, PHYSADDR(dev, cxda)); return 0; } @@ -1166,7 +1138,7 @@ pcnetTdtePoll(nic_t *dev, TMD *tmd) /* set current transmit descriptor. */ CSR_CXDA(dev) = cxda; CSR_CXBC(dev) = tmd->tmd1.bcnt; - CSR_CXST(dev) = ((uint32_t *)tmd)[1] >> 16; + CSR_CXST(dev) = ((uint32_t *) tmd)[1] >> 16; return CARD_IS_OWNER(CSR_CXST(dev)); } else { /** @todo consistency with previous receive descriptor */ @@ -1176,7 +1148,6 @@ pcnetTdtePoll(nic_t *dev, TMD *tmd) } } - /** * Poll Transmit Descriptor Table Entry * @return true if transmit descriptors available @@ -1184,13 +1155,12 @@ pcnetTdtePoll(nic_t *dev, TMD *tmd) static int pcnetCalcPacketLen(nic_t *dev, int cb) { - TMD tmd; - int cbPacket = cb; - uint32_t iDesc = CSR_XMTRC(dev); + TMD tmd; + int cbPacket = cb; + uint32_t iDesc = CSR_XMTRC(dev); uint32_t iFirstDesc = iDesc; - do - { + do { /* Advance the ring counter */ if (iDesc < 2) iDesc = CSR_XMTRL(dev); @@ -1212,7 +1182,7 @@ pcnetCalcPacketLen(nic_t *dev, int cb) } if (tmd.tmd1.ones != 15) { pcnetlog(1, "%s: BAD TMD XDA=%#010x\n", - dev->name, PHYSADDR(dev, addrDesc)); + dev->name, PHYSADDR(dev, addrDesc)); pcnetlog(3, "%s: pcnetCalcPacketLen: bad TMD, return %u\n", dev->name, cbPacket); return cbPacket; } @@ -1224,27 +1194,26 @@ pcnetCalcPacketLen(nic_t *dev, int cb) return cbPacket; } - /** * Write data into guest receive buffers. */ static int pcnetReceiveNoSync(void *priv, uint8_t *buf, int size) { - nic_t *dev = (nic_t *)priv; - int is_padr = 0, is_bcast = 0, is_ladr = 0; + nic_t *dev = (nic_t *) priv; + int is_padr = 0, is_bcast = 0, is_ladr = 0; uint32_t iRxDesc; - int cbPacket; - uint8_t buf1[60]; + int cbPacket; + uint8_t buf1[60]; if (CSR_DRX(dev) || CSR_STOP(dev) || CSR_SPND(dev) || !size) - return 0; + return 0; /* if too small buffer, then expand it */ if (size < 60) { memcpy(buf1, buf, size); memset(buf1 + size, 0, 60 - size); - buf = buf1; + buf = buf1; size = 60; } @@ -1252,34 +1221,34 @@ pcnetReceiveNoSync(void *priv, uint8_t *buf, int size) * Drop packets if the cable is not connected */ if (!pcnetIsLinkUp(dev)) - return 0; + return 0; dev->fMaybeOutOfSpace = !pcnetCanReceive(dev); if (dev->fMaybeOutOfSpace) return 0; pcnetlog(1, "%s: pcnetReceiveNoSync: RX %x:%x:%x:%x:%x:%x > %x:%x:%x:%x:%x:%x len %d\n", dev->name, - buf[6], buf[7], buf[8], buf[9], buf[10], buf[11], - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], - size); + buf[6], buf[7], buf[8], buf[9], buf[10], buf[11], + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], + size); /* * Perform address matching. */ if (CSR_PROM(dev) - || (is_padr = padr_match(dev, buf, size)) + || (is_padr = padr_match(dev, buf, size)) || (is_bcast = padr_bcast(dev, buf, size)) - || (is_ladr = ladr_match(dev, buf, size))) { + || (is_ladr = ladr_match(dev, buf, size))) { - if (HOST_IS_OWNER(CSR_CRST(dev))) - pcnetRdtePoll(dev); + if (HOST_IS_OWNER(CSR_CRST(dev))) + pcnetRdtePoll(dev); if (HOST_IS_OWNER(CSR_CRST(dev))) { /* Not owned by controller. This should not be possible as * we already called pcnetCanReceive(). */ - const unsigned cb = 1 << dev->iLog2DescSize; - uint32_t GCPhys = dev->GCRDRA; - iRxDesc = CSR_RCVRL(dev); + const unsigned cb = 1 << dev->iLog2DescSize; + uint32_t GCPhys = dev->GCRDRA; + iRxDesc = CSR_RCVRL(dev); while (iRxDesc-- > 0) { RMD rmd; @@ -1287,16 +1256,17 @@ pcnetReceiveNoSync(void *priv, uint8_t *buf, int size) GCPhys += cb; } dev->aCSR[0] |= 0x1000; /* Set MISS flag */ - CSR_MISSC(dev)++; - pcnetlog(2, "%s: pcnetReceiveNoSync: packet missed\n", dev->name); + CSR_MISSC(dev) + ++; + pcnetlog(2, "%s: pcnetReceiveNoSync: packet missed\n", dev->name); } else { - RTNETETHERHDR *pEth = (RTNETETHERHDR *)buf; - int fStrip = 0; - size_t len_802_3; - uint8_t *src = &dev->abRecvBuf[8]; - uint32_t crda = CSR_CRDA(dev); - uint32_t next_crda; - RMD rmd, next_rmd; + RTNETETHERHDR *pEth = (RTNETETHERHDR *) buf; + int fStrip = 0; + size_t len_802_3; + uint8_t *src = &dev->abRecvBuf[8]; + uint32_t crda = CSR_CRDA(dev); + uint32_t next_crda; + RMD rmd, next_rmd; /* * Ethernet framing considers these two octets to be @@ -1307,40 +1277,40 @@ pcnetReceiveNoSync(void *priv, uint8_t *buf, int size) * * NB: CSR_ASTRP_RCV bit affects only 802.3 frames! */ - len_802_3 = cpu_to_be16(pEth->EtherType); + len_802_3 = cpu_to_be16(pEth->EtherType); if (len_802_3 < 46 && CSR_ASTRP_RCV(dev)) { - size = MIN(sizeof(RTNETETHERHDR) + len_802_3, size); + size = MIN(sizeof(RTNETETHERHDR) + len_802_3, size); fStrip = 1; } - memcpy(src, buf, size); + memcpy(src, buf, size); if (!fStrip) { /* In loopback mode, Runt Packed Accept is always enabled internally; * don't do any padding because guest may be looping back very short packets. */ - if (!CSR_LOOP(dev)) - while (size < 60) - src[size++] = 0; + if (!CSR_LOOP(dev)) + while (size < 60) + src[size++] = 0; uint32_t fcs = UINT32_MAX; - uint8_t *p = src; + uint8_t *p = src; - while (p != &src[size]) - CRC(fcs, *p++); + while (p != &src[size]) + CRC(fcs, *p++); - /* FCS at the end of the packet */ - ((uint32_t *)&src[size])[0] = htonl(fcs); - size += 4; - } + /* FCS at the end of the packet */ + ((uint32_t *) &src[size])[0] = htonl(fcs); + size += 4; + } - cbPacket = (int)size; + cbPacket = (int) size; pcnetRmdLoad(dev, &rmd, PHYSADDR(dev, crda), 0); /* if (!CSR_LAPPEN(dev)) */ - rmd.rmd1.stp = 1; + rmd.rmd1.stp = 1; - size_t cbBuf = MIN(4096 - rmd.rmd1.bcnt, size); + size_t cbBuf = MIN(4096 - rmd.rmd1.bcnt, size); uint32_t rbadr = PHYSADDR(dev, rmd.rmd0.rbadr); /* save the old value to check if it was changed as long as we didn't @@ -1361,9 +1331,9 @@ pcnetReceiveNoSync(void *priv, uint8_t *buf, int size) /* RX disabled in the meantime? If so, abort RX. */ if (CSR_DRX(dev) || CSR_STOP(dev) || CSR_SPND(dev)) { - pcnetlog(3, "%s: RX disabled 1\n", dev->name); + pcnetlog(3, "%s: RX disabled 1\n", dev->name); return 0; - } + } /* Was the register modified in the meantime? If so, don't touch the * register but still update the RX descriptor. */ @@ -1394,7 +1364,7 @@ pcnetReceiveNoSync(void *priv, uint8_t *buf, int size) crda = next_crda; rmd = next_rmd; - cbBuf = MIN(4096 - (size_t)rmd.rmd1.bcnt, size); + cbBuf = MIN(4096 - (size_t) rmd.rmd1.bcnt, size); uint32_t rbadr2 = PHYSADDR(dev, rmd.rmd0.rbadr); /* We have to leave the critical section here or we risk deadlocking @@ -1404,9 +1374,9 @@ pcnetReceiveNoSync(void *priv, uint8_t *buf, int size) /* RX disabled in the meantime? If so, abort RX. */ if (CSR_DRX(dev) || CSR_STOP(dev) || CSR_SPND(dev)) { - pcnetlog(3, "%s: RX disabled 2\n", dev->name); + pcnetlog(3, "%s: RX disabled 2\n", dev->name); return 0; - } + } /* Was the register modified in the meantime? If so, don't touch the * register but still update the RX descriptor. */ @@ -1416,18 +1386,18 @@ pcnetReceiveNoSync(void *priv, uint8_t *buf, int size) CSR_RCVRC(dev) = iRxDesc; } else { iRxDesc = CSR_RCVRC(dev); - } + } src += cbBuf; size -= cbBuf; } if (size == 0) { - rmd.rmd1.enp = 1; - rmd.rmd1.pam = !CSR_PROM(dev) && is_padr; - rmd.rmd1.lafm = !CSR_PROM(dev) && is_ladr; - rmd.rmd1.bam = !CSR_PROM(dev) && is_bcast; - rmd.rmd2.mcnt = cbPacket; + rmd.rmd1.enp = 1; + rmd.rmd1.pam = !CSR_PROM(dev) && is_padr; + rmd.rmd1.lafm = !CSR_PROM(dev) && is_ladr; + rmd.rmd1.bam = !CSR_PROM(dev) && is_bcast; + rmd.rmd2.mcnt = cbPacket; rmd.rmd2.zeros = 0; } else { pcnetlog(1, "%s: Overflow by %ubytes\n", dev->name, size); @@ -1441,11 +1411,11 @@ pcnetReceiveNoSync(void *priv, uint8_t *buf, int size) dev->aCSR[0] |= 0x0400; pcnetlog(1, "%s: RINT set, RCVRC=%d CRDA=%#010x\n", dev->name, - CSR_RCVRC(dev), PHYSADDR(dev, CSR_CRDA(dev))); + CSR_RCVRC(dev), PHYSADDR(dev, CSR_CRDA(dev))); /* guest driver is owner: force repoll of current and next RDTEs */ CSR_CRST(dev) = 0; - } + } } pcnetUpdateIrq(dev); @@ -1496,7 +1466,7 @@ pcnetAsyncTransmit(nic_t *dev) * Iterate the transmit descriptors. */ unsigned cFlushIrq = 0; - int cMax = 32; + int cMax = 32; do { TMD tmd; if (!pcnetTdtePoll(dev, &tmd)) @@ -1504,8 +1474,7 @@ pcnetAsyncTransmit(nic_t *dev) /* Don't continue sending packets when the link is down. */ if ((!pcnetIsLinkUp(dev) - && dev->cLinkDownReported > PCNET_MAX_LINKDOWN_REPORTED) - ) + && dev->cLinkDownReported > PCNET_MAX_LINKDOWN_REPORTED)) break; pcnetlog(3, "%s: TMDLOAD %#010x\n", dev->name, PHYSADDR(dev, CSR_CXDA(dev))); @@ -1519,60 +1488,60 @@ pcnetAsyncTransmit(nic_t *dev) const int cb = 4096 - tmd.tmd1.bcnt; pcnetlog("%s: pcnetAsyncTransmit: stp&enp: cb=%d xmtrc=%#x\n", dev->name, cb, CSR_XMTRC(dev)); - if ((pcnetIsLinkUp(dev) || fLoopback)) { + if ((pcnetIsLinkUp(dev) || fLoopback)) { - /* From the manual: ``A zero length buffer is acceptable as - * long as it is not the last buffer in a chain (STP = 0 and - * ENP = 1).'' That means that the first buffer might have a - * zero length if it is not the last one in the chain. */ - if (cb <= MAX_FRAME) { - dev->xmit_pos = cb; - dma_bm_read(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf, cb, dev->transfer_size); + /* From the manual: ``A zero length buffer is acceptable as + * long as it is not the last buffer in a chain (STP = 0 and + * ENP = 1).'' That means that the first buffer might have a + * zero length if it is not the last one in the chain. */ + if (cb <= MAX_FRAME) { + dev->xmit_pos = cb; + dma_bm_read(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf, cb, dev->transfer_size); - if (fLoopback) { - if (HOST_IS_OWNER(CSR_CRST(dev))) - pcnetRdtePoll(dev); + if (fLoopback) { + if (HOST_IS_OWNER(CSR_CRST(dev))) + pcnetRdtePoll(dev); - pcnetReceiveNoSync(dev, dev->abLoopBuf, dev->xmit_pos); - } else { - pcnetlog(3, "%s: pcnetAsyncTransmit: transmit loopbuf stp and enp, xmit pos = %d\n", dev->name, dev->xmit_pos); - network_tx(dev->netcard, dev->abLoopBuf, dev->xmit_pos); - } - } else if (cb == 4096) { - /* The Windows NT4 pcnet driver sometimes marks the first - * unused descriptor as owned by us. Ignore that (by - * passing it back). Do not update the ring counter in this - * case (otherwise that driver becomes even more confused, - * which causes transmit to stall for about 10 seconds). - * This is just a workaround, not a final solution. - */ - /* r=frank: IMHO this is the correct implementation. The - * manual says: ``If the OWN bit is set and the buffer - * length is 0, the OWN bit will be cleared. In the C-LANCE - * the buffer length of 0 is interpreted as a 4096-byte - * buffer.'' - */ - /* r=michaln: Perhaps not quite right. The C-LANCE (Am79C90) - * datasheet explains that the old LANCE (Am7990) ignored - * the top four bits next to BCNT and a count of 0 was - * interpreted as 4096. In the C-LANCE, that is still the - * case if the top bits are all ones. If all 16 bits are - * zero, the C-LANCE interprets it as zero-length transmit - * buffer. It's not entirely clear if the later models - * (PCnet-ISA, PCnet-PCI) behave like the C-LANCE or not. - * It is possible that the actual behavior of the C-LANCE - * and later hardware is that the buffer lengths are *16-bit* - * two's complement numbers between 0 and 4096. AMD's drivers - * in fact generally treat the length as a 16-bit quantity. */ - pcnetlog(1, "%s: pcnetAsyncTransmit: illegal 4kb frame -> ignoring\n", dev->name); - pcnetTmdStorePassHost(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev))); - break; - } else { - pcnetXmitFailTMDGeneric(dev, &tmd); - } - } else { - pcnetXmitFailTMDLinkDown(dev, &tmd); - } + pcnetReceiveNoSync(dev, dev->abLoopBuf, dev->xmit_pos); + } else { + pcnetlog(3, "%s: pcnetAsyncTransmit: transmit loopbuf stp and enp, xmit pos = %d\n", dev->name, dev->xmit_pos); + network_tx(dev->netcard, dev->abLoopBuf, dev->xmit_pos); + } + } else if (cb == 4096) { + /* The Windows NT4 pcnet driver sometimes marks the first + * unused descriptor as owned by us. Ignore that (by + * passing it back). Do not update the ring counter in this + * case (otherwise that driver becomes even more confused, + * which causes transmit to stall for about 10 seconds). + * This is just a workaround, not a final solution. + */ + /* r=frank: IMHO this is the correct implementation. The + * manual says: ``If the OWN bit is set and the buffer + * length is 0, the OWN bit will be cleared. In the C-LANCE + * the buffer length of 0 is interpreted as a 4096-byte + * buffer.'' + */ + /* r=michaln: Perhaps not quite right. The C-LANCE (Am79C90) + * datasheet explains that the old LANCE (Am7990) ignored + * the top four bits next to BCNT and a count of 0 was + * interpreted as 4096. In the C-LANCE, that is still the + * case if the top bits are all ones. If all 16 bits are + * zero, the C-LANCE interprets it as zero-length transmit + * buffer. It's not entirely clear if the later models + * (PCnet-ISA, PCnet-PCI) behave like the C-LANCE or not. + * It is possible that the actual behavior of the C-LANCE + * and later hardware is that the buffer lengths are *16-bit* + * two's complement numbers between 0 and 4096. AMD's drivers + * in fact generally treat the length as a 16-bit quantity. */ + pcnetlog(1, "%s: pcnetAsyncTransmit: illegal 4kb frame -> ignoring\n", dev->name); + pcnetTmdStorePassHost(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev))); + break; + } else { + pcnetXmitFailTMDGeneric(dev, &tmd); + } + } else { + pcnetXmitFailTMDLinkDown(dev, &tmd); + } /* Write back the TMD and pass it to the host (clear own bit). */ pcnetTmdStorePassHost(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev))); @@ -1581,8 +1550,9 @@ pcnetAsyncTransmit(nic_t *dev) if (CSR_XMTRC(dev) < 2) { CSR_XMTRC(dev) = CSR_XMTRL(dev); } else { - CSR_XMTRC(dev)--; - } + CSR_XMTRC(dev) + --; + } } else if (tmd.tmd1.stp) { /* * Read TMDs until end-of-packet or tdte poll fails (underflow). @@ -1591,9 +1561,9 @@ pcnetAsyncTransmit(nic_t *dev) * waste time finding out how much space we actually need even if * we could reliably do that on SMP guests. */ - unsigned cb = 4096 - tmd.tmd1.bcnt; - dev->xmit_pos = pcnetCalcPacketLen(dev, cb); - dma_bm_read(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf, cb, dev->transfer_size); + unsigned cb = 4096 - tmd.tmd1.bcnt; + dev->xmit_pos = pcnetCalcPacketLen(dev, cb); + dma_bm_read(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf, cb, dev->transfer_size); for (;;) { /* @@ -1603,7 +1573,8 @@ pcnetAsyncTransmit(nic_t *dev) if (CSR_XMTRC(dev) < 2) CSR_XMTRC(dev) = CSR_XMTRL(dev); else - CSR_XMTRC(dev)--; + CSR_XMTRC(dev) + --; TMD dummy; if (!pcnetTdtePoll(dev, &dummy)) { @@ -1611,13 +1582,13 @@ pcnetAsyncTransmit(nic_t *dev) * Underflow! */ tmd.tmd2.buff = tmd.tmd2.uflo = tmd.tmd1.err = 1; - dev->aCSR[0] |= 0x0200; /* set TINT */ - /* Don't allow the guest to clear TINT before reading it */ - dev->u16CSR0LastSeenByGuest &= ~0x0200; - if (!CSR_DXSUFLO(dev)) /* stop on xmit underflow */ - dev->aCSR[0] &= ~0x0010; /* clear TXON */ + dev->aCSR[0] |= 0x0200; /* set TINT */ + /* Don't allow the guest to clear TINT before reading it */ + dev->u16CSR0LastSeenByGuest &= ~0x0200; + if (!CSR_DXSUFLO(dev)) /* stop on xmit underflow */ + dev->aCSR[0] &= ~0x0010; /* clear TXON */ pcnetTmdStorePassHost(dev, &tmd, GCPhysPrevTmd); - pcnetlog(3,"%s: pcnetAsyncTransmit: Underflow!!!\n", dev->name); + pcnetlog(3, "%s: pcnetAsyncTransmit: Underflow!!!\n", dev->name); break; } @@ -1630,25 +1601,25 @@ pcnetAsyncTransmit(nic_t *dev) pcnetTmdLoad(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev)), 0); cb = 4096 - tmd.tmd1.bcnt; if (dev->xmit_pos + cb <= MAX_FRAME) { /** @todo this used to be ... + cb < MAX_FRAME. */ - int off = dev->xmit_pos; - dev->xmit_pos = cb + off; - dma_bm_read(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf + off, cb, dev->transfer_size); - } + int off = dev->xmit_pos; + dev->xmit_pos = cb + off; + dma_bm_read(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf + off, cb, dev->transfer_size); + } /* * Done already? */ if (tmd.tmd1.enp) { - if (fLoopback) { - if (HOST_IS_OWNER(CSR_CRST(dev))) - pcnetRdtePoll(dev); + if (fLoopback) { + if (HOST_IS_OWNER(CSR_CRST(dev))) + pcnetRdtePoll(dev); - pcnetlog(3, "%s: pcnetAsyncTransmit: receive loopback enp\n", dev->name); - pcnetReceiveNoSync(dev, dev->abLoopBuf, dev->xmit_pos); - } else { - pcnetlog(3, "%s: pcnetAsyncTransmit: transmit loopbuf enp\n", dev->name); - network_tx(dev->netcard, dev->abLoopBuf, dev->xmit_pos); - } + pcnetlog(3, "%s: pcnetAsyncTransmit: receive loopback enp\n", dev->name); + pcnetReceiveNoSync(dev, dev->abLoopBuf, dev->xmit_pos); + } else { + pcnetlog(3, "%s: pcnetAsyncTransmit: transmit loopbuf enp\n", dev->name); + network_tx(dev->netcard, dev->abLoopBuf, dev->xmit_pos); + } /* Write back the TMD, pass it to the host */ pcnetTmdStorePassHost(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev))); @@ -1657,40 +1628,40 @@ pcnetAsyncTransmit(nic_t *dev) if (CSR_XMTRC(dev) < 2) CSR_XMTRC(dev) = CSR_XMTRL(dev); else - CSR_XMTRC(dev)--; + CSR_XMTRC(dev) + --; break; } } /* the loop */ } /* Update TDMD, TXSTRT and TINT. */ - dev->aCSR[0] &= ~0x0008; /* clear TDMD */ - dev->aCSR[4] |= 0x0008; /* set TXSTRT */ - dev->xmit_pos = -1; - if (!CSR_TOKINTD(dev) /* Transmit OK Interrupt Disable, no infl. on errors. */ - || (CSR_LTINTEN(dev) && tmd.tmd1.ltint) + dev->aCSR[0] &= ~0x0008; /* clear TDMD */ + dev->aCSR[4] |= 0x0008; /* set TXSTRT */ + dev->xmit_pos = -1; + if (!CSR_TOKINTD(dev) /* Transmit OK Interrupt Disable, no infl. on errors. */ + || (CSR_LTINTEN(dev) && tmd.tmd1.ltint) || tmd.tmd1.err) { - cFlushIrq++; + cFlushIrq++; } if (--cMax == 0) break; - } while (CSR_TXON(dev)); /* transfer on */ + } while (CSR_TXON(dev)); /* transfer on */ if (cFlushIrq) { - dev->aCSR[0] |= 0x0200; /* set TINT */ - /* Don't allow the guest to clear TINT before reading it */ - dev->u16CSR0LastSeenByGuest &= ~0x0200; - pcnetUpdateIrq(dev); + dev->aCSR[0] |= 0x0200; /* set TINT */ + /* Don't allow the guest to clear TINT before reading it */ + dev->u16CSR0LastSeenByGuest &= ~0x0200; + pcnetUpdateIrq(dev); } } - /** * Poll for changes in RX and TX descriptor rings. */ static void pcnetPollRxTx(nic_t *dev) { - if (CSR_RXON(dev)) { + if (CSR_RXON(dev)) { /* * The second case is important for pcnetWaitReceiveAvail(): If CSR_CRST(dev) was * true but pcnetCanReceive() returned false for some other reason we need to check @@ -1704,24 +1675,22 @@ pcnetPollRxTx(nic_t *dev) pcnetAsyncTransmit(dev); } - static void pcnetPollTimer(void *p) { - nic_t *dev = (nic_t *)p; + nic_t *dev = (nic_t *) p; timer_advance_u64(&dev->timer, 2000 * TIMER_USEC); if (CSR_TDMD(dev)) - pcnetAsyncTransmit(dev); + pcnetAsyncTransmit(dev); pcnetUpdateIrq(dev); if (!CSR_STOP(dev) && !CSR_SPND(dev) && (!CSR_DPOLL(dev) || dev->fMaybeOutOfSpace)) - pcnetPollRxTx(dev); + pcnetPollRxTx(dev); } - static void pcnetHardReset(nic_t *dev) { @@ -1733,24 +1702,24 @@ pcnetHardReset(nic_t *dev) /* Many of the BCR values would normally be read from the EEPROM. */ dev->aBCR[BCR_MSRDA] = 0x0005; dev->aBCR[BCR_MSWRA] = 0x0005; - dev->aBCR[BCR_MC] = 0x0002; + dev->aBCR[BCR_MC] = 0x0002; dev->aBCR[BCR_LNKST] = 0x00c0; - dev->aBCR[BCR_LED1] = 0x0084; - dev->aBCR[BCR_LED2] = 0x0088; - dev->aBCR[BCR_LED3] = 0x0090; + dev->aBCR[BCR_LED1] = 0x0084; + dev->aBCR[BCR_LED2] = 0x0088; + dev->aBCR[BCR_LED3] = 0x0090; - dev->aBCR[BCR_FDC] = 0x0000; - dev->aBCR[BCR_BSBC] = 0x9001; + dev->aBCR[BCR_FDC] = 0x0000; + dev->aBCR[BCR_BSBC] = 0x9001; dev->aBCR[BCR_EECAS] = 0x0002; dev->aBCR[BCR_STVAL] = 0xffff; dev->aCSR[58] = dev->aBCR[BCR_SWS] = 0x0200; /* CSR58 is an alias for BCR20 */ - dev->iLog2DescSize = 3; - dev->aBCR[BCR_PLAT] = 0xff06; - dev->aBCR[BCR_MIICAS] = 0x20; /* Auto-negotiation on. */ - dev->aBCR[BCR_MIIADDR] = 0; /* Internal PHY on Am79C973 would be (0x1e << 5) */ - dev->aBCR[BCR_PCIVID] = 0x1022; - dev->aBCR[BCR_PCISID] = 0x0020; - dev->aBCR[BCR_PCISVID] = 0x1022; + dev->iLog2DescSize = 3; + dev->aBCR[BCR_PLAT] = 0xff06; + dev->aBCR[BCR_MIICAS] = 0x20; /* Auto-negotiation on. */ + dev->aBCR[BCR_MIIADDR] = 0; /* Internal PHY on Am79C973 would be (0x1e << 5) */ + dev->aBCR[BCR_PCIVID] = 0x1022; + dev->aBCR[BCR_PCISID] = 0x0020; + dev->aBCR[BCR_PCISVID] = 0x1022; /* Reset the error counter. */ dev->uCntBadRMD = 0; @@ -1758,193 +1727,191 @@ pcnetHardReset(nic_t *dev) pcnetSoftReset(dev); } - static void pcnet_csr_writew(nic_t *dev, uint16_t rap, uint16_t val) { pcnetlog(1, "%s: pcnet_csr_writew: rap=%d val=%#06x\n", dev->name, rap, val); switch (rap) { - case 0: - { - uint16_t csr0 = dev->aCSR[0]; - /* Clear any interrupt flags. - * Don't clear an interrupt flag which was not seen by the guest yet. */ - csr0 &= ~(val & 0x7f00 & dev->u16CSR0LastSeenByGuest); - csr0 = (csr0 & ~0x0040) | (val & 0x0048); - val = (val & 0x007f) | (csr0 & 0x7f00); + case 0: + { + uint16_t csr0 = dev->aCSR[0]; + /* Clear any interrupt flags. + * Don't clear an interrupt flag which was not seen by the guest yet. */ + csr0 &= ~(val & 0x7f00 & dev->u16CSR0LastSeenByGuest); + csr0 = (csr0 & ~0x0040) | (val & 0x0048); + val = (val & 0x007f) | (csr0 & 0x7f00); - /* If STOP, STRT and INIT are set, clear STRT and INIT */ - if ((val & 7) == 7) - val &= ~3; + /* If STOP, STRT and INIT are set, clear STRT and INIT */ + if ((val & 7) == 7) + val &= ~3; - pcnetlog(2, "%s: CSR0 val = %04x, val2 = %04x\n", dev->name, val, dev->aCSR[0]); + pcnetlog(2, "%s: CSR0 val = %04x, val2 = %04x\n", dev->name, val, dev->aCSR[0]); - dev->aCSR[0] = csr0; + dev->aCSR[0] = csr0; - if (!CSR_STOP(dev) && (val & 4)) { - pcnetlog(3, "%s: pcnet_csr_writew(): Stop\n", dev->name); - pcnetStop(dev); - } + if (!CSR_STOP(dev) && (val & 4)) { + pcnetlog(3, "%s: pcnet_csr_writew(): Stop\n", dev->name); + pcnetStop(dev); + } - if (!CSR_INIT(dev) && (val & 1)) { - pcnetlog(3, "%s: pcnet_csr_writew(): Init\n", dev->name); - pcnetInit(dev); - } + if (!CSR_INIT(dev) && (val & 1)) { + pcnetlog(3, "%s: pcnet_csr_writew(): Init\n", dev->name); + pcnetInit(dev); + } - if (!CSR_STRT(dev) && (val & 2)) { - pcnetlog(3, "%s: pcnet_csr_writew(): Start\n", dev->name); - pcnetStart(dev); - } + if (!CSR_STRT(dev) && (val & 2)) { + pcnetlog(3, "%s: pcnet_csr_writew(): Start\n", dev->name); + pcnetStart(dev); + } - if (CSR_TDMD(dev)) { - pcnetlog(3, "%s: pcnet_csr_writew(): Transmit\n", dev->name); - pcnetAsyncTransmit(dev); - } - } - return; + if (CSR_TDMD(dev)) { + pcnetlog(3, "%s: pcnet_csr_writew(): Transmit\n", dev->name); + pcnetAsyncTransmit(dev); + } + } + return; - case 2: /* IADRH */ - if (dev->is_isa) - val &= 0x00ff; /* Upper 8 bits ignored on ISA chips. */ - case 1: /* IADRL */ - case 8: /* LADRF 0..15 */ - case 9: /* LADRF 16..31 */ - case 10: /* LADRF 32..47 */ - case 11: /* LADRF 48..63 */ - case 12: /* PADR 0..15 */ - case 13: /* PADR 16..31 */ - case 14: /* PADR 32..47 */ - case 18: /* CRBAL */ - case 19: /* CRBAU */ - case 20: /* CXBAL */ - case 21: /* CXBAU */ - case 22: /* NRBAL */ - case 23: /* NRBAU */ - case 26: /* NRDAL */ - case 27: /* NRDAU */ - case 28: /* CRDAL */ - case 29: /* CRDAU */ - case 32: /* NXDAL */ - case 33: /* NXDAU */ - case 34: /* CXDAL */ - case 35: /* CXDAU */ - case 36: /* NNRDL */ - case 37: /* NNRDU */ - case 38: /* NNXDL */ - case 39: /* NNXDU */ - case 40: /* CRBCL */ - case 41: /* CRBCU */ - case 42: /* CXBCL */ - case 43: /* CXBCU */ - case 44: /* NRBCL */ - case 45: /* NRBCU */ - case 46: /* POLL */ - case 47: /* POLLINT */ - case 72: /* RCVRC */ - case 74: /* XMTRC */ - case 112: /* MISSC */ - if (CSR_STOP(dev) || CSR_SPND(dev)) - break; - return; - case 3: /* Interrupt Mask and Deferral Control */ - break; - case 4: /* Test and Features Control */ - dev->aCSR[4] &= ~(val & 0x026a); - val &= ~0x026a; - val |= dev->aCSR[4] & 0x026a; - break; - case 5: /* Extended Control and Interrupt 1 */ - dev->aCSR[5] &= ~(val & 0x0a90); - val &= ~0x0a90; - val |= dev->aCSR[5] & 0x0a90; - break; - case 7: /* Extended Control and Interrupt 2 */ - { - uint16_t csr7 = dev->aCSR[7]; - csr7 &= ~0x0400; - csr7 &= ~(val & 0x0800); - csr7 |= (val & 0x0400); - dev->aCSR[7] = csr7; - } - return; - case 15: /* Mode */ - break; - case 16: /* IADRL */ - pcnet_csr_writew(dev,1,val); - return; - case 17: /* IADRH */ - pcnet_csr_writew(dev,2,val); - return; - /* - * 24 and 25 are the Base Address of Receive Descriptor. - * We combine and mirror these in GCRDRA. - */ - case 24: /* BADRL */ - case 25: /* BADRU */ - if (!CSR_STOP(dev) && !CSR_SPND(dev)) { - pcnetlog(3, "%s: WRITE CSR%d, %#06x, ignoring!!\n", dev->name, rap, val); - return; - } - if (rap == 24) - dev->GCRDRA = (dev->GCRDRA & 0xffff0000) | (val & 0x0000ffff); - else - dev->GCRDRA = (dev->GCRDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16); - pcnetlog(3, "%s: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", dev->name, rap, val, dev->GCRDRA); - if (dev->GCRDRA & (dev->iLog2DescSize - 1)) - pcnetlog(1, "%s: Warning: Misaligned RDRA (GCRDRA=%#010x)\n", dev->name, dev->GCRDRA); - break; - /* - * 30 & 31 are the Base Address of Transmit Descriptor. - * We combine and mirrorthese in GCTDRA. - */ - case 30: /* BADXL */ - case 31: /* BADXU */ - if (!CSR_STOP(dev) && !CSR_SPND(dev)) { - pcnetlog(3, "%s: WRITE CSR%d, %#06x !!\n", dev->name, rap, val); - return; - } - if (rap == 30) - dev->GCTDRA = (dev->GCTDRA & 0xffff0000) | (val & 0x0000ffff); - else - dev->GCTDRA = (dev->GCTDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16); + case 2: /* IADRH */ + if (dev->is_isa) + val &= 0x00ff; /* Upper 8 bits ignored on ISA chips. */ + case 1: /* IADRL */ + case 8: /* LADRF 0..15 */ + case 9: /* LADRF 16..31 */ + case 10: /* LADRF 32..47 */ + case 11: /* LADRF 48..63 */ + case 12: /* PADR 0..15 */ + case 13: /* PADR 16..31 */ + case 14: /* PADR 32..47 */ + case 18: /* CRBAL */ + case 19: /* CRBAU */ + case 20: /* CXBAL */ + case 21: /* CXBAU */ + case 22: /* NRBAL */ + case 23: /* NRBAU */ + case 26: /* NRDAL */ + case 27: /* NRDAU */ + case 28: /* CRDAL */ + case 29: /* CRDAU */ + case 32: /* NXDAL */ + case 33: /* NXDAU */ + case 34: /* CXDAL */ + case 35: /* CXDAU */ + case 36: /* NNRDL */ + case 37: /* NNRDU */ + case 38: /* NNXDL */ + case 39: /* NNXDU */ + case 40: /* CRBCL */ + case 41: /* CRBCU */ + case 42: /* CXBCL */ + case 43: /* CXBCU */ + case 44: /* NRBCL */ + case 45: /* NRBCU */ + case 46: /* POLL */ + case 47: /* POLLINT */ + case 72: /* RCVRC */ + case 74: /* XMTRC */ + case 112: /* MISSC */ + if (CSR_STOP(dev) || CSR_SPND(dev)) + break; + return; + case 3: /* Interrupt Mask and Deferral Control */ + break; + case 4: /* Test and Features Control */ + dev->aCSR[4] &= ~(val & 0x026a); + val &= ~0x026a; + val |= dev->aCSR[4] & 0x026a; + break; + case 5: /* Extended Control and Interrupt 1 */ + dev->aCSR[5] &= ~(val & 0x0a90); + val &= ~0x0a90; + val |= dev->aCSR[5] & 0x0a90; + break; + case 7: /* Extended Control and Interrupt 2 */ + { + uint16_t csr7 = dev->aCSR[7]; + csr7 &= ~0x0400; + csr7 &= ~(val & 0x0800); + csr7 |= (val & 0x0400); + dev->aCSR[7] = csr7; + } + return; + case 15: /* Mode */ + break; + case 16: /* IADRL */ + pcnet_csr_writew(dev, 1, val); + return; + case 17: /* IADRH */ + pcnet_csr_writew(dev, 2, val); + return; + /* + * 24 and 25 are the Base Address of Receive Descriptor. + * We combine and mirror these in GCRDRA. + */ + case 24: /* BADRL */ + case 25: /* BADRU */ + if (!CSR_STOP(dev) && !CSR_SPND(dev)) { + pcnetlog(3, "%s: WRITE CSR%d, %#06x, ignoring!!\n", dev->name, rap, val); + return; + } + if (rap == 24) + dev->GCRDRA = (dev->GCRDRA & 0xffff0000) | (val & 0x0000ffff); + else + dev->GCRDRA = (dev->GCRDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16); + pcnetlog(3, "%s: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", dev->name, rap, val, dev->GCRDRA); + if (dev->GCRDRA & (dev->iLog2DescSize - 1)) + pcnetlog(1, "%s: Warning: Misaligned RDRA (GCRDRA=%#010x)\n", dev->name, dev->GCRDRA); + break; + /* + * 30 & 31 are the Base Address of Transmit Descriptor. + * We combine and mirrorthese in GCTDRA. + */ + case 30: /* BADXL */ + case 31: /* BADXU */ + if (!CSR_STOP(dev) && !CSR_SPND(dev)) { + pcnetlog(3, "%s: WRITE CSR%d, %#06x !!\n", dev->name, rap, val); + return; + } + if (rap == 30) + dev->GCTDRA = (dev->GCTDRA & 0xffff0000) | (val & 0x0000ffff); + else + dev->GCTDRA = (dev->GCTDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16); - pcnetlog(3, "%s: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", dev->name, rap, val, dev->GCTDRA); + pcnetlog(3, "%s: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", dev->name, rap, val, dev->GCTDRA); - if (dev->GCTDRA & (dev->iLog2DescSize - 1)) - pcnetlog(1, "%s: Warning: Misaligned TDRA (GCTDRA=%#010x)\n", dev->name, dev->GCTDRA); - break; - case 58: /* Software Style */ - pcnet_bcr_writew(dev,BCR_SWS,val); - break; - /* - * Registers 76 and 78 aren't stored correctly (see todos), but I'm don't dare - * try fix that right now. So, as a quick hack for 'alt init' I'll just correct them here. - */ - case 76: /* RCVRL */ /** @todo call pcnetUpdateRingHandlers */ - /** @todo receive ring length is stored in two's complement! */ - case 78: /* XMTRL */ /** @todo call pcnetUpdateRingHandlers */ - /** @todo transmit ring length is stored in two's complement! */ - if (!CSR_STOP(dev) && !CSR_SPND(dev)) { - pcnetlog(3, "%s: WRITE CSR%d, %#06x !!\n", dev->name, rap, val); - return; - } - pcnetlog(3, "%s: WRITE CSR%d, %#06x (hacked %#06x) (alt init)\n", dev->name, - rap, val, 1 + ~val); - val = 1 + ~val; + if (dev->GCTDRA & (dev->iLog2DescSize - 1)) + pcnetlog(1, "%s: Warning: Misaligned TDRA (GCTDRA=%#010x)\n", dev->name, dev->GCTDRA); + break; + case 58: /* Software Style */ + pcnet_bcr_writew(dev, BCR_SWS, val); + break; + /* + * Registers 76 and 78 aren't stored correctly (see todos), but I'm don't dare + * try fix that right now. So, as a quick hack for 'alt init' I'll just correct them here. + */ + case 76: /* RCVRL */ /** @todo call pcnetUpdateRingHandlers */ + /** @todo receive ring length is stored in two's complement! */ + case 78: /* XMTRL */ /** @todo call pcnetUpdateRingHandlers */ + /** @todo transmit ring length is stored in two's complement! */ + if (!CSR_STOP(dev) && !CSR_SPND(dev)) { + pcnetlog(3, "%s: WRITE CSR%d, %#06x !!\n", dev->name, rap, val); + return; + } + pcnetlog(3, "%s: WRITE CSR%d, %#06x (hacked %#06x) (alt init)\n", dev->name, + rap, val, 1 + ~val); + val = 1 + ~val; - /* - * HACK ALERT! Set the counter registers too. - */ - dev->aCSR[rap - 4] = val; - break; - default: - return; + /* + * HACK ALERT! Set the counter registers too. + */ + dev->aCSR[rap - 4] = val; + break; + default: + return; } dev->aCSR[rap] = val; } - /** * Encode a 32-bit link speed into a custom 16-bit floating-point value */ @@ -1960,98 +1927,96 @@ pcnetLinkSpd(uint32_t speed) return (exp << 13) | speed; } - static uint16_t pcnet_csr_readw(nic_t *dev, uint16_t rap) { uint16_t val; switch (rap) { - case 0: - pcnetUpdateIrq(dev); - val = dev->aCSR[0]; - val |= (val & 0x7800) ? 0x8000 : 0; - dev->u16CSR0LastSeenByGuest = val; - break; - case 16: - return pcnet_csr_readw(dev,1); - case 17: - return pcnet_csr_readw(dev,2); - case 58: - return pcnet_bcr_readw(dev,BCR_SWS); - case 68: /* Custom register to pass link speed to driver */ - return pcnetLinkSpd(dev->u32LinkSpeed); - default: - val = dev->aCSR[rap]; - break; + case 0: + pcnetUpdateIrq(dev); + val = dev->aCSR[0]; + val |= (val & 0x7800) ? 0x8000 : 0; + dev->u16CSR0LastSeenByGuest = val; + break; + case 16: + return pcnet_csr_readw(dev, 1); + case 17: + return pcnet_csr_readw(dev, 2); + case 58: + return pcnet_bcr_readw(dev, BCR_SWS); + case 68: /* Custom register to pass link speed to driver */ + return pcnetLinkSpd(dev->u32LinkSpeed); + default: + val = dev->aCSR[rap]; + break; } pcnetlog(3, "%s: pcnet_csr_readw rap=%d val=0x%04x\n", dev->name, rap, val); return val; } - static void pcnet_bcr_writew(nic_t *dev, uint16_t rap, uint16_t val) { rap &= 0x7f; pcnetlog(3, "%s: pcnet_bcr_writew rap=%d val=0x%04x\n", dev->name, rap, val); switch (rap) { - case BCR_SWS: - if (!(CSR_STOP(dev) || CSR_SPND(dev))) - return; - val &= ~0x0300; - switch (val & 0x00ff) { - default: - case 0: - val |= 0x0200; /* 16 bit */ - dev->iLog2DescSize = 3; - dev->GCUpperPhys = (0xff00 & dev->aCSR[2]) << 16; - break; - case 1: - val |= 0x0100; /* 32 bit */ - dev->iLog2DescSize = 4; - dev->GCUpperPhys = 0; - break; - case 2: - case 3: - val |= 0x0300; /* 32 bit */ - dev->iLog2DescSize = 4; - dev->GCUpperPhys = 0; - break; - } - dev->aCSR[58] = val; - /* fall through */ - case BCR_LNKST: - case BCR_LED1: - case BCR_LED2: - case BCR_LED3: - case BCR_MC: - case BCR_FDC: - case BCR_BSBC: - case BCR_EECAS: - case BCR_PLAT: - case BCR_MIIADDR: - dev->aBCR[rap] = val; - break; + case BCR_SWS: + if (!(CSR_STOP(dev) || CSR_SPND(dev))) + return; + val &= ~0x0300; + switch (val & 0x00ff) { + default: + case 0: + val |= 0x0200; /* 16 bit */ + dev->iLog2DescSize = 3; + dev->GCUpperPhys = (0xff00 & dev->aCSR[2]) << 16; + break; + case 1: + val |= 0x0100; /* 32 bit */ + dev->iLog2DescSize = 4; + dev->GCUpperPhys = 0; + break; + case 2: + case 3: + val |= 0x0300; /* 32 bit */ + dev->iLog2DescSize = 4; + dev->GCUpperPhys = 0; + break; + } + dev->aCSR[58] = val; + /* fall through */ + case BCR_LNKST: + case BCR_LED1: + case BCR_LED2: + case BCR_LED3: + case BCR_MC: + case BCR_FDC: + case BCR_BSBC: + case BCR_EECAS: + case BCR_PLAT: + case BCR_MIIADDR: + dev->aBCR[rap] = val; + break; - case BCR_MIICAS: - dev->netcard->byte_period = (dev->board == DEV_AM79C973 && (val & 0x28)) ? NET_PERIOD_100M : NET_PERIOD_10M; - dev->aBCR[rap] = val; - break; + case BCR_MIICAS: + dev->netcard->byte_period = (dev->board == DEV_AM79C973 && (val & 0x28)) ? NET_PERIOD_100M : NET_PERIOD_10M; + dev->aBCR[rap] = val; + break; - case BCR_STVAL: - val &= 0xffff; - dev->aBCR[BCR_STVAL] = val; - if (dev->board == DEV_AM79C973) - timer_set_delay_u64(&dev->timer_soft_int, (12.8 * val) * TIMER_USEC); - break; + case BCR_STVAL: + val &= 0xffff; + dev->aBCR[BCR_STVAL] = val; + if (dev->board == DEV_AM79C973) + timer_set_delay_u64(&dev->timer_soft_int, (12.8 * val) * TIMER_USEC); + break; - case BCR_MIIMDR: - dev->aMII[dev->aBCR[BCR_MIIADDR] & 0x1f] = val; - break; + case BCR_MIIMDR: + dev->aMII[dev->aBCR[BCR_MIIADDR] & 0x1f] = val; + break; - default: - break; + default: + break; } } @@ -2059,132 +2024,132 @@ static uint16_t pcnet_mii_readw(nic_t *dev, uint16_t miiaddr) { uint16_t val; - int autoneg, duplex, fast, isolate; + int autoneg, duplex, fast, isolate; /* If the DANAS (BCR32.7) bit is set, the MAC does not do any * auto-negotiation and the PHY must be set up explicitly. DANAS * effectively disables most other BCR32 bits. */ if (dev->aBCR[BCR_MIICAS] & 0x80) { - /* PHY controls auto-negotiation. */ - autoneg = duplex = fast = 1; + /* PHY controls auto-negotiation. */ + autoneg = duplex = fast = 1; } else { - /* BCR32 controls auto-negotiation. */ - autoneg = (dev->aBCR[BCR_MIICAS] & 0x20) != 0; - duplex = (dev->aBCR[BCR_MIICAS] & 0x10) != 0; - fast = (dev->aBCR[BCR_MIICAS] & 0x08) != 0; + /* BCR32 controls auto-negotiation. */ + autoneg = (dev->aBCR[BCR_MIICAS] & 0x20) != 0; + duplex = (dev->aBCR[BCR_MIICAS] & 0x10) != 0; + fast = (dev->aBCR[BCR_MIICAS] & 0x08) != 0; } /* Electrically isolating the PHY mostly disables it. */ isolate = (dev->aMII[0] & 0x400) != 0; switch (miiaddr) { - case 0: - /* MII basic mode control register. */ - val = 0; - if (autoneg) - val |= 0x1000; /* Enable auto negotiation. */ - if (fast) - val |= 0x2000; /* 100 Mbps */ - if (duplex) /* Full duplex forced */ - val |= 0x0100; /* Full duplex */ - if (isolate) /* PHY electrically isolated. */ - val |= 0x0400; /* Isolated */ - break; + case 0: + /* MII basic mode control register. */ + val = 0; + if (autoneg) + val |= 0x1000; /* Enable auto negotiation. */ + if (fast) + val |= 0x2000; /* 100 Mbps */ + if (duplex) /* Full duplex forced */ + val |= 0x0100; /* Full duplex */ + if (isolate) /* PHY electrically isolated. */ + val |= 0x0400; /* Isolated */ + break; - case 1: - /* MII basic mode status register. */ - val = 0x7800 /* Can do 100mbps FD/HD and 10mbps FD/HD. */ - | 0x0040 /* Mgmt frame preamble not required. */ - | 0x0020 /* Auto-negotiation complete. */ - | 0x0008 /* Able to do auto-negotiation. */ - | 0x0004 /* Link up. */ - | 0x0001; /* Extended Capability, i.e. registers 4+ valid. */ - if (!pcnetIsLinkUp(dev) || isolate) { - val &= ~(0x0020 | 0x0004); - dev->cLinkDownReported++; - } - if (!autoneg) { - /* Auto-negotiation disabled. */ - val &= ~(0x0020 | 0x0008); - if (duplex) - val &= ~0x2800; /* Full duplex forced. */ - else - val &= ~0x5000; /* Half duplex forced. */ + case 1: + /* MII basic mode status register. */ + val = 0x7800 /* Can do 100mbps FD/HD and 10mbps FD/HD. */ + | 0x0040 /* Mgmt frame preamble not required. */ + | 0x0020 /* Auto-negotiation complete. */ + | 0x0008 /* Able to do auto-negotiation. */ + | 0x0004 /* Link up. */ + | 0x0001; /* Extended Capability, i.e. registers 4+ valid. */ + if (!pcnetIsLinkUp(dev) || isolate) { + val &= ~(0x0020 | 0x0004); + dev->cLinkDownReported++; + } + if (!autoneg) { + /* Auto-negotiation disabled. */ + val &= ~(0x0020 | 0x0008); + if (duplex) + val &= ~0x2800; /* Full duplex forced. */ + else + val &= ~0x5000; /* Half duplex forced. */ - if (fast) - val &= ~0x1800; /* 100 Mbps forced */ - else - val &= ~0x6000; /* 10 Mbps forced */ - } - break; + if (fast) + val &= ~0x1800; /* 100 Mbps forced */ + else + val &= ~0x6000; /* 10 Mbps forced */ + } + break; - case 2: - /* PHY identifier 1. */ - val = 0x22; /* Am79C874/AC101 PHY */ - break; + case 2: + /* PHY identifier 1. */ + val = 0x22; /* Am79C874/AC101 PHY */ + break; - case 3: - /* PHY identifier 2. */ - val = 0x561b; /* Am79C874/AC101 PHY */ - break; + case 3: + /* PHY identifier 2. */ + val = 0x561b; /* Am79C874/AC101 PHY */ + break; - case 4: - /* Advertisement control register. */ - val = 0x01e0 /* Try 100mbps FD/HD and 10mbps FD/HD. */ - | 0x0001; /* CSMA selector. */ - break; + case 4: + /* Advertisement control register. */ + val = 0x01e0 /* Try 100mbps FD/HD and 10mbps FD/HD. */ + | 0x0001; /* CSMA selector. */ + break; - case 5: - /* Link partner ability register. */ - if (pcnetIsLinkUp(dev) && !isolate) { - val = 0x8000 /* Next page bit. */ - | 0x4000 /* Link partner acked us. */ - | 0x0400 /* Can do flow control. */ - | 0x01e0 /* Can do 100mbps FD/HD and 10mbps FD/HD. */ - | 0x0001; /* Use CSMA selector. */ - } else { - val = 0; - dev->cLinkDownReported++; - } - break; + case 5: + /* Link partner ability register. */ + if (pcnetIsLinkUp(dev) && !isolate) { + val = 0x8000 /* Next page bit. */ + | 0x4000 /* Link partner acked us. */ + | 0x0400 /* Can do flow control. */ + | 0x01e0 /* Can do 100mbps FD/HD and 10mbps FD/HD. */ + | 0x0001; /* Use CSMA selector. */ + } else { + val = 0; + dev->cLinkDownReported++; + } + break; - case 6: - /* Auto negotiation expansion register. */ - if (pcnetIsLinkUp(dev) && !isolate) { - val = 0x0008 /* Link partner supports npage. */ - | 0x0004 /* Enable npage words. */ - | 0x0001; /* Can do N-way auto-negotiation. */ - } else { - val = 0; - dev->cLinkDownReported++; - } - break; + case 6: + /* Auto negotiation expansion register. */ + if (pcnetIsLinkUp(dev) && !isolate) { + val = 0x0008 /* Link partner supports npage. */ + | 0x0004 /* Enable npage words. */ + | 0x0001; /* Can do N-way auto-negotiation. */ + } else { + val = 0; + dev->cLinkDownReported++; + } + break; - case 18: - /* Diagnostic Register (FreeBSD pcn/ac101 driver reads this). */ - if (pcnetIsLinkUp(dev) && !isolate) { - val = 0x1000 /* Receive PLL locked. */ - | 0x0200; /* Signal detected. */ + case 18: + /* Diagnostic Register (FreeBSD pcn/ac101 driver reads this). */ + if (pcnetIsLinkUp(dev) && !isolate) { + val = 0x1000 /* Receive PLL locked. */ + | 0x0200; /* Signal detected. */ - if (autoneg) { - val |= 0x0400 /* 100Mbps rate. */ - | 0x0800; /* Full duplex. */ - } else { - if (fast) - val |= 0x0400; /* 100Mbps rate. */ - if (duplex) - val |= 0x0800; /* Full duplex. */ - } - } else { - val = 0; - dev->cLinkDownReported++; - } - break; + if (autoneg) { + val |= 0x0400 /* 100Mbps rate. */ + | 0x0800; /* Full duplex. */ + } else { + if (fast) + val |= 0x0400; /* 100Mbps rate. */ + if (duplex) + val |= 0x0800; /* Full duplex. */ + } + } else { + val = 0; + dev->cLinkDownReported++; + } + break; - default: - val = 0; - break; + default: + val = 0; + break; } return val; @@ -2196,44 +2161,43 @@ pcnet_bcr_readw(nic_t *dev, uint16_t rap) uint16_t val; rap &= 0x7f; switch (rap) { - case BCR_LNKST: - case BCR_LED1: - case BCR_LED2: - case BCR_LED3: - val = dev->aBCR[rap] & ~0x8000; - if (!(pcnetIsLinkUp(dev))) { - if (rap == 4) - dev->cLinkDownReported++; - val &= ~0x40; - } - val |= (val & 0x017f & dev->u32Lnkst) ? 0x8000 : 0; - break; + case BCR_LNKST: + case BCR_LED1: + case BCR_LED2: + case BCR_LED3: + val = dev->aBCR[rap] & ~0x8000; + if (!(pcnetIsLinkUp(dev))) { + if (rap == 4) + dev->cLinkDownReported++; + val &= ~0x40; + } + val |= (val & 0x017f & dev->u32Lnkst) ? 0x8000 : 0; + break; - case BCR_MIIMDR: - if ((dev->board == DEV_AM79C973) && (((dev->aBCR[BCR_MIIADDR] >> 5) & 0x1f) == 0)) { - uint16_t miiaddr = dev->aBCR[BCR_MIIADDR] & 0x1f; - val = pcnet_mii_readw(dev, miiaddr); - } else - val = 0xffff; - break; + case BCR_MIIMDR: + if ((dev->board == DEV_AM79C973) && (((dev->aBCR[BCR_MIIADDR] >> 5) & 0x1f) == 0)) { + uint16_t miiaddr = dev->aBCR[BCR_MIIADDR] & 0x1f; + val = pcnet_mii_readw(dev, miiaddr); + } else + val = 0xffff; + break; - case BCR_SWCONFIG: - if (dev->board == DEV_AM79C961) - val = ((dev->base_irq & 0x0f) << 4) | (dev->dma_channel & 0x07); - else - val = 0xffff; - break; + case BCR_SWCONFIG: + if (dev->board == DEV_AM79C961) + val = ((dev->base_irq & 0x0f) << 4) | (dev->dma_channel & 0x07); + else + val = 0xffff; + break; - default: - val = rap < BCR_MAX_RAP ? dev->aBCR[rap] : 0; - break; + default: + val = rap < BCR_MAX_RAP ? dev->aBCR[rap] : 0; + break; } pcnetlog(3, "pcnet_bcr_readw rap=%d val=0x%04x\n", rap, val); return val; } - static void pcnet_word_write(nic_t *dev, uint32_t addr, uint16_t val) { @@ -2241,18 +2205,18 @@ pcnet_word_write(nic_t *dev, uint32_t addr, uint16_t val) if (!BCR_DWIO(dev)) { switch (addr & 0x0f) { - case 0x00: /* RDP */ - timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC); - pcnet_csr_writew(dev, dev->u32RAP, val); - pcnetUpdateIrq(dev); - break; - case 0x02: - dev->u32RAP = val & 0x7f; - break; - case 0x06: - pcnet_bcr_writew(dev, dev->u32RAP, val); - break; - } + case 0x00: /* RDP */ + timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC); + pcnet_csr_writew(dev, dev->u32RAP, val); + pcnetUpdateIrq(dev); + break; + case 0x02: + dev->u32RAP = val & 0x7f; + break; + case 0x06: + pcnet_bcr_writew(dev, dev->u32RAP, val); + break; + } } } @@ -2262,19 +2226,19 @@ pcnet_byte_read(nic_t *dev, uint32_t addr) uint8_t val = 0xff; if (!BCR_DWIO(dev)) { - switch (addr & 0x0f) { - case 0x04: - pcnetSoftReset(dev); - val = 0; - break; - } + switch (addr & 0x0f) { + case 0x04: + pcnetSoftReset(dev); + val = 0; + break; + } } pcnetUpdateIrq(dev); pcnetlog(3, "%s: pcnet_word_read: addr = %04x, val = %04x, DWIO not set = %04x\n", dev->name, addr & 0x0f, val, !BCR_DWIO(dev)); - return(val); + return (val); } static uint16_t @@ -2283,28 +2247,28 @@ pcnet_word_read(nic_t *dev, uint32_t addr) uint16_t val = 0xffff; if (!BCR_DWIO(dev)) { - switch (addr & 0x0f) { - case 0x00: /* RDP */ - /** @note if we're not polling, then the guest will tell us when to poll by setting TDMD in CSR0 */ - /** Polling is then useless here and possibly expensive. */ - if (!CSR_DPOLL(dev)) - timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC); + switch (addr & 0x0f) { + case 0x00: /* RDP */ + /** @note if we're not polling, then the guest will tell us when to poll by setting TDMD in CSR0 */ + /** Polling is then useless here and possibly expensive. */ + if (!CSR_DPOLL(dev)) + timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC); - val = pcnet_csr_readw(dev, dev->u32RAP); - if (dev->u32RAP == 0) - goto skip_update_irq; - break; - case 0x02: - val = dev->u32RAP; - goto skip_update_irq; - case 0x04: - pcnetSoftReset(dev); - val = 0; - break; - case 0x06: - val = pcnet_bcr_readw(dev, dev->u32RAP); - break; - } + val = pcnet_csr_readw(dev, dev->u32RAP); + if (dev->u32RAP == 0) + goto skip_update_irq; + break; + case 0x02: + val = dev->u32RAP; + goto skip_update_irq; + case 0x04: + pcnetSoftReset(dev); + val = 0; + break; + case 0x06: + val = pcnet_bcr_readw(dev, dev->u32RAP); + break; + } } pcnetUpdateIrq(dev); @@ -2312,27 +2276,26 @@ pcnet_word_read(nic_t *dev, uint32_t addr) skip_update_irq: pcnetlog(3, "%s: pcnet_word_read: addr = %04x, val = %04x, DWIO not set = %04x\n", dev->name, addr & 0x0f, val, !BCR_DWIO(dev)); - return(val); + return (val); } - static void pcnet_dword_write(nic_t *dev, uint32_t addr, uint32_t val) { if (BCR_DWIO(dev)) { switch (addr & 0x0f) { - case 0x00: /* RDP */ - timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC); - pcnet_csr_writew(dev, dev->u32RAP, val & 0xffff); - pcnetUpdateIrq(dev); - break; - case 0x04: - dev->u32RAP = val & 0x7f; - break; - case 0x0c: - pcnet_bcr_writew(dev, dev->u32RAP, val & 0xffff); - break; - } + case 0x00: /* RDP */ + timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC); + pcnet_csr_writew(dev, dev->u32RAP, val & 0xffff); + pcnetUpdateIrq(dev); + break; + case 0x04: + dev->u32RAP = val & 0x7f; + break; + case 0x0c: + pcnet_bcr_writew(dev, dev->u32RAP, val & 0xffff); + break; + } } else if ((addr & 0x0f) == 0) { /* switch device to dword i/o mode */ pcnet_bcr_writew(dev, BCR_BSBC, pcnet_bcr_readw(dev, BCR_BSBC) | 0x0080); @@ -2340,42 +2303,40 @@ pcnet_dword_write(nic_t *dev, uint32_t addr, uint32_t val) }; } - static uint32_t pcnet_dword_read(nic_t *dev, uint32_t addr) { uint32_t val = 0xffffffff; if (BCR_DWIO(dev)) { - switch (addr & 0x0f) { - case 0x00: /* RDP */ - if (!CSR_DPOLL(dev)) - timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC); - val = pcnet_csr_readw(dev, dev->u32RAP); - if (dev->u32RAP == 0) - goto skip_update_irq; - break; - case 0x04: - val = dev->u32RAP; - goto skip_update_irq; - case 0x08: - pcnetSoftReset(dev); - val = 0; - break; - case 0x0c: - val = pcnet_bcr_readw(dev, dev->u32RAP); - break; - } + switch (addr & 0x0f) { + case 0x00: /* RDP */ + if (!CSR_DPOLL(dev)) + timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC); + val = pcnet_csr_readw(dev, dev->u32RAP); + if (dev->u32RAP == 0) + goto skip_update_irq; + break; + case 0x04: + val = dev->u32RAP; + goto skip_update_irq; + case 0x08: + pcnetSoftReset(dev); + val = 0; + break; + case 0x0c: + val = pcnet_bcr_readw(dev, dev->u32RAP); + break; + } } pcnetUpdateIrq(dev); skip_update_irq: pcnetlog(3, "%s: Read Long mode, addr = %08x, val = %08x\n", dev->name, addr, val); - return(val); + return (val); } - static void pcnet_aprom_writeb(nic_t *dev, uint32_t addr, uint32_t val) { @@ -2384,7 +2345,6 @@ pcnet_aprom_writeb(nic_t *dev, uint32_t addr, uint32_t val) dev->aPROM[addr & 0x0f] = val & 0xff; } - static uint32_t pcnet_aprom_readb(nic_t *dev, uint32_t addr) { @@ -2393,7 +2353,6 @@ pcnet_aprom_readb(nic_t *dev, uint32_t addr) return val; } - static void pcnet_write(nic_t *dev, uint32_t addr, uint32_t val, int len) { @@ -2402,379 +2361,363 @@ pcnet_write(nic_t *dev, uint32_t addr, uint32_t val, int len) pcnetlog(3, "%s: write addr %x, val %x, off %x, len %d\n", dev->name, addr, val, off, len); if (off < 0x10) { - if (!BCR_DWIO(dev) && len == 1) - pcnet_aprom_writeb(dev, addr, val); - else if (!BCR_DWIO(dev) && ((addr & 1) == 0) && len == 2) { - pcnet_aprom_writeb(dev, addr, val); - pcnet_aprom_writeb(dev, addr + 1, val >> 8); - } else if (BCR_DWIO(dev) && ((addr & 3) == 0) && len == 4) { - pcnet_aprom_writeb(dev, addr, val); - pcnet_aprom_writeb(dev, addr + 1, val >> 8); - pcnet_aprom_writeb(dev, addr + 2, val >> 16); - pcnet_aprom_writeb(dev, addr + 3, val >> 24); - } + if (!BCR_DWIO(dev) && len == 1) + pcnet_aprom_writeb(dev, addr, val); + else if (!BCR_DWIO(dev) && ((addr & 1) == 0) && len == 2) { + pcnet_aprom_writeb(dev, addr, val); + pcnet_aprom_writeb(dev, addr + 1, val >> 8); + } else if (BCR_DWIO(dev) && ((addr & 3) == 0) && len == 4) { + pcnet_aprom_writeb(dev, addr, val); + pcnet_aprom_writeb(dev, addr + 1, val >> 8); + pcnet_aprom_writeb(dev, addr + 2, val >> 16); + pcnet_aprom_writeb(dev, addr + 3, val >> 24); + } } else { - if (len == 2) - pcnet_word_write(dev, addr, val); - else if (len == 4) - pcnet_dword_write(dev, addr, val); + if (len == 2) + pcnet_word_write(dev, addr, val); + else if (len == 4) + pcnet_dword_write(dev, addr, val); } } - static void pcnet_writeb(uint16_t addr, uint8_t val, void *priv) { - pcnet_write((nic_t *)priv, addr, val, 1); + pcnet_write((nic_t *) priv, addr, val, 1); } - static void pcnet_writew(uint16_t addr, uint16_t val, void *priv) { - pcnet_write((nic_t *)priv, addr, val, 2); + pcnet_write((nic_t *) priv, addr, val, 2); } - static void pcnet_writel(uint16_t addr, uint32_t val, void *priv) { - pcnet_write((nic_t *)priv, addr, val, 4); + pcnet_write((nic_t *) priv, addr, val, 4); } - static uint32_t pcnet_read(nic_t *dev, uint32_t addr, int len) { uint32_t retval = 0xffffffff; - uint16_t off = addr & 0x1f; + uint16_t off = addr & 0x1f; pcnetlog(3, "%s: read addr %x, off %x, len %d\n", dev->name, addr, off, len); if (off < 0x10) { - if (!BCR_DWIO(dev) && len == 1) - retval = pcnet_aprom_readb(dev, addr); - else if (!BCR_DWIO(dev) && ((addr & 1) == 0) && len == 2) - retval = pcnet_aprom_readb(dev, addr) | (pcnet_aprom_readb(dev, addr + 1) << 8); - else if (BCR_DWIO(dev) && ((addr & 3) == 0) && len == 4) { - retval = pcnet_aprom_readb(dev, addr) | (pcnet_aprom_readb(dev, addr + 1) << 8) | - (pcnet_aprom_readb(dev, addr + 2) << 16) | (pcnet_aprom_readb(dev, addr + 3) << 24); - } + if (!BCR_DWIO(dev) && len == 1) + retval = pcnet_aprom_readb(dev, addr); + else if (!BCR_DWIO(dev) && ((addr & 1) == 0) && len == 2) + retval = pcnet_aprom_readb(dev, addr) | (pcnet_aprom_readb(dev, addr + 1) << 8); + else if (BCR_DWIO(dev) && ((addr & 3) == 0) && len == 4) { + retval = pcnet_aprom_readb(dev, addr) | (pcnet_aprom_readb(dev, addr + 1) << 8) | (pcnet_aprom_readb(dev, addr + 2) << 16) | (pcnet_aprom_readb(dev, addr + 3) << 24); + } } else { - if (len == 1) - retval = pcnet_byte_read(dev, addr); - else if (len == 2) - retval = pcnet_word_read(dev, addr); - else if (len == 4) - retval = pcnet_dword_read(dev, addr); + if (len == 1) + retval = pcnet_byte_read(dev, addr); + else if (len == 2) + retval = pcnet_word_read(dev, addr); + else if (len == 4) + retval = pcnet_dword_read(dev, addr); } pcnetlog(3, "%s: value in read - %08x\n", dev->name, retval); - return(retval); + return (retval); } - static uint8_t pcnet_readb(uint16_t addr, void *priv) { - return(pcnet_read((nic_t *)priv, addr, 1)); + return (pcnet_read((nic_t *) priv, addr, 1)); } - static uint16_t pcnet_readw(uint16_t addr, void *priv) { - return(pcnet_read((nic_t *)priv, addr, 2)); + return (pcnet_read((nic_t *) priv, addr, 2)); } - static uint32_t pcnet_readl(uint16_t addr, void *priv) { - return(pcnet_read((nic_t *)priv, addr, 4)); + return (pcnet_read((nic_t *) priv, addr, 4)); } - static void pcnet_mmio_writeb(uint32_t addr, uint8_t val, void *priv) { - pcnet_write((nic_t *)priv, addr, val, 1); + pcnet_write((nic_t *) priv, addr, val, 1); } - static void pcnet_mmio_writew(uint32_t addr, uint16_t val, void *priv) { - pcnet_write((nic_t *)priv, addr, val, 2); + pcnet_write((nic_t *) priv, addr, val, 2); } - static void pcnet_mmio_writel(uint32_t addr, uint32_t val, void *priv) { - pcnet_write((nic_t *)priv, addr, val, 4); + pcnet_write((nic_t *) priv, addr, val, 4); } - static uint8_t pcnet_mmio_readb(uint32_t addr, void *priv) { - return(pcnet_read((nic_t *)priv, addr, 1)); + return (pcnet_read((nic_t *) priv, addr, 1)); } - static uint16_t pcnet_mmio_readw(uint32_t addr, void *priv) { - return(pcnet_read((nic_t *)priv, addr, 2)); + return (pcnet_read((nic_t *) priv, addr, 2)); } - static uint32_t pcnet_mmio_readl(uint32_t addr, void *priv) { - return(pcnet_read((nic_t *)priv, addr, 4)); + return (pcnet_read((nic_t *) priv, addr, 4)); } - static void pcnet_mem_init(nic_t *dev, uint32_t addr) { mem_mapping_add(&dev->mmio_mapping, addr, 32, - pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl, - pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel, - NULL, MEM_MAPPING_EXTERNAL, dev); + pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl, + pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel, + NULL, MEM_MAPPING_EXTERNAL, dev); } - static void pcnet_mem_set_addr(nic_t *dev, uint32_t base) { mem_mapping_set_addr(&dev->mmio_mapping, base, 32); } - static void pcnet_mem_disable(nic_t *dev) { mem_mapping_disable(&dev->mmio_mapping); } - static void pcnet_ioremove(nic_t *dev, uint16_t addr, int len) { if (dev->is_pci || dev->is_vlb) { - io_removehandler(addr, len, - pcnet_readb, pcnet_readw, pcnet_readl, - pcnet_writeb, pcnet_writew, pcnet_writel, dev); + io_removehandler(addr, len, + pcnet_readb, pcnet_readw, pcnet_readl, + pcnet_writeb, pcnet_writew, pcnet_writel, dev); } else { - io_removehandler(addr, len, - pcnet_readb, pcnet_readw, NULL, - pcnet_writeb, pcnet_writew, NULL, dev); + io_removehandler(addr, len, + pcnet_readb, pcnet_readw, NULL, + pcnet_writeb, pcnet_writew, NULL, dev); } } - static void pcnet_ioset(nic_t *dev, uint16_t addr, int len) { pcnet_ioremove(dev, addr, len); if (dev->is_pci || dev->is_vlb) { - io_sethandler(addr, len, - pcnet_readb, pcnet_readw, pcnet_readl, - pcnet_writeb, pcnet_writew, pcnet_writel, dev); + io_sethandler(addr, len, + pcnet_readb, pcnet_readw, pcnet_readl, + pcnet_writeb, pcnet_writew, pcnet_writel, dev); } else { - io_sethandler(addr, len, - pcnet_readb, pcnet_readw, NULL, - pcnet_writeb, pcnet_writew, NULL, dev); + io_sethandler(addr, len, + pcnet_readb, pcnet_readw, NULL, + pcnet_writeb, pcnet_writew, NULL, dev); } } - static void pcnet_pci_write(int func, int addr, uint8_t val, void *p) { - nic_t *dev = (nic_t *)p; + nic_t *dev = (nic_t *) p; uint8_t valxor; pcnetlog(4, "%s: Write value %02X to register %02X\n", dev->name, val, addr & 0xff); switch (addr) { - case 0x04: - valxor = (val & 0x57) ^ pcnet_pci_regs[addr]; - if (valxor & PCI_COMMAND_IO) { - pcnet_ioremove(dev, dev->PCIBase, 32); - if ((dev->PCIBase != 0) && (val & PCI_COMMAND_IO)) - pcnet_ioset(dev, dev->PCIBase, 32); - } - if (valxor & PCI_COMMAND_MEM) { - pcnet_mem_disable(dev); - if ((dev->MMIOBase != 0) && (val & PCI_COMMAND_MEM)) - pcnet_mem_set_addr(dev, dev->MMIOBase); - } - pcnet_pci_regs[addr] = val & 0x57; - break; + case 0x04: + valxor = (val & 0x57) ^ pcnet_pci_regs[addr]; + if (valxor & PCI_COMMAND_IO) { + pcnet_ioremove(dev, dev->PCIBase, 32); + if ((dev->PCIBase != 0) && (val & PCI_COMMAND_IO)) + pcnet_ioset(dev, dev->PCIBase, 32); + } + if (valxor & PCI_COMMAND_MEM) { + pcnet_mem_disable(dev); + if ((dev->MMIOBase != 0) && (val & PCI_COMMAND_MEM)) + pcnet_mem_set_addr(dev, dev->MMIOBase); + } + pcnet_pci_regs[addr] = val & 0x57; + break; - case 0x05: - pcnet_pci_regs[addr] = val & 0x01; - break; + case 0x05: + pcnet_pci_regs[addr] = val & 0x01; + break; - case 0x0D: - pcnet_pci_regs[addr] = val; - break; + case 0x0D: + pcnet_pci_regs[addr] = val; + break; - case 0x10: case 0x11: case 0x12: case 0x13: - /* I/O Base set. */ - /* First, remove the old I/O. */ - pcnet_ioremove(dev, dev->PCIBase, 32); - /* Then let's set the PCI regs. */ - pcnet_pci_bar[0].addr_regs[addr & 3] = val; - /* Then let's calculate the new I/O base. */ - pcnet_pci_bar[0].addr &= 0xff00; - dev->PCIBase = pcnet_pci_bar[0].addr; - /* Log the new base. */ - pcnetlog(4, "%s: New I/O base is %04X\n" , dev->name, dev->PCIBase); - /* We're done, so get out of the here. */ - if (pcnet_pci_regs[4] & PCI_COMMAND_IO) { - if (dev->PCIBase != 0) - pcnet_ioset(dev, dev->PCIBase, 32); - } - return; + case 0x10: + case 0x11: + case 0x12: + case 0x13: + /* I/O Base set. */ + /* First, remove the old I/O. */ + pcnet_ioremove(dev, dev->PCIBase, 32); + /* Then let's set the PCI regs. */ + pcnet_pci_bar[0].addr_regs[addr & 3] = val; + /* Then let's calculate the new I/O base. */ + pcnet_pci_bar[0].addr &= 0xff00; + dev->PCIBase = pcnet_pci_bar[0].addr; + /* Log the new base. */ + pcnetlog(4, "%s: New I/O base is %04X\n", dev->name, dev->PCIBase); + /* We're done, so get out of the here. */ + if (pcnet_pci_regs[4] & PCI_COMMAND_IO) { + if (dev->PCIBase != 0) + pcnet_ioset(dev, dev->PCIBase, 32); + } + return; - case 0x15: case 0x16: case 0x17: - /* MMIO Base set. */ - /* First, remove the old I/O. */ - pcnet_mem_disable(dev); - /* Then let's set the PCI regs. */ - pcnet_pci_bar[1].addr_regs[addr & 3] = val; - /* Then let's calculate the new I/O base. */ - pcnet_pci_bar[1].addr &= 0xffffc000; - dev->MMIOBase = pcnet_pci_bar[1].addr & 0xffffc000; - /* Log the new base. */ - pcnetlog(4, "%s: New MMIO base is %08X\n" , dev->name, dev->MMIOBase); - /* We're done, so get out of the here. */ - if (pcnet_pci_regs[4] & PCI_COMMAND_MEM) { - if (dev->MMIOBase != 0) - pcnet_mem_set_addr(dev, dev->MMIOBase); - } - return; + case 0x15: + case 0x16: + case 0x17: + /* MMIO Base set. */ + /* First, remove the old I/O. */ + pcnet_mem_disable(dev); + /* Then let's set the PCI regs. */ + pcnet_pci_bar[1].addr_regs[addr & 3] = val; + /* Then let's calculate the new I/O base. */ + pcnet_pci_bar[1].addr &= 0xffffc000; + dev->MMIOBase = pcnet_pci_bar[1].addr & 0xffffc000; + /* Log the new base. */ + pcnetlog(4, "%s: New MMIO base is %08X\n", dev->name, dev->MMIOBase); + /* We're done, so get out of the here. */ + if (pcnet_pci_regs[4] & PCI_COMMAND_MEM) { + if (dev->MMIOBase != 0) + pcnet_mem_set_addr(dev, dev->MMIOBase); + } + return; - case 0x3C: - dev->base_irq = val; - pcnet_pci_regs[addr] = val; - return; + case 0x3C: + dev->base_irq = val; + pcnet_pci_regs[addr] = val; + return; } } - static uint8_t pcnet_pci_read(int func, int addr, void *p) { - nic_t *dev = (nic_t *)p; + nic_t *dev = (nic_t *) p; pcnetlog(4, "%s: Read to register %02X\n", dev->name, addr & 0xff); switch (addr) { - case 0x00: - return 0x22; - case 0x01: - return 0x10; - case 0x02: - return 0x00; - case 0x03: - return 0x20; - case 0x04: - return pcnet_pci_regs[0x04] & 0x57; /*Respond to IO and memory accesses*/ - case 0x05: - return pcnet_pci_regs[0x05] & 0x01; - case 0x06: - return 0x80; - case 0x07: - return 2; - case 0x08: - return (dev->board == DEV_AM79C973) ? 0x40 : 0x10; /*Revision ID*/ - case 0x09: - return 0; /*Programming interface*/ - case 0x0A: - return 0; /*devubclass*/ - case 0x0B: - return 2; /*Class code*/ - case 0x0D: - return pcnet_pci_regs[addr]; - case 0x0E: - return 0; /*Header type */ - case 0x10: - return 1; /*I/O space*/ - case 0x11: - return pcnet_pci_bar[0].addr_regs[1]; - case 0x12: - return pcnet_pci_bar[0].addr_regs[2]; - case 0x13: - return pcnet_pci_bar[0].addr_regs[3]; - case 0x14: - return 0; /*Memory space*/ - case 0x15: - return pcnet_pci_bar[1].addr_regs[1]; - case 0x16: - return pcnet_pci_bar[1].addr_regs[2]; - case 0x17: - return pcnet_pci_bar[1].addr_regs[3]; - case 0x2C: - return 0x22; - case 0x2D: - return 0x10; - case 0x2E: - return 0x00; - case 0x2F: - return 0x20; - case 0x3C: - return dev->base_irq; - case 0x3D: - return PCI_INTA; - case 0x3E: - return 0x06; - case 0x3F: - return 0xff; + case 0x00: + return 0x22; + case 0x01: + return 0x10; + case 0x02: + return 0x00; + case 0x03: + return 0x20; + case 0x04: + return pcnet_pci_regs[0x04] & 0x57; /*Respond to IO and memory accesses*/ + case 0x05: + return pcnet_pci_regs[0x05] & 0x01; + case 0x06: + return 0x80; + case 0x07: + return 2; + case 0x08: + return (dev->board == DEV_AM79C973) ? 0x40 : 0x10; /*Revision ID*/ + case 0x09: + return 0; /*Programming interface*/ + case 0x0A: + return 0; /*devubclass*/ + case 0x0B: + return 2; /*Class code*/ + case 0x0D: + return pcnet_pci_regs[addr]; + case 0x0E: + return 0; /*Header type */ + case 0x10: + return 1; /*I/O space*/ + case 0x11: + return pcnet_pci_bar[0].addr_regs[1]; + case 0x12: + return pcnet_pci_bar[0].addr_regs[2]; + case 0x13: + return pcnet_pci_bar[0].addr_regs[3]; + case 0x14: + return 0; /*Memory space*/ + case 0x15: + return pcnet_pci_bar[1].addr_regs[1]; + case 0x16: + return pcnet_pci_bar[1].addr_regs[2]; + case 0x17: + return pcnet_pci_bar[1].addr_regs[3]; + case 0x2C: + return 0x22; + case 0x2D: + return 0x10; + case 0x2E: + return 0x00; + case 0x2F: + return 0x20; + case 0x3C: + return dev->base_irq; + case 0x3D: + return PCI_INTA; + case 0x3E: + return 0x06; + case 0x3F: + return 0xff; } - return(0); + return (0); } static void pcnet_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv) { if (ld) - return; + return; nic_t *dev = (nic_t *) priv; dev->base_address = 0; - dev->base_irq = 0; - dev->dma_channel = -1; + dev->base_irq = 0; + dev->dma_channel = -1; if (dev->base_address) { - pcnet_ioremove(dev, dev->base_address, 0x20); - dev->base_address = 0; + pcnet_ioremove(dev, dev->base_address, 0x20); + dev->base_address = 0; } if (config->activate) { - dev->base_address = config->io[0].base; - if (dev->base_address != ISAPNP_IO_DISABLED) - pcnet_ioset(dev, dev->base_address, 0x20); + dev->base_address = config->io[0].base; + if (dev->base_address != ISAPNP_IO_DISABLED) + pcnet_ioset(dev, dev->base_address, 0x20); - dev->base_irq = config->irq[0].irq; - dev->dma_channel = config->dma[0].dma; - if (dev->dma_channel == ISAPNP_DMA_DISABLED) - dev->dma_channel = -1; + dev->base_irq = config->irq[0].irq; + dev->dma_channel = config->dma[0].dma; + if (dev->dma_channel == ISAPNP_DMA_DISABLED) + dev->dma_channel = -1; - /* Update PnP register mirrors in ROM. */ - dev->aPROM[32] = dev->base_address >> 8; - dev->aPROM[33] = dev->base_address; - dev->aPROM[34] = dev->base_irq; - dev->aPROM[35] = (config->irq[0].level << 1) | config->irq[0].type; - dev->aPROM[36] = (dev->dma_channel == -1) ? ISAPNP_DMA_DISABLED : dev->dma_channel; + /* Update PnP register mirrors in ROM. */ + dev->aPROM[32] = dev->base_address >> 8; + dev->aPROM[33] = dev->base_address; + dev->aPROM[34] = dev->base_irq; + dev->aPROM[35] = (config->irq[0].level << 1) | config->irq[0].type; + dev->aPROM[36] = (dev->dma_channel == -1) ? ISAPNP_DMA_DISABLED : dev->dma_channel; } } @@ -2784,21 +2727,21 @@ pcnet_pnp_read_vendor_reg(uint8_t ld, uint8_t reg, void *priv) nic_t *dev = (nic_t *) priv; if (!ld && (reg == 0xf0)) - return dev->aPROM[50]; + return dev->aPROM[50]; else - return 0x00; + return 0x00; } static void pcnet_pnp_write_vendor_reg(uint8_t ld, uint8_t reg, uint8_t val, void *priv) { if (ld) - return; + return; nic_t *dev = (nic_t *) priv; if (reg == 0xf0) - dev->aPROM[50] = val & 0x1f; + dev->aPROM[50] = val & 0x1f; } /** @@ -2816,7 +2759,7 @@ static void pcnetTempLinkDown(nic_t *dev) { if (dev->fLinkUp) { - dev->fLinkTempDown = 1; + dev->fLinkTempDown = 1; dev->cLinkDownReported = 0; dev->aCSR[0] |= 0x8000 | 0x2000; /* ERR | CERR (this is probably wrong) */ timer_set_delay_u64(&dev->timer_restore, (dev->cMsLinkUpDelay * 1000) * TIMER_USEC); @@ -2846,7 +2789,7 @@ pcnetCanReceive(nic_t *dev) if (dev->fSignalRxMiss) dev->aCSR[0] |= 0x1000; /* Set MISS flag */ } else - rc = 1; + rc = 1; } return rc; @@ -2895,12 +2838,12 @@ pcnetTimerRestore(void *priv) nic_t *dev = (nic_t *) priv; if (dev->cLinkDownReported <= PCNET_MAX_LINKDOWN_REPORTED) { - timer_advance_u64(&dev->timer_restore, 1500000 * TIMER_USEC); + timer_advance_u64(&dev->timer_restore, 1500000 * TIMER_USEC); } else { - dev->fLinkTempDown = 0; - if (dev->fLinkUp) { - dev->aCSR[0] &= ~(0x8000 | 0x2000); /* ERR | CERR - probably not 100% correct either... */ - } + dev->fLinkTempDown = 0; + if (dev->fLinkUp) { + dev->aCSR[0] &= ~(0x8000 | 0x2000); /* ERR | CERR - probably not 100% correct either... */ + } } } @@ -2908,13 +2851,13 @@ static void * pcnet_init(const device_t *info) { uint32_t mac; - nic_t *dev; - int c; + nic_t *dev; + int c; uint16_t checksum; dev = malloc(sizeof(nic_t)); memset(dev, 0x00, sizeof(nic_t)); - dev->name = info->name; + dev->name = info->name; dev->board = info->local; dev->is_pci = !!(info->flags & DEVICE_PCI); @@ -2922,26 +2865,26 @@ pcnet_init(const device_t *info) dev->is_isa = !!(info->flags & (DEVICE_ISA | DEVICE_AT)); if (dev->is_pci || dev->is_vlb) - dev->transfer_size = 4; + dev->transfer_size = 4; else - dev->transfer_size = 2; + dev->transfer_size = 2; if (dev->is_pci) { - pcnet_mem_init(dev, 0x0fffff00); - pcnet_mem_disable(dev); + pcnet_mem_init(dev, 0x0fffff00); + pcnet_mem_disable(dev); } - dev->fLinkUp = 1; + dev->fLinkUp = 1; dev->cMsLinkUpDelay = 5000; if (dev->board == DEV_AM79C960_EB) { - dev->maclocal[0] = 0x02; /* 02:07:01 (Racal OID) */ - dev->maclocal[1] = 0x07; - dev->maclocal[2] = 0x01; + dev->maclocal[0] = 0x02; /* 02:07:01 (Racal OID) */ + dev->maclocal[1] = 0x07; + dev->maclocal[2] = 0x01; } else { - dev->maclocal[0] = 0x00; /* 00:0C:87 (AMD OID) */ - dev->maclocal[1] = 0x0C; - dev->maclocal[2] = 0x87; + dev->maclocal[0] = 0x00; /* 00:0C:87 (AMD OID) */ + dev->maclocal[1] = 0x0C; + dev->maclocal[2] = 0x87; } /* See if we have a local MAC address configured. */ @@ -2949,18 +2892,18 @@ pcnet_init(const device_t *info) /* Set up our BIA. */ if (mac & 0xff000000) { - /* Generate new local MAC. */ - dev->maclocal[3] = random_generate(); - dev->maclocal[4] = random_generate(); - dev->maclocal[5] = random_generate(); - mac = (((int) dev->maclocal[3]) << 16); - mac |= (((int) dev->maclocal[4]) << 8); - mac |= ((int) dev->maclocal[5]); - device_set_config_mac("mac", mac); + /* Generate new local MAC. */ + dev->maclocal[3] = random_generate(); + dev->maclocal[4] = random_generate(); + dev->maclocal[5] = random_generate(); + mac = (((int) dev->maclocal[3]) << 16); + mac |= (((int) dev->maclocal[4]) << 8); + mac |= ((int) dev->maclocal[5]); + device_set_config_mac("mac", mac); } else { - dev->maclocal[3] = (mac>>16) & 0xff; - dev->maclocal[4] = (mac>>8) & 0xff; - dev->maclocal[5] = (mac & 0xff); + dev->maclocal[3] = (mac >> 16) & 0xff; + dev->maclocal[4] = (mac >> 8) & 0xff; + dev->maclocal[5] = (mac & 0xff); } memcpy(dev->aPROM, dev->maclocal, sizeof(dev->maclocal)); @@ -2974,85 +2917,85 @@ pcnet_init(const device_t *info) /* Hardware ID: must be 11h if compatibility to AMD drivers is desired */ /* 0x00/0xFF=ISA, 0x01=PnP, 0x10=VLB, 0x11=PCI */ if (dev->is_pci) - dev->aPROM[9] = 0x11; + dev->aPROM[9] = 0x11; else if (dev->is_vlb) - dev->aPROM[9] = 0x10; + dev->aPROM[9] = 0x10; else if (dev->board == DEV_AM79C961) - dev->aPROM[9] = 0x01; + dev->aPROM[9] = 0x01; else - dev->aPROM[9] = 0x00; + dev->aPROM[9] = 0x00; /* User programmable space, init with 0 */ dev->aPROM[10] = dev->aPROM[11] = 0x00; if (dev->board == DEV_AM79C960_EB) { dev->aPROM[14] = 0x52; - dev->aPROM[15] = 0x44; /* NI6510 EtherBlaster 'RD' signature. */ + dev->aPROM[15] = 0x44; /* NI6510 EtherBlaster 'RD' signature. */ } else { - /* Must be ASCII W (57h) if compatibility to AMD - driver software is desired */ - dev->aPROM[14] = dev->aPROM[15] = 0x57; + /* Must be ASCII W (57h) if compatibility to AMD + driver software is desired */ + dev->aPROM[14] = dev->aPROM[15] = 0x57; } for (c = 0, checksum = 0; c < 16; c++) - checksum += dev->aPROM[c]; + checksum += dev->aPROM[c]; - *(uint16_t *)&dev->aPROM[12] = cpu_to_le16(checksum); + *(uint16_t *) &dev->aPROM[12] = cpu_to_le16(checksum); /* * Make this device known to the I/O system. * PCI devices start with address spaces inactive. */ if (dev->is_pci) { - /* - * Configure the PCI space registers. - * - * We do this here, so the I/O routines are generic. - */ + /* + * Configure the PCI space registers. + * + * We do this here, so the I/O routines are generic. + */ - /* Enable our address space in PCI. */ - pcnet_pci_bar[0].addr_regs[0] = 1; - pcnet_pci_bar[1].addr_regs[0] = 0; - pcnet_pci_regs[0x04] = 3; + /* Enable our address space in PCI. */ + pcnet_pci_bar[0].addr_regs[0] = 1; + pcnet_pci_bar[1].addr_regs[0] = 0; + pcnet_pci_regs[0x04] = 3; - /* Add device to the PCI bus, keep its slot number. */ - dev->card = pci_add_card(PCI_ADD_NORMAL, - pcnet_pci_read, pcnet_pci_write, dev); + /* Add device to the PCI bus, keep its slot number. */ + dev->card = pci_add_card(PCI_ADD_NORMAL, + pcnet_pci_read, pcnet_pci_write, dev); } else if (dev->board == DEV_AM79C961) { - dev->dma_channel = -1; + dev->dma_channel = -1; - /* Weird secondary checksum. The datasheet isn't clear on what - role it might play with the PnP register mirrors before it. */ - for (c = 0, checksum = 0; c < 54; c++) - checksum += dev->aPROM[c]; + /* Weird secondary checksum. The datasheet isn't clear on what + role it might play with the PnP register mirrors before it. */ + for (c = 0, checksum = 0; c < 54; c++) + checksum += dev->aPROM[c]; - dev->aPROM[51] = checksum; + dev->aPROM[51] = checksum; - memcpy(&dev->aPROM[0x40], am79c961_pnp_rom, sizeof(am79c961_pnp_rom)); - isapnp_add_card(&dev->aPROM[0x40], sizeof(am79c961_pnp_rom), pcnet_pnp_config_changed, NULL, pcnet_pnp_read_vendor_reg, pcnet_pnp_write_vendor_reg, dev); + memcpy(&dev->aPROM[0x40], am79c961_pnp_rom, sizeof(am79c961_pnp_rom)); + isapnp_add_card(&dev->aPROM[0x40], sizeof(am79c961_pnp_rom), pcnet_pnp_config_changed, NULL, pcnet_pnp_read_vendor_reg, pcnet_pnp_write_vendor_reg, dev); } else { - dev->base_address = device_get_config_hex16("base"); - dev->base_irq = device_get_config_int("irq"); - if (dev->is_vlb) - dev->dma_channel = -1; - else - dev->dma_channel = device_get_config_int("dma"); - pcnet_ioset(dev, dev->base_address, 0x20); + dev->base_address = device_get_config_hex16("base"); + dev->base_irq = device_get_config_int("irq"); + if (dev->is_vlb) + dev->dma_channel = -1; + else + dev->dma_channel = device_get_config_int("dma"); + pcnet_ioset(dev, dev->base_address, 0x20); } pcnetlog(2, "%s: I/O=%04x, IRQ=%d, MAC=%02x:%02x:%02x:%02x:%02x:%02x\n", - dev->name, dev->base_address, dev->base_irq, - dev->aPROM[0], dev->aPROM[1], dev->aPROM[2], - dev->aPROM[3], dev->aPROM[4], dev->aPROM[5]); + dev->name, dev->base_address, dev->base_irq, + dev->aPROM[0], dev->aPROM[1], dev->aPROM[2], + dev->aPROM[3], dev->aPROM[4], dev->aPROM[5]); pcnetlog(1, "%s: %s attached IO=0x%X IRQ=%d\n", dev->name, - dev->is_pci?"PCI":"VLB/ISA", dev->base_address, dev->base_irq); + dev->is_pci ? "PCI" : "VLB/ISA", dev->base_address, dev->base_irq); /* Reset the board. */ pcnetHardReset(dev); /* Attach ourselves to the network module. */ - dev->netcard = network_attach(dev, dev->aPROM, pcnetReceiveNoSync, pcnetSetLinkState); + dev->netcard = network_attach(dev, dev->aPROM, pcnetReceiveNoSync, pcnetSetLinkState); dev->netcard->byte_period = (dev->board == DEV_AM79C973) ? NET_PERIOD_100M : NET_PERIOD_10M; timer_add(&dev->timer, pcnetPollTimer, dev, 0); @@ -3062,23 +3005,21 @@ pcnet_init(const device_t *info) timer_add(&dev->timer_restore, pcnetTimerRestore, dev, 0); - return(dev); + return (dev); } - static void pcnet_close(void *priv) { - nic_t *dev = (nic_t *)priv; + nic_t *dev = (nic_t *) priv; pcnetlog(1, "%s: closed\n", dev->name); netcard_close(dev->netcard); if (dev) { - free(dev); - dev = NULL; - + free(dev); + dev = NULL; } } @@ -3198,85 +3139,85 @@ static const device_config_t pcnet_vlb_config[] = { // clang-format on const device_t pcnet_am79c960_device = { - .name = "AMD PCnet-ISA", + .name = "AMD PCnet-ISA", .internal_name = "pcnetisa", - .flags = DEVICE_AT | DEVICE_ISA, - .local = DEV_AM79C960, - .init = pcnet_init, - .close = pcnet_close, - .reset = NULL, + .flags = DEVICE_AT | DEVICE_ISA, + .local = DEV_AM79C960, + .init = pcnet_init, + .close = pcnet_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = pcnet_isa_config + .force_redraw = NULL, + .config = pcnet_isa_config }; const device_t pcnet_am79c960_eb_device = { - .name = "Racal Interlan EtherBlaster", + .name = "Racal Interlan EtherBlaster", .internal_name = "pcnetracal", - .flags = DEVICE_AT | DEVICE_ISA, - .local = DEV_AM79C960_EB, - .init = pcnet_init, - .close = pcnet_close, - .reset = NULL, + .flags = DEVICE_AT | DEVICE_ISA, + .local = DEV_AM79C960_EB, + .init = pcnet_init, + .close = pcnet_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = pcnet_isa_config + .force_redraw = NULL, + .config = pcnet_isa_config }; const device_t pcnet_am79c960_vlb_device = { - .name = "AMD PCnet-VL", + .name = "AMD PCnet-VL", .internal_name = "pcnetvlb", - .flags = DEVICE_VLB, - .local = DEV_AM79C960_VLB, - .init = pcnet_init, - .close = pcnet_close, - .reset = NULL, + .flags = DEVICE_VLB, + .local = DEV_AM79C960_VLB, + .init = pcnet_init, + .close = pcnet_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = pcnet_vlb_config + .force_redraw = NULL, + .config = pcnet_vlb_config }; const device_t pcnet_am79c961_device = { - .name = "AMD PCnet-ISA+", + .name = "AMD PCnet-ISA+", .internal_name = "pcnetisaplus", - .flags = DEVICE_AT | DEVICE_ISA, - .local = DEV_AM79C961, - .init = pcnet_init, - .close = pcnet_close, - .reset = NULL, + .flags = DEVICE_AT | DEVICE_ISA, + .local = DEV_AM79C961, + .init = pcnet_init, + .close = pcnet_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = pcnet_pci_config + .force_redraw = NULL, + .config = pcnet_pci_config }; const device_t pcnet_am79c970a_device = { - .name = "AMD PCnet-PCI II", + .name = "AMD PCnet-PCI II", .internal_name = "pcnetpci", - .flags = DEVICE_PCI, - .local = DEV_AM79C970A, - .init = pcnet_init, - .close = pcnet_close, - .reset = NULL, + .flags = DEVICE_PCI, + .local = DEV_AM79C970A, + .init = pcnet_init, + .close = pcnet_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = pcnet_pci_config + .force_redraw = NULL, + .config = pcnet_pci_config }; const device_t pcnet_am79c973_device = { - .name = "AMD PCnet-FAST III", + .name = "AMD PCnet-FAST III", .internal_name = "pcnetfast", - .flags = DEVICE_PCI, - .local = DEV_AM79C973, - .init = pcnet_init, - .close = pcnet_close, - .reset = NULL, + .flags = DEVICE_PCI, + .local = DEV_AM79C973, + .init = pcnet_init, + .close = pcnet_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = pcnet_pci_config + .force_redraw = NULL, + .config = pcnet_pci_config }; diff --git a/src/network/net_plip.c b/src/network/net_plip.c index 9372e8022..158e64764 100644 --- a/src/network/net_plip.c +++ b/src/network/net_plip.c @@ -36,9 +36,8 @@ #include <86box/network.h> #include <86box/net_plip.h> - enum { - PLIP_START = 0x00, + PLIP_START = 0x00, PLIP_TX_LEN_LSB_LOW = 0x10, PLIP_TX_LEN_LSB_HIGH, PLIP_TX_LEN_MSB_LOW, @@ -60,26 +59,24 @@ enum { typedef struct { - uint8_t mac[6]; + uint8_t mac[6]; - void *lpt; - pc_timer_t rx_timer; - pc_timer_t timeout_timer; - uint8_t status, ctrl; + void *lpt; + pc_timer_t rx_timer; + pc_timer_t timeout_timer; + uint8_t status, ctrl; - uint8_t state, ack, tx_checksum, tx_checksum_calc, *tx_pkt; - uint16_t tx_len, tx_ptr; + uint8_t state, ack, tx_checksum, tx_checksum_calc, *tx_pkt; + uint16_t tx_len, tx_ptr; - uint8_t *rx_pkt, rx_checksum, rx_return_state; - uint16_t rx_len, rx_ptr; + uint8_t *rx_pkt, rx_checksum, rx_return_state; + uint16_t rx_len, rx_ptr; netcard_t *card; } plip_t; +static void plip_receive_packet(plip_t *dev); -static void plip_receive_packet(plip_t *dev); - -plip_t *instance; - +plip_t *instance; #ifdef ENABLE_PLIP_LOG int plip_do_log = ENABLE_PLIP_LOG; @@ -90,16 +87,15 @@ plip_log(uint8_t lvl, const char *fmt, ...) va_list ap; if (plip_do_log >= lvl) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define plip_log(lvl, fmt, ...) +# define plip_log(lvl, fmt, ...) #endif - static void timeout_timer(void *priv) { @@ -108,22 +104,21 @@ timeout_timer(void *priv) plip_log(1, "PLIP: timeout at state %d status %02X\n", dev->state, dev->status); /* Throw everything out the window. */ - dev->state = PLIP_START; + dev->state = PLIP_START; dev->status = 0x80; if (dev->tx_pkt) { - free(dev->tx_pkt); - dev->tx_pkt = NULL; + free(dev->tx_pkt); + dev->tx_pkt = NULL; } if (dev->rx_pkt) { - free(dev->rx_pkt); - dev->rx_pkt = NULL; + free(dev->rx_pkt); + dev->rx_pkt = NULL; } timer_disable(&dev->timeout_timer); } - static void plip_write_data(uint8_t val, void *priv) { @@ -132,220 +127,219 @@ plip_write_data(uint8_t val, void *priv) plip_log(3, "PLIP: write_data(%02X)\n", val); switch (dev->state) { - case PLIP_START: - if (val == 0x08) { /* D3/ACK wakes us up */ - plip_log(2, "PLIP: ACK wakeup\n"); - dev->state = PLIP_TX_LEN_LSB_LOW; - dev->status = 0x08; - break; - } - return; + case PLIP_START: + if (val == 0x08) { /* D3/ACK wakes us up */ + plip_log(2, "PLIP: ACK wakeup\n"); + dev->state = PLIP_TX_LEN_LSB_LOW; + dev->status = 0x08; + break; + } + return; - case PLIP_TX_LEN_LSB_LOW: - if (!(val & 0x10)) - return; /* D4/BUSY not high yet */ - dev->tx_len = val & 0xf; - plip_log(2, "PLIP: tx_len = %04X (1/4)\n", dev->tx_len); - dev->state = PLIP_TX_LEN_LSB_HIGH; - dev->status &= ~0x88; - break; + case PLIP_TX_LEN_LSB_LOW: + if (!(val & 0x10)) + return; /* D4/BUSY not high yet */ + dev->tx_len = val & 0xf; + plip_log(2, "PLIP: tx_len = %04X (1/4)\n", dev->tx_len); + dev->state = PLIP_TX_LEN_LSB_HIGH; + dev->status &= ~0x88; + break; - case PLIP_TX_LEN_LSB_HIGH: - if (val & 0x10) - return; /* D4/BUSY not low yet */ - dev->tx_len |= (val & 0xf) << 4; - plip_log(2, "PLIP: tx_len = %04X (2/4)\n", dev->tx_len); - dev->state = PLIP_TX_LEN_MSB_LOW; - dev->status |= 0x80; - break; + case PLIP_TX_LEN_LSB_HIGH: + if (val & 0x10) + return; /* D4/BUSY not low yet */ + dev->tx_len |= (val & 0xf) << 4; + plip_log(2, "PLIP: tx_len = %04X (2/4)\n", dev->tx_len); + dev->state = PLIP_TX_LEN_MSB_LOW; + dev->status |= 0x80; + break; - case PLIP_TX_LEN_MSB_LOW: - if (!(val & 0x10)) - return; /* D4/BUSY not high yet */ - dev->tx_len |= (val & 0xf) << 8; - plip_log(2, "PLIP: tx_len = %04X (3/4)\n", dev->tx_len); - dev->state = PLIP_TX_LEN_MSB_HIGH; - dev->status &= ~0x80; - break; + case PLIP_TX_LEN_MSB_LOW: + if (!(val & 0x10)) + return; /* D4/BUSY not high yet */ + dev->tx_len |= (val & 0xf) << 8; + plip_log(2, "PLIP: tx_len = %04X (3/4)\n", dev->tx_len); + dev->state = PLIP_TX_LEN_MSB_HIGH; + dev->status &= ~0x80; + break; - case PLIP_TX_LEN_MSB_HIGH: - if (val & 0x10) - return; /* D4/BUSY not low yet */ - dev->tx_len |= (val & 0xf) << 12; - plip_log(2, "PLIP: tx_len = %04X (4/4)\n", dev->tx_len); + case PLIP_TX_LEN_MSB_HIGH: + if (val & 0x10) + return; /* D4/BUSY not low yet */ + dev->tx_len |= (val & 0xf) << 12; + plip_log(2, "PLIP: tx_len = %04X (4/4)\n", dev->tx_len); - /* We have the length, allocate a packet. */ - if (!(dev->tx_pkt = malloc(dev->tx_len))) /* unlikely */ - fatal("PLIP: unable to allocate tx_pkt\n"); - dev->tx_ptr = 0; - dev->tx_checksum_calc = 0; + /* We have the length, allocate a packet. */ + if (!(dev->tx_pkt = malloc(dev->tx_len))) /* unlikely */ + fatal("PLIP: unable to allocate tx_pkt\n"); + dev->tx_ptr = 0; + dev->tx_checksum_calc = 0; - dev->state = PLIP_TX_DATA_LOW; - dev->status |= 0x80; - break; + dev->state = PLIP_TX_DATA_LOW; + dev->status |= 0x80; + break; - case PLIP_TX_DATA_LOW: - if (!(val & 0x10)) - return; /* D4/BUSY not high yet */ - dev->tx_pkt[dev->tx_ptr] = val & 0x0f; - plip_log(2, "PLIP: tx_pkt[%d] = %02X (1/2)\n", dev->tx_ptr, dev->tx_pkt[dev->tx_ptr]); - dev->state = PLIP_TX_DATA_HIGH; - dev->status &= ~0x80; - break; + case PLIP_TX_DATA_LOW: + if (!(val & 0x10)) + return; /* D4/BUSY not high yet */ + dev->tx_pkt[dev->tx_ptr] = val & 0x0f; + plip_log(2, "PLIP: tx_pkt[%d] = %02X (1/2)\n", dev->tx_ptr, dev->tx_pkt[dev->tx_ptr]); + dev->state = PLIP_TX_DATA_HIGH; + dev->status &= ~0x80; + break; - case PLIP_TX_DATA_HIGH: - if (val & 0x10) - return; /* D4/BUSY not low yet */ - dev->tx_pkt[dev->tx_ptr] |= (val & 0x0f) << 4; - plip_log(2, "PLIP: tx_pkt[%d] = %02X (2/2)\n", dev->tx_ptr, dev->tx_pkt[dev->tx_ptr]); - dev->tx_checksum_calc += dev->tx_pkt[dev->tx_ptr++]; + case PLIP_TX_DATA_HIGH: + if (val & 0x10) + return; /* D4/BUSY not low yet */ + dev->tx_pkt[dev->tx_ptr] |= (val & 0x0f) << 4; + plip_log(2, "PLIP: tx_pkt[%d] = %02X (2/2)\n", dev->tx_ptr, dev->tx_pkt[dev->tx_ptr]); + dev->tx_checksum_calc += dev->tx_pkt[dev->tx_ptr++]; - /* Are we done yet? */ - if (dev->tx_ptr < dev->tx_len) /* no, receive another byte */ - dev->state = PLIP_TX_DATA_LOW; - else /* yes, move on to checksum */ - dev->state = PLIP_TX_CHECKSUM_LOW; - dev->status |= 0x80; - break; + /* Are we done yet? */ + if (dev->tx_ptr < dev->tx_len) /* no, receive another byte */ + dev->state = PLIP_TX_DATA_LOW; + else /* yes, move on to checksum */ + dev->state = PLIP_TX_CHECKSUM_LOW; + dev->status |= 0x80; + break; - case PLIP_TX_CHECKSUM_LOW: - if (!(val & 0x10)) - return; /* D4/BUSY not high yet */ - dev->tx_checksum = val & 0x0f; - plip_log(2, "PLIP: tx_checksum = %02X (1/2)\n", dev->tx_checksum); - dev->state = PLIP_TX_CHECKSUM_HIGH; - dev->status &= ~0x80; - break; + case PLIP_TX_CHECKSUM_LOW: + if (!(val & 0x10)) + return; /* D4/BUSY not high yet */ + dev->tx_checksum = val & 0x0f; + plip_log(2, "PLIP: tx_checksum = %02X (1/2)\n", dev->tx_checksum); + dev->state = PLIP_TX_CHECKSUM_HIGH; + dev->status &= ~0x80; + break; - case PLIP_TX_CHECKSUM_HIGH: - if (val & 0x10) - return; /* D4/BUSY not low yet */ - dev->tx_checksum |= (val & 0x0f) << 4; - plip_log(2, "PLIP: tx_checksum = %02X (2/2)\n", dev->tx_checksum); + case PLIP_TX_CHECKSUM_HIGH: + if (val & 0x10) + return; /* D4/BUSY not low yet */ + dev->tx_checksum |= (val & 0x0f) << 4; + plip_log(2, "PLIP: tx_checksum = %02X (2/2)\n", dev->tx_checksum); - /* Verify checksum. */ - if (dev->tx_checksum_calc == dev->tx_checksum) { - /* Make sure we know the other end's MAC address. */ - memcpy(dev->mac, dev->tx_pkt + 6, 6); + /* Verify checksum. */ + if (dev->tx_checksum_calc == dev->tx_checksum) { + /* Make sure we know the other end's MAC address. */ + memcpy(dev->mac, dev->tx_pkt + 6, 6); - /* Transmit packet. */ - plip_log(2, "PLIP: transmitting %d-byte packet\n", dev->tx_len); - network_tx(dev->card, dev->tx_pkt, dev->tx_len); - } else { - plip_log(1, "PLIP: checksum error: expected %02X, got %02X\n", dev->tx_checksum_calc, dev->tx_checksum); - } + /* Transmit packet. */ + plip_log(2, "PLIP: transmitting %d-byte packet\n", dev->tx_len); + network_tx(dev->card, dev->tx_pkt, dev->tx_len); + } else { + plip_log(1, "PLIP: checksum error: expected %02X, got %02X\n", dev->tx_checksum_calc, dev->tx_checksum); + } - /* We're done with this packet. */ - free(dev->tx_pkt); - dev->tx_pkt = NULL; - dev->tx_len = 0; + /* We're done with this packet. */ + free(dev->tx_pkt); + dev->tx_pkt = NULL; + dev->tx_len = 0; - dev->state = PLIP_END; - dev->status |= 0x80; - break; + dev->state = PLIP_END; + dev->status |= 0x80; + break; - case PLIP_RX_LEN_LSB_LOW: - if (!(val & 0x01)) - return; /* D3/ACK not high yet */ - plip_log(2, "PLIP: rx_len = %04X (1/4)\n", dev->rx_len); - dev->status = (dev->rx_len & 0x0f) << 3; - dev->state = PLIP_RX_LEN_LSB_HIGH; - break; + case PLIP_RX_LEN_LSB_LOW: + if (!(val & 0x01)) + return; /* D3/ACK not high yet */ + plip_log(2, "PLIP: rx_len = %04X (1/4)\n", dev->rx_len); + dev->status = (dev->rx_len & 0x0f) << 3; + dev->state = PLIP_RX_LEN_LSB_HIGH; + break; - case PLIP_RX_LEN_LSB_HIGH: - if (!(val & 0x10)) - return; /* D4/BUSY not high yet */ - plip_log(2, "PLIP: rx_len = %04X (2/4)\n", dev->rx_len); - dev->status = ((dev->rx_len >> 4) & 0x0f) << 3; - dev->status |= 0x80; - dev->state = PLIP_RX_LEN_MSB_LOW; - break; + case PLIP_RX_LEN_LSB_HIGH: + if (!(val & 0x10)) + return; /* D4/BUSY not high yet */ + plip_log(2, "PLIP: rx_len = %04X (2/4)\n", dev->rx_len); + dev->status = ((dev->rx_len >> 4) & 0x0f) << 3; + dev->status |= 0x80; + dev->state = PLIP_RX_LEN_MSB_LOW; + break; - case PLIP_RX_LEN_MSB_LOW: - if (val & 0x10) - return; /* D4/BUSY not low yet */ - plip_log(2, "PLIP: rx_len = %04X (3/4)\n", dev->rx_len); - dev->status = ((dev->rx_len >> 8) & 0x0f) << 3; - dev->state = PLIP_RX_LEN_MSB_HIGH; - break; + case PLIP_RX_LEN_MSB_LOW: + if (val & 0x10) + return; /* D4/BUSY not low yet */ + plip_log(2, "PLIP: rx_len = %04X (3/4)\n", dev->rx_len); + dev->status = ((dev->rx_len >> 8) & 0x0f) << 3; + dev->state = PLIP_RX_LEN_MSB_HIGH; + break; - case PLIP_RX_LEN_MSB_HIGH: - if (!(val & 0x10)) - return; /* D4/BUSY not high yet */ - plip_log(2, "PLIP: rx_len = %04X (4/4)\n", dev->rx_len); - dev->status = ((dev->rx_len >> 12) & 0x0f) << 3; - dev->status |= 0x80; + case PLIP_RX_LEN_MSB_HIGH: + if (!(val & 0x10)) + return; /* D4/BUSY not high yet */ + plip_log(2, "PLIP: rx_len = %04X (4/4)\n", dev->rx_len); + dev->status = ((dev->rx_len >> 12) & 0x0f) << 3; + dev->status |= 0x80; - dev->rx_ptr = 0; - dev->rx_checksum = 0; - dev->state = PLIP_RX_DATA_LOW; - break; + dev->rx_ptr = 0; + dev->rx_checksum = 0; + dev->state = PLIP_RX_DATA_LOW; + break; - case PLIP_RX_DATA_LOW: - if (val & 0x10) - return; /* D4/BUSY not low yet */ - plip_log(2, "PLIP: rx_pkt[%d] = %02X (1/2)\n", dev->rx_ptr, dev->rx_pkt[dev->rx_ptr]); - dev->status = (dev->rx_pkt[dev->rx_ptr] & 0x0f) << 3; - dev->state = PLIP_RX_DATA_HIGH; - break; + case PLIP_RX_DATA_LOW: + if (val & 0x10) + return; /* D4/BUSY not low yet */ + plip_log(2, "PLIP: rx_pkt[%d] = %02X (1/2)\n", dev->rx_ptr, dev->rx_pkt[dev->rx_ptr]); + dev->status = (dev->rx_pkt[dev->rx_ptr] & 0x0f) << 3; + dev->state = PLIP_RX_DATA_HIGH; + break; - case PLIP_RX_DATA_HIGH: - if (!(val & 0x10)) - return; /* D4/BUSY not high yet */ - plip_log(2, "PLIP: rx_pkt[%d] = %02X (2/2)\n", dev->rx_ptr, dev->rx_pkt[dev->rx_ptr]); - dev->status = ((dev->rx_pkt[dev->rx_ptr] >> 4) & 0x0f) << 3; - dev->status |= 0x80; - dev->rx_checksum += dev->rx_pkt[dev->rx_ptr++]; + case PLIP_RX_DATA_HIGH: + if (!(val & 0x10)) + return; /* D4/BUSY not high yet */ + plip_log(2, "PLIP: rx_pkt[%d] = %02X (2/2)\n", dev->rx_ptr, dev->rx_pkt[dev->rx_ptr]); + dev->status = ((dev->rx_pkt[dev->rx_ptr] >> 4) & 0x0f) << 3; + dev->status |= 0x80; + dev->rx_checksum += dev->rx_pkt[dev->rx_ptr++]; - /* Are we done yet? */ - if (dev->rx_ptr < dev->rx_len) /* no, send another byte */ - dev->state = PLIP_RX_DATA_LOW; - else /* yes, move on to checksum */ - dev->state = PLIP_RX_CHECKSUM_LOW; - break; + /* Are we done yet? */ + if (dev->rx_ptr < dev->rx_len) /* no, send another byte */ + dev->state = PLIP_RX_DATA_LOW; + else /* yes, move on to checksum */ + dev->state = PLIP_RX_CHECKSUM_LOW; + break; - case PLIP_RX_CHECKSUM_LOW: - if (val & 0x10) - return; /* D4/BUSY not low yet */ - plip_log(2, "PLIP: rx_checksum = %02X (1/2)\n", dev->rx_checksum); - dev->status = (dev->rx_checksum & 0x0f) << 3; - dev->state = PLIP_RX_CHECKSUM_HIGH; - break; + case PLIP_RX_CHECKSUM_LOW: + if (val & 0x10) + return; /* D4/BUSY not low yet */ + plip_log(2, "PLIP: rx_checksum = %02X (1/2)\n", dev->rx_checksum); + dev->status = (dev->rx_checksum & 0x0f) << 3; + dev->state = PLIP_RX_CHECKSUM_HIGH; + break; - case PLIP_RX_CHECKSUM_HIGH: - if (!(val & 0x10)) - return; /* D4/BUSY not high yet */ - plip_log(2, "PLIP: rx_checksum = %02X (2/2)\n", dev->rx_checksum); - dev->status = ((dev->rx_checksum >> 4) & 0x0f) << 3; - dev->status |= 0x80; + case PLIP_RX_CHECKSUM_HIGH: + if (!(val & 0x10)) + return; /* D4/BUSY not high yet */ + plip_log(2, "PLIP: rx_checksum = %02X (2/2)\n", dev->rx_checksum); + dev->status = ((dev->rx_checksum >> 4) & 0x0f) << 3; + dev->status |= 0x80; - /* We're done with this packet. */ - free(dev->rx_pkt); - dev->rx_pkt = NULL; - dev->rx_len = 0; + /* We're done with this packet. */ + free(dev->rx_pkt); + dev->rx_pkt = NULL; + dev->rx_len = 0; - dev->state = PLIP_END; - break; + dev->state = PLIP_END; + break; - case PLIP_END: - if (val == 0x00) { /* written after TX or RX is done */ - plip_log(2, "PLIP: end\n"); - dev->status = 0x80; - dev->state = PLIP_START; + case PLIP_END: + if (val == 0x00) { /* written after TX or RX is done */ + plip_log(2, "PLIP: end\n"); + dev->status = 0x80; + dev->state = PLIP_START; - timer_set_delay_u64(&dev->rx_timer, ISACONST); /* for DOS */ - } + timer_set_delay_u64(&dev->rx_timer, ISACONST); /* for DOS */ + } - /* Disengage timeout timer. */ - timer_disable(&dev->timeout_timer); - return; + /* Disengage timeout timer. */ + timer_disable(&dev->timeout_timer); + return; } /* Engage timeout timer unless otherwise specified. */ timer_set_delay_u64(&dev->timeout_timer, 1000000 * TIMER_USEC); } - static void plip_write_ctrl(uint8_t val, void *priv) { @@ -356,10 +350,9 @@ plip_write_ctrl(uint8_t val, void *priv) dev->ctrl = val; if (val & 0x10) /* for Linux */ - timer_set_delay_u64(&dev->rx_timer, ISACONST); + timer_set_delay_u64(&dev->rx_timer, ISACONST); } - static uint8_t plip_read_status(void *priv) { @@ -370,31 +363,30 @@ plip_read_status(void *priv) return dev->status; } - static void plip_receive_packet(plip_t *dev) { /* At least the Linux driver supports being interrupted in the PLIP_TX_LEN_LSB_LOW state, but let's be safe. */ if (dev->state > PLIP_START) { - plip_log(3, "PLIP: cannot receive, operation already in progress\n"); - return; + plip_log(3, "PLIP: cannot receive, operation already in progress\n"); + return; } if (!dev->rx_pkt || !dev->rx_len) { /* unpause RX queue if there's no packet to receive */ - return; + return; } if (!(dev->ctrl & 0x10)) { /* checking this is essential to avoid collisions */ - plip_log(3, "PLIP: cannot receive, interrupts are off\n"); - return; + plip_log(3, "PLIP: cannot receive, interrupts are off\n"); + return; } plip_log(2, "PLIP: receiving %d-byte packet\n", dev->rx_len); /* Set up to receive a packet. */ dev->status = 0xc7; /* DOS expects exactly 0xc7, while Linux masks the 7 off */ - dev->state = PLIP_RX_LEN_LSB_LOW; + dev->state = PLIP_RX_LEN_LSB_LOW; /* Engage timeout timer. */ timer_set_delay_u64(&dev->timeout_timer, 1000000 * TIMER_USEC); @@ -403,7 +395,6 @@ plip_receive_packet(plip_t *dev) lpt_irq(dev->lpt, 1); } - /* This timer defers a call to plip_receive_packet to the next ISA clock, in order to avoid IRQ weirdness. */ static void @@ -416,7 +407,6 @@ rx_timer(void *priv) timer_disable(&dev->rx_timer); } - static int plip_rx(void *priv, uint8_t *buf, int io_len) { @@ -425,12 +415,12 @@ plip_rx(void *priv, uint8_t *buf, int io_len) plip_log(2, "PLIP: incoming %d-byte packet\n", io_len); if (dev->rx_pkt) { /* shouldn't really happen with the RX queue paused */ - plip_log(3, "PLIP: already have a packet to receive"); - return 0; + plip_log(3, "PLIP: already have a packet to receive"); + return 0; } if (!(dev->rx_pkt = malloc(io_len))) /* unlikely */ - fatal("PLIP: unable to allocate rx_pkt\n"); + fatal("PLIP: unable to allocate rx_pkt\n"); /* Copy this packet to our buffer. */ dev->rx_len = io_len; @@ -442,7 +432,6 @@ plip_rx(void *priv, uint8_t *buf, int io_len) return 1; } - static void * plip_lpt_init(void *lpt) { @@ -464,15 +453,14 @@ plip_lpt_init(void *lpt) return dev; } - static void * plip_net_init(const device_t *info) { plip_log(1, "PLIP: net_init()"); if (!instance) { - plip_log(1, " (not attached to LPT)\n"); - return NULL; + plip_log(1, " (not attached to LPT)\n"); + return NULL; } plip_log(1, " (attached to LPT)\n"); @@ -481,38 +469,37 @@ plip_net_init(const device_t *info) return instance; } - static void plip_close(void *priv) { - if (instance->card) { - netcard_close(instance->card); - } + if (instance->card) { + netcard_close(instance->card); + } free(priv); } const lpt_device_t lpt_plip_device = { - .name = "Parallel Line Internet Protocol", + .name = "Parallel Line Internet Protocol", .internal_name = "plip", - .init = plip_lpt_init, - .close = plip_close, - .write_data = plip_write_data, - .write_ctrl = plip_write_ctrl, - .read_data = NULL, - .read_status = plip_read_status, - .read_ctrl = NULL + .init = plip_lpt_init, + .close = plip_close, + .write_data = plip_write_data, + .write_ctrl = plip_write_ctrl, + .read_data = NULL, + .read_status = plip_read_status, + .read_ctrl = NULL }; const device_t plip_device = { - .name = "Parallel Line Internet Protocol", + .name = "Parallel Line Internet Protocol", .internal_name = "plip", - .flags = DEVICE_LPT, - .local = 0, - .init = plip_net_init, - .close = NULL, - .reset = NULL, + .flags = DEVICE_LPT, + .local = 0, + .init = plip_net_init, + .close = NULL, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/network/net_slirp.c b/src/network/net_slirp.c index 0bbd534b3..89c658e64 100644 --- a/src/network/net_slirp.c +++ b/src/network/net_slirp.c @@ -39,10 +39,10 @@ #include <86box/config.h> #include <86box/video.h> #ifdef _WIN32 -#define WIN32_LEAN_AND_MEAN -#include +# define WIN32_LEAN_AND_MEAN +# include #else -#include +# include #endif #include <86box/net_event.h> @@ -75,37 +75,33 @@ typedef struct { #ifdef ENABLE_SLIRP_LOG int slirp_do_log = ENABLE_SLIRP_LOG; - static void slirp_log(const char *fmt, ...) { va_list ap; if (slirp_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define slirp_log(fmt, ...) +# define slirp_log(fmt, ...) #endif - static void net_slirp_guest_error(const char *msg, void *opaque) { slirp_log("SLiRP: guest_error(): %s\n", msg); } - static int64_t net_slirp_clock_get_ns(void *opaque) { - return (int64_t)((double)tsc / cpuclock * 1000000000.0); + return (int64_t) ((double) tsc / cpuclock * 1000000000.0); } - static void * net_slirp_timer_new(SlirpTimerCb cb, void *cb_opaque, void *opaque) { @@ -114,7 +110,6 @@ net_slirp_timer_new(SlirpTimerCb cb, void *cb_opaque, void *opaque) return timer; } - static void net_slirp_timer_free(void *timer, void *opaque) { @@ -122,14 +117,12 @@ net_slirp_timer_free(void *timer, void *opaque) free(timer); } - static void net_slirp_timer_mod(void *timer, int64_t expire_timer, void *opaque) { timer_on_auto(timer, expire_timer * 1000); } - static void net_slirp_register_poll_fd(int fd, void *opaque) { @@ -137,7 +130,6 @@ net_slirp_register_poll_fd(int fd, void *opaque) (void) opaque; } - static void net_slirp_unregister_poll_fd(int fd, void *opaque) { @@ -145,14 +137,12 @@ net_slirp_unregister_poll_fd(int fd, void *opaque) (void) opaque; } - static void net_slirp_notify(void *opaque) { (void) opaque; } - ssize_t net_slirp_send_packet(const void *qp, size_t pkt_len, void *opaque) { @@ -160,20 +150,19 @@ net_slirp_send_packet(const void *qp, size_t pkt_len, void *opaque) slirp_log("SLiRP: received %d-byte packet\n", pkt_len); - memcpy(slirp->pkt.data, (uint8_t*) qp, pkt_len); + memcpy(slirp->pkt.data, (uint8_t *) qp, pkt_len); slirp->pkt.len = pkt_len; network_rx_put_pkt(slirp->card, &slirp->pkt); return pkt_len; } - #ifdef _WIN32 static int net_slirp_add_poll(int fd, int events, void *opaque) { - net_slirp_t *slirp = (net_slirp_t *) opaque; - long bitmask = 0; + net_slirp_t *slirp = (net_slirp_t *) opaque; + long bitmask = 0; if (events & SLIRP_POLL_IN) bitmask |= FD_READ | FD_ACCEPT; if (events & SLIRP_POLL_OUT) @@ -193,17 +182,17 @@ net_slirp_add_poll(int fd, int events, void *opaque) net_slirp_t *slirp = (net_slirp_t *) opaque; if (slirp->pfd_len >= slirp->pfd_size) { - int newsize = slirp->pfd_size + 16; + int newsize = slirp->pfd_size + 16; struct pollfd *new = realloc(slirp->pfd, newsize * sizeof(struct pollfd)); if (new) { - slirp->pfd = new; + slirp->pfd = new; slirp->pfd_size = newsize; } } if ((slirp->pfd_len < slirp->pfd_size)) { - int idx = slirp->pfd_len++; + int idx = slirp->pfd_len++; slirp->pfd[idx].fd = fd; - int pevents = 0; + int pevents = 0; if (events & SLIRP_POLL_IN) pevents |= POLLIN; if (events & SLIRP_POLL_OUT) @@ -225,8 +214,8 @@ net_slirp_add_poll(int fd, int events, void *opaque) static int net_slirp_get_revents(int idx, void *opaque) { - net_slirp_t *slirp = (net_slirp_t *) opaque; - int ret = 0; + net_slirp_t *slirp = (net_slirp_t *) opaque; + int ret = 0; WSANETWORKEVENTS ev; if (WSAEnumNetworkEvents(idx, slirp->sock_event, &ev) != 0) { return ret; @@ -242,9 +231,9 @@ net_slirp_get_revents(int idx, void *opaque) } \ } while (0) - WSA_TO_POLL(FD_READ, SLIRP_POLL_IN); - WSA_TO_POLL(FD_ACCEPT, SLIRP_POLL_IN); - WSA_TO_POLL(FD_WRITE, SLIRP_POLL_OUT); + WSA_TO_POLL(FD_READ, SLIRP_POLL_IN); + WSA_TO_POLL(FD_ACCEPT, SLIRP_POLL_IN); + WSA_TO_POLL(FD_WRITE, SLIRP_POLL_OUT); WSA_TO_POLL(FD_CONNECT, SLIRP_POLL_OUT); WSA_TO_POLL(FD_OOB, SLIRP_POLL_PRI); WSA_TO_POLL(FD_CLOSE, SLIRP_POLL_HUP); @@ -255,9 +244,9 @@ net_slirp_get_revents(int idx, void *opaque) static int net_slirp_get_revents(int idx, void *opaque) { - net_slirp_t *slirp = (net_slirp_t *) opaque; - int ret = 0; - int events = slirp->pfd[idx].revents; + net_slirp_t *slirp = (net_slirp_t *) opaque; + int ret = 0; + int events = slirp->pfd[idx].revents; if (events & POLLIN) ret |= SLIRP_POLL_IN; if (events & POLLOUT) @@ -273,15 +262,15 @@ net_slirp_get_revents(int idx, void *opaque) #endif static const SlirpCb slirp_cb = { - .send_packet = net_slirp_send_packet, - .guest_error = net_slirp_guest_error, - .clock_get_ns = net_slirp_clock_get_ns, - .timer_new = net_slirp_timer_new, - .timer_free = net_slirp_timer_free, - .timer_mod = net_slirp_timer_mod, - .register_poll_fd = net_slirp_register_poll_fd, + .send_packet = net_slirp_send_packet, + .guest_error = net_slirp_guest_error, + .clock_get_ns = net_slirp_clock_get_ns, + .timer_new = net_slirp_timer_new, + .timer_free = net_slirp_timer_free, + .timer_mod = net_slirp_timer_mod, + .register_poll_fd = net_slirp_register_poll_fd, .unregister_poll_fd = net_slirp_unregister_poll_fd, - .notify = net_slirp_notify + .notify = net_slirp_notify }; /* Send a packet to the SLiRP interface. */ @@ -299,7 +288,7 @@ net_slirp_in(net_slirp_t *slirp, uint8_t *pkt, int pkt_len) void net_slirp_in_available(void *priv) { - net_slirp_t *slirp = (net_slirp_t *)priv; + net_slirp_t *slirp = (net_slirp_t *) priv; net_event_set(&slirp->tx_event); } @@ -314,16 +303,16 @@ net_slirp_thread(void *priv) HANDLE events[3]; events[NET_EVENT_STOP] = net_event_get_handle(&slirp->stop_event); - events[NET_EVENT_TX] = net_event_get_handle(&slirp->tx_event); - events[NET_EVENT_RX] = slirp->sock_event; - bool run = true; + events[NET_EVENT_TX] = net_event_get_handle(&slirp->tx_event); + events[NET_EVENT_RX] = slirp->sock_event; + bool run = true; while (run) { uint32_t timeout = -1; slirp_pollfds_fill(slirp->slirp, &timeout, net_slirp_add_poll, slirp); if (timeout < 0) timeout = INFINITE; - int ret = WaitForMultipleObjects(3, events, FALSE, (DWORD)timeout); + int ret = WaitForMultipleObjects(3, events, FALSE, (DWORD) timeout); switch (ret - WAIT_OBJECT_0) { case NET_EVENT_STOP: run = false; @@ -341,7 +330,6 @@ net_slirp_thread(void *priv) default: slirp_pollfds_poll(slirp->slirp, ret == WAIT_FAILED, net_slirp_get_revents, slirp); break; - } } @@ -398,11 +386,11 @@ net_slirp_init(const netcard_t *card, const uint8_t *mac_addr, void *priv) slirp_log("SLiRP: initializing...\n"); net_slirp_t *slirp = calloc(1, sizeof(net_slirp_t)); memcpy(slirp->mac_addr, mac_addr, sizeof(slirp->mac_addr)); - slirp->card = (netcard_t*)card; + slirp->card = (netcard_t *) card; #ifndef _WIN32 slirp->pfd_size = 16 * sizeof(struct pollfd); - slirp->pfd = malloc(slirp->pfd_size); + slirp->pfd = malloc(slirp->pfd_size); memset(slirp->pfd, 0, slirp->pfd_size); #endif @@ -412,7 +400,7 @@ net_slirp_init(const netcard_t *card, const uint8_t *mac_addr, void *priv) struct in_addr host = { .s_addr = htonl(0x0a000002 | (slirp_card_num << 8)) }; /* 10.0.x.2 */ struct in_addr dhcp = { .s_addr = htonl(0x0a00000f | (slirp_card_num << 8)) }; /* 10.0.x.15 */ struct in_addr dns = { .s_addr = htonl(0x0a000003 | (slirp_card_num << 8)) }; /* 10.0.x.3 */ - struct in_addr bind = { .s_addr = htonl(0x00000000) }; /* 0.0.0.0 */ + struct in_addr bind = { .s_addr = htonl(0x00000000) }; /* 0.0.0.0 */ struct in6_addr ipv6_dummy = { 0 }; /* contents don't matter; we're not using IPv6 */ /* Initialize SLiRP. */ @@ -424,10 +412,10 @@ net_slirp_init(const netcard_t *card, const uint8_t *mac_addr, void *priv) } /* Set up port forwarding. */ - int udp, external, internal, i = 0; + int udp, external, internal, i = 0; char category[32]; snprintf(category, sizeof(category), "SLiRP Port Forwarding #%i", card->card_num + 1); - char key[20]; + char key[20]; while (1) { sprintf(key, "%d_protocol", i); udp = strcmp(config_get_string(category, key, "tcp"), "udp") == 0; diff --git a/src/network/net_wd8003.c b/src/network/net_wd8003.c index d53f570f0..4142fbd38 100644 --- a/src/network/net_wd8003.c +++ b/src/network/net_wd8003.c @@ -68,59 +68,58 @@ #include "cpu.h" /* Board type codes in card ID */ -#define WE_TYPE_WD8003 0x01 -#define WE_TYPE_WD8003S 0x02 -#define WE_TYPE_WD8003E 0x03 -#define WE_TYPE_WD8013EBT 0x05 -#define WE_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ -#define WE_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ -#define WE_TYPE_TOSHIBA3 0x13 /* named PCETB */ -#define WE_TYPE_TOSHIBA4 0x14 /* named PCETC */ -#define WE_TYPE_WD8003W 0x24 -#define WE_TYPE_WD8003EB 0x25 -#define WE_TYPE_WD8013W 0x26 -#define WE_TYPE_WD8013EP 0x27 -#define WE_TYPE_WD8013WC 0x28 -#define WE_TYPE_WD8013EPC 0x29 -#define WE_TYPE_SMC8216T 0x2a -#define WE_TYPE_SMC8216C 0x2b -#define WE_TYPE_WD8013EBP 0x2c +#define WE_TYPE_WD8003 0x01 +#define WE_TYPE_WD8003S 0x02 +#define WE_TYPE_WD8003E 0x03 +#define WE_TYPE_WD8013EBT 0x05 +#define WE_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ +#define WE_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ +#define WE_TYPE_TOSHIBA3 0x13 /* named PCETB */ +#define WE_TYPE_TOSHIBA4 0x14 /* named PCETC */ +#define WE_TYPE_WD8003W 0x24 +#define WE_TYPE_WD8003EB 0x25 +#define WE_TYPE_WD8013W 0x26 +#define WE_TYPE_WD8013EP 0x27 +#define WE_TYPE_WD8013WC 0x28 +#define WE_TYPE_WD8013EPC 0x29 +#define WE_TYPE_SMC8216T 0x2a +#define WE_TYPE_SMC8216C 0x2b +#define WE_TYPE_WD8013EBP 0x2c -#define WE_ICR_16BIT_SLOT 0x01 +#define WE_ICR_16BIT_SLOT 0x01 -#define WE_MSR_ENABLE_RAM 0x40 -#define WE_MSR_SOFT_RESET 0x80 +#define WE_MSR_ENABLE_RAM 0x40 +#define WE_MSR_SOFT_RESET 0x80 -#define WE_IRR_ENABLE_IRQ 0x80 +#define WE_IRR_ENABLE_IRQ 0x80 -#define WE_ID_ETHERNET 0x01 -#define WE_ID_SOFT_CONFIG 0x20 -#define WE_ID_EXTRA_RAM 0x40 -#define WE_ID_BUS_MCA 0x80 +#define WE_ID_ETHERNET 0x01 +#define WE_ID_SOFT_CONFIG 0x20 +#define WE_ID_EXTRA_RAM 0x40 +#define WE_ID_BUS_MCA 0x80 typedef struct { - dp8390_t *dp8390; - mem_mapping_t ram_mapping; - uint32_t ram_addr, ram_size; - uint8_t maclocal[6]; /* configured MAC (local) address */ - uint8_t bit16, pad; - int board; - const char *name; - uint32_t base_address; - int irq; + dp8390_t *dp8390; + mem_mapping_t ram_mapping; + uint32_t ram_addr, ram_size; + uint8_t maclocal[6]; /* configured MAC (local) address */ + uint8_t bit16, pad; + int board; + const char *name; + uint32_t base_address; + int irq; /* POS registers, MCA boards only */ - uint8_t pos_regs[8]; + uint8_t pos_regs[8]; /* Memory for WD cards*/ - uint8_t msr, /* Memory Select Register (MSR) */ - icr, /* Interface Configuration Register (ICR) */ - irr, /* Interrupt Request Register (IRR) */ - laar, /* LA Address Register (read by Windows 98!) */ - if_chip, board_chip; + uint8_t msr, /* Memory Select Register (MSR) */ + icr, /* Interface Configuration Register (ICR) */ + irr, /* Interrupt Request Register (IRR) */ + laar, /* LA Address Register (read by Windows 98!) */ + if_chip, board_chip; } wd_t; - #ifdef ENABLE_WD_LOG int wd_do_log = ENABLE_WD_LOG; @@ -130,18 +129,16 @@ wdlog(const char *fmt, ...) va_list ap; if (wd_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define wdlog(fmt, ...) +# define wdlog(fmt, ...) #endif - -static const int we_int_table[4] = {2, 3, 4, 7}; - +static const int we_int_table[4] = { 2, 3, 4, 7 }; static void wd_interrupt(void *priv, int set) @@ -149,40 +146,37 @@ wd_interrupt(void *priv, int set) wd_t *dev = (wd_t *) priv; if (!(dev->irr & WE_IRR_ENABLE_IRQ)) - return; + return; if (set) - picint(1 << dev->irq); + picint(1 << dev->irq); else - picintc(1 << dev->irq); + picintc(1 << dev->irq); } - /* reset - restore state to power-up, cancelling all i/o */ static void wd_reset(void *priv) { - wd_t *dev = (wd_t *)priv; + wd_t *dev = (wd_t *) priv; wdlog("%s: reset\n", dev->name); dp8390_reset(dev->dp8390); } - static void wd_soft_reset(void *priv) { - wd_t *dev = (wd_t *)priv; + wd_t *dev = (wd_t *) priv; dp8390_soft_reset(dev->dp8390); } - static uint8_t wd_ram_read(uint32_t addr, void *priv) { - wd_t *dev = (wd_t *)priv; + wd_t *dev = (wd_t *) priv; wdlog("WD80x3: RAM Read: addr=%06x, val=%02x\n", addr & (dev->ram_size - 1), dev->dp8390->mem[addr & (dev->ram_size - 1)]); return dev->dp8390->mem[addr & (dev->ram_size - 1)]; @@ -191,365 +185,353 @@ wd_ram_read(uint32_t addr, void *priv) static void wd_ram_write(uint32_t addr, uint8_t val, void *priv) { - wd_t *dev = (wd_t *)priv; + wd_t *dev = (wd_t *) priv; dev->dp8390->mem[addr & (dev->ram_size - 1)] = val; wdlog("WD80x3: RAM Write: addr=%06x, val=%02x\n", addr & (dev->ram_size - 1), val); } - static int wd_get_irq_index(wd_t *dev) { uint8_t i, irq = 255; for (i = 0; i < 4; i++) { - if (we_int_table[i] == dev->irq) - irq = i; + if (we_int_table[i] == dev->irq) + irq = i; } if (irq != 255) - return ((irq & 0x03) << 5); + return ((irq & 0x03) << 5); else - return 0; + return 0; } - static uint32_t wd_smc_read(wd_t *dev, uint32_t off) { - uint32_t retval = 0; + uint32_t retval = 0; uint32_t checksum = 0; if (dev->board == WD8003E) - off |= 0x08; + off |= 0x08; - switch(off) { - case 0x00: - if (dev->board_chip & WE_ID_BUS_MCA) - retval = (dev->msr & 0xc0) | ((dev->ram_addr >> 13) & 0x3f); - else - retval = dev->msr; - break; + switch (off) { + case 0x00: + if (dev->board_chip & WE_ID_BUS_MCA) + retval = (dev->msr & 0xc0) | ((dev->ram_addr >> 13) & 0x3f); + else + retval = dev->msr; + break; - case 0x01: - if (dev->board_chip & WE_ID_SOFT_CONFIG) - retval = dev->icr; - else - retval = dev->icr & WE_ICR_16BIT_SLOT; - break; + case 0x01: + if (dev->board_chip & WE_ID_SOFT_CONFIG) + retval = dev->icr; + else + retval = dev->icr & WE_ICR_16BIT_SLOT; + break; - case 0x04: - if (dev->board_chip & WE_ID_SOFT_CONFIG) - retval = (dev->irr & 0x9f) | wd_get_irq_index(dev); - break; + case 0x04: + if (dev->board_chip & WE_ID_SOFT_CONFIG) + retval = (dev->irr & 0x9f) | wd_get_irq_index(dev); + break; - case 0x05: - if (dev->board_chip & WE_ID_SOFT_CONFIG) - retval = dev->laar; - break; + case 0x05: + if (dev->board_chip & WE_ID_SOFT_CONFIG) + retval = dev->laar; + break; - case 0x07: - if (dev->board_chip & WE_ID_SOFT_CONFIG) - retval = dev->if_chip; - break; + case 0x07: + if (dev->board_chip & WE_ID_SOFT_CONFIG) + retval = dev->if_chip; + break; - case 0x08: - retval = dev->dp8390->physaddr[0]; - break; + case 0x08: + retval = dev->dp8390->physaddr[0]; + break; - case 0x09: - retval = dev->dp8390->physaddr[1]; - break; + case 0x09: + retval = dev->dp8390->physaddr[1]; + break; - case 0x0a: - retval = dev->dp8390->physaddr[2]; - break; + case 0x0a: + retval = dev->dp8390->physaddr[2]; + break; - case 0x0b: - retval = dev->dp8390->physaddr[3]; - break; + case 0x0b: + retval = dev->dp8390->physaddr[3]; + break; - case 0x0c: - retval = dev->dp8390->physaddr[4]; - break; + case 0x0c: + retval = dev->dp8390->physaddr[4]; + break; - case 0x0d: - retval = dev->dp8390->physaddr[5]; - break; + case 0x0d: + retval = dev->dp8390->physaddr[5]; + break; - case 0x0e: - retval = dev->board_chip; - break; + case 0x0e: + retval = dev->board_chip; + break; - case 0x0f: - /*This has to return the byte that adds up to 0xFF*/ - checksum = (dev->dp8390->physaddr[0] + dev->dp8390->physaddr[1] + dev->dp8390->physaddr[2] + - dev->dp8390->physaddr[3] + dev->dp8390->physaddr[4] + dev->dp8390->physaddr[5] + - dev->board_chip); + case 0x0f: + /*This has to return the byte that adds up to 0xFF*/ + checksum = (dev->dp8390->physaddr[0] + dev->dp8390->physaddr[1] + dev->dp8390->physaddr[2] + dev->dp8390->physaddr[3] + dev->dp8390->physaddr[4] + dev->dp8390->physaddr[5] + dev->board_chip); - retval = 0xff - (checksum & 0xff); - break; + retval = 0xff - (checksum & 0xff); + break; } wdlog("%s: ASIC read addr=0x%02x, value=0x%04x\n", - dev->name, (unsigned)off, (unsigned) retval); + dev->name, (unsigned) off, (unsigned) retval); - return(retval); + return (retval); } - static void wd_set_ram(wd_t *dev) { uint32_t a13; if ((dev->board_chip & 0xa0) == 0x20) { - a13 = dev->msr & 0x3f; - a13 <<= 13; + a13 = dev->msr & 0x3f; + a13 <<= 13; - dev->ram_addr = a13 | (1 << 19); - mem_mapping_set_addr(&dev->ram_mapping, dev->ram_addr, dev->ram_size); - wdlog("%s: RAM address set to %08X\n", dev->name, dev->ram_addr); + dev->ram_addr = a13 | (1 << 19); + mem_mapping_set_addr(&dev->ram_mapping, dev->ram_addr, dev->ram_size); + wdlog("%s: RAM address set to %08X\n", dev->name, dev->ram_addr); } if (dev->msr & WE_MSR_ENABLE_RAM) - mem_mapping_enable(&dev->ram_mapping); + mem_mapping_enable(&dev->ram_mapping); else - mem_mapping_disable(&dev->ram_mapping); + mem_mapping_disable(&dev->ram_mapping); wdlog("%s: RAM now %sabled\n", dev->name, (dev->msr & WE_MSR_ENABLE_RAM) ? "en" : "dis"); } - static void wd_smc_write(wd_t *dev, uint32_t off, uint32_t val) { uint8_t old; wdlog("%s: ASIC write addr=0x%02x, value=0x%04x\n", - dev->name, (unsigned)off, (unsigned) val); + dev->name, (unsigned) off, (unsigned) val); if (off && (dev->board == WD8003E)) - return; + return; - switch(off) { - /* Bits 0-5: Bits 13-18 of memory address (writable?): - Windows 98 requires this to be preloaded with the initial - addresss to work correctly; - Bit 6: Enable memory if set; - Bit 7: Software reset if set. */ - case 0x00: /* WD Control register */ - old = dev->msr; + switch (off) { + /* Bits 0-5: Bits 13-18 of memory address (writable?): + Windows 98 requires this to be preloaded with the initial + addresss to work correctly; + Bit 6: Enable memory if set; + Bit 7: Software reset if set. */ + case 0x00: /* WD Control register */ + old = dev->msr; - if (!(old & WE_MSR_SOFT_RESET) && (val & WE_MSR_SOFT_RESET)) { - wd_soft_reset(dev); - wdlog("WD80x3: Soft reset\n"); - } + if (!(old & WE_MSR_SOFT_RESET) && (val & WE_MSR_SOFT_RESET)) { + wd_soft_reset(dev); + wdlog("WD80x3: Soft reset\n"); + } - if ((dev->board_chip & 0xa0) == 0x20) - dev->msr = val; - else - dev->msr = (dev->msr & 0x3f) | (val & 0xc0); + if ((dev->board_chip & 0xa0) == 0x20) + dev->msr = val; + else + dev->msr = (dev->msr & 0x3f) | (val & 0xc0); - if ((old &= 0x7f) != (val & 0x7f)) { - wd_set_ram(dev); - wdlog("WD80x3: Memory now %sabled (addr = %08X)\n", (val & WE_MSR_ENABLE_RAM) ? "en" : "dis", dev->ram_addr); - } - break; + if ((old &= 0x7f) != (val & 0x7f)) { + wd_set_ram(dev); + wdlog("WD80x3: Memory now %sabled (addr = %08X)\n", (val & WE_MSR_ENABLE_RAM) ? "en" : "dis", dev->ram_addr); + } + break; - /* Bit 1: 0 = 8-bit slot, 1 = 16-bit slot; - Bit 3: 0 = 8k RAM, 1 = 32k RAM (only on revision < 2). */ - case 0x01: - if (dev->bit16 & 2) - dev->icr = (dev->icr & WE_ICR_16BIT_SLOT) | (val & WE_ICR_16BIT_SLOT); - else - dev->icr = val; - break; + /* Bit 1: 0 = 8-bit slot, 1 = 16-bit slot; + Bit 3: 0 = 8k RAM, 1 = 32k RAM (only on revision < 2). */ + case 0x01: + if (dev->bit16 & 2) + dev->icr = (dev->icr & WE_ICR_16BIT_SLOT) | (val & WE_ICR_16BIT_SLOT); + else + dev->icr = val; + break; - /* Bit 5: Bit 0 of encoded IRQ; - Bit 6: Bit 1 of encoded IRQ; - Bit 7: Enable interrupts. */ - case 0x04: - if (dev->board_chip & WE_ID_SOFT_CONFIG) - dev->irr = (dev->irr & 0xe0) | (val & 0x1f); - break; + /* Bit 5: Bit 0 of encoded IRQ; + Bit 6: Bit 1 of encoded IRQ; + Bit 7: Enable interrupts. */ + case 0x04: + if (dev->board_chip & WE_ID_SOFT_CONFIG) + dev->irr = (dev->irr & 0xe0) | (val & 0x1f); + break; - /* Bits 0-4: Bits 19-23 of memory address (writable?): - Windows 98 requires this to be preloaded with the initial - addresss to work correctly; - Bit 5: Enable software interrupt; - Bit 6: Enable 16-bit RAM for LAN if set; - Bit 7: Enable 16-bit RAM for host if set. */ - case 0x05: - if (dev->board_chip & WE_ID_SOFT_CONFIG) - dev->laar = val; - break; + /* Bits 0-4: Bits 19-23 of memory address (writable?): + Windows 98 requires this to be preloaded with the initial + addresss to work correctly; + Bit 5: Enable software interrupt; + Bit 6: Enable 16-bit RAM for LAN if set; + Bit 7: Enable 16-bit RAM for host if set. */ + case 0x05: + if (dev->board_chip & WE_ID_SOFT_CONFIG) + dev->laar = val; + break; - /* Bits 0-4: Chip ID; - Bit 5: Software configuration is supported if present; - Bit 6: 0 = 16k RAM, 1 = 32k RAM. */ - case 0x07: - if (dev->board_chip & WE_ID_SOFT_CONFIG) - dev->if_chip = val; - break; + /* Bits 0-4: Chip ID; + Bit 5: Software configuration is supported if present; + Bit 6: 0 = 16k RAM, 1 = 32k RAM. */ + case 0x07: + if (dev->board_chip & WE_ID_SOFT_CONFIG) + dev->if_chip = val; + break; - default: - /* This is invalid, but happens under win95 device detection: - maybe some clone cards implement writing for some other - registers? */ - wdlog("%s: ASIC write invalid address %04x, ignoring\n", - dev->name, (unsigned)off); - break; + default: + /* This is invalid, but happens under win95 device detection: + maybe some clone cards implement writing for some other + registers? */ + wdlog("%s: ASIC write invalid address %04x, ignoring\n", + dev->name, (unsigned) off); + break; } } - static uint8_t wd_read(uint16_t addr, void *priv, int len) { - wd_t *dev = (wd_t *)priv; + wd_t *dev = (wd_t *) priv; uint8_t retval = 0; - int off = addr - dev->base_address; + int off = addr - dev->base_address; wdlog("%s: read addr %x\n", dev->name, addr); if (off == 0x10) - retval = dp8390_read_cr(dev->dp8390); + retval = dp8390_read_cr(dev->dp8390); else if ((off >= 0x00) && (off <= 0x0f)) - retval = wd_smc_read(dev, off); + retval = wd_smc_read(dev, off); else { - switch(dev->dp8390->CR.pgsel) { - case 0x00: - retval = dp8390_page0_read(dev->dp8390, off - 0x10, len); - break; - case 0x01: - retval = dp8390_page1_read(dev->dp8390, off - 0x10, len); - break; - case 0x02: - retval = dp8390_page2_read(dev->dp8390, off - 0x10, len); - break; - default: - wdlog("%s: unknown value of pgsel in read - %d\n", - dev->name, dev->dp8390->CR.pgsel); - break; - } + switch (dev->dp8390->CR.pgsel) { + case 0x00: + retval = dp8390_page0_read(dev->dp8390, off - 0x10, len); + break; + case 0x01: + retval = dp8390_page1_read(dev->dp8390, off - 0x10, len); + break; + case 0x02: + retval = dp8390_page2_read(dev->dp8390, off - 0x10, len); + break; + default: + wdlog("%s: unknown value of pgsel in read - %d\n", + dev->name, dev->dp8390->CR.pgsel); + break; + } } - return(retval); + return (retval); } - static uint8_t wd_readb(uint16_t addr, void *priv) { wd_t *dev = (wd_t *) priv; - return(wd_read(addr, dev, 1)); + return (wd_read(addr, dev, 1)); } - static uint16_t wd_readw(uint16_t addr, void *priv) { wd_t *dev = (wd_t *) priv; - return(wd_read(addr, dev, 2)); + return (wd_read(addr, dev, 2)); } - static void wd_write(uint16_t addr, uint8_t val, void *priv, unsigned int len) { - wd_t *dev = (wd_t *)priv; - int off = addr - dev->base_address; + wd_t *dev = (wd_t *) priv; + int off = addr - dev->base_address; wdlog("%s: write addr %x, value %x\n", dev->name, addr, val); if (off == 0x10) - dp8390_write_cr(dev->dp8390, val); + dp8390_write_cr(dev->dp8390, val); else if ((off >= 0x00) && (off <= 0x0f)) - wd_smc_write(dev, off, val); + wd_smc_write(dev, off, val); else { - switch(dev->dp8390->CR.pgsel) { - case 0x00: - dp8390_page0_write(dev->dp8390, off - 0x10, val, len); - break; - case 0x01: - dp8390_page1_write(dev->dp8390, off - 0x10, val, len); - break; - default: - wdlog("%s: unknown value of pgsel in write - %d\n", - dev->name, dev->dp8390->CR.pgsel); - break; - } + switch (dev->dp8390->CR.pgsel) { + case 0x00: + dp8390_page0_write(dev->dp8390, off - 0x10, val, len); + break; + case 0x01: + dp8390_page1_write(dev->dp8390, off - 0x10, val, len); + break; + default: + wdlog("%s: unknown value of pgsel in write - %d\n", + dev->name, dev->dp8390->CR.pgsel); + break; + } } } - static void wd_writeb(uint16_t addr, uint8_t val, void *priv) { wd_write(addr, val, priv, 1); } - static void wd_writew(uint16_t addr, uint16_t val, void *priv) { wd_write(addr, val & 0xff, priv, 2); } - static void wd_io_set(wd_t *dev, uint16_t addr) { if (dev->bit16 & 1) { - io_sethandler(addr, 0x20, - wd_readb, wd_readw, NULL, - wd_writeb, wd_writew, NULL, dev); + io_sethandler(addr, 0x20, + wd_readb, wd_readw, NULL, + wd_writeb, wd_writew, NULL, dev); } else { - io_sethandler(addr, 0x20, - wd_readb, NULL, NULL, - wd_writeb, NULL, NULL, dev); + io_sethandler(addr, 0x20, + wd_readb, NULL, NULL, + wd_writeb, NULL, NULL, dev); } } - static void wd_io_remove(wd_t *dev, uint16_t addr) { if (dev->bit16 & 1) { - io_removehandler(addr, 0x20, - wd_readb, wd_readw, NULL, - wd_writeb, wd_writew, NULL, dev); + io_removehandler(addr, 0x20, + wd_readb, wd_readw, NULL, + wd_writeb, wd_writew, NULL, dev); } else { - io_removehandler(addr, 0x20, - wd_readb, NULL, NULL, - wd_writeb, NULL, NULL, dev); + io_removehandler(addr, 0x20, + wd_readb, NULL, NULL, + wd_writeb, NULL, NULL, dev); } } - static uint8_t wd_mca_read(int port, void *priv) { - wd_t *dev = (wd_t *)priv; + wd_t *dev = (wd_t *) priv; - return(dev->pos_regs[port & 7]); + return (dev->pos_regs[port & 7]); } - -#define MCA_6FC0_IRQS { 3, 4, 10, 15 } +#define MCA_6FC0_IRQS \ + { \ + 3, 4, 10, 15 \ + } static void wd_mca_write(int port, uint8_t val, void *priv) { - wd_t *dev = (wd_t *)priv; + wd_t *dev = (wd_t *) priv; int8_t irq[4] = MCA_6FC0_IRQS; /* MCA does not write registers below 0x0100. */ - if (port < 0x0102) return; + if (port < 0x0102) + return; /* Save the MCA register value. */ dev->pos_regs[port & 7] = val; @@ -562,34 +544,35 @@ wd_mca_write(int port, uint8_t val, void *priv) * So, remove current address, if any. */ if (dev->base_address) - wd_io_remove(dev, dev->base_address); + wd_io_remove(dev, dev->base_address); dev->base_address = (dev->pos_regs[2] & 0xfe) << 4; - dev->ram_addr = (dev->pos_regs[3] & 0xfc) << 12; - dev->irq = irq[dev->pos_regs[5] & 0x02]; + dev->ram_addr = (dev->pos_regs[3] & 0xfc) << 12; + dev->irq = irq[dev->pos_regs[5] & 0x02]; /* Initialize the device if fully configured. */ /* Register (new) I/O handler. */ if (dev->pos_regs[2] & 0x01) - wd_io_set(dev, dev->base_address); + wd_io_set(dev, dev->base_address); mem_mapping_set_addr(&dev->ram_mapping, dev->ram_addr, dev->ram_size); mem_mapping_disable(&dev->ram_mapping); if ((dev->msr & WE_MSR_ENABLE_RAM) && (dev->pos_regs[2] & 0x01)) - mem_mapping_enable(&dev->ram_mapping); + mem_mapping_enable(&dev->ram_mapping); wdlog("%s: attached IO=0x%X IRQ=%d, RAM addr=0x%06x\n", dev->name, - dev->base_address, dev->irq, dev->ram_addr); + dev->base_address, dev->irq, dev->ram_addr); } static void wd_8013epa_mca_write(int port, uint8_t val, void *priv) { - wd_t *dev = (wd_t *)priv; + wd_t *dev = (wd_t *) priv; /* MCA does not write registers below 0x0100. */ - if (port < 0x0102) return; + if (port < 0x0102) + return; /* Save the MCA register value. */ dev->pos_regs[port & 7] = val; @@ -602,7 +585,7 @@ wd_8013epa_mca_write(int port, uint8_t val, void *priv) * So, remove current address, if any. */ if (dev->base_address) - wd_io_remove(dev, dev->base_address); + wd_io_remove(dev, dev->base_address); dev->base_address = 0x800 + ((dev->pos_regs[2] & 0xf0) << 8); @@ -633,38 +616,36 @@ wd_8013epa_mca_write(int port, uint8_t val, void *priv) /* Initialize the device if fully configured. */ /* Register (new) I/O handler. */ if (dev->pos_regs[2] & 0x01) - wd_io_set(dev, dev->base_address); + wd_io_set(dev, dev->base_address); mem_mapping_set_addr(&dev->ram_mapping, dev->ram_addr, dev->ram_size); mem_mapping_disable(&dev->ram_mapping); if ((dev->msr & WE_MSR_ENABLE_RAM) && (dev->pos_regs[2] & 0x01)) - mem_mapping_enable(&dev->ram_mapping); + mem_mapping_enable(&dev->ram_mapping); wdlog("%s: attached IO=0x%X IRQ=%d, RAM addr=0x%06x\n", dev->name, - dev->base_address, dev->irq, dev->ram_addr); + dev->base_address, dev->irq, dev->ram_addr); } - static uint8_t wd_mca_feedb(void *priv) { return 1; } - static void * wd_init(const device_t *info) { uint32_t mac; - wd_t *dev; + wd_t *dev; dev = malloc(sizeof(wd_t)); memset(dev, 0x00, sizeof(wd_t)); - dev->name = info->name; + dev->name = info->name; dev->board = info->local; - dev->maclocal[0] = 0x00; /* 00:00:C0 (WD/SMC OID) */ + dev->maclocal[0] = 0x00; /* 00:00:C0 (WD/SMC OID) */ dev->maclocal[1] = 0x00; dev->maclocal[2] = 0xC0; @@ -673,92 +654,92 @@ wd_init(const device_t *info) /* Set up our BIA. */ if (mac & 0xff000000) { - /* Generate new local MAC. */ - dev->maclocal[3] = random_generate(); - dev->maclocal[4] = random_generate(); - dev->maclocal[5] = random_generate(); - mac = (((int) dev->maclocal[3]) << 16); - mac |= (((int) dev->maclocal[4]) << 8); - mac |= ((int) dev->maclocal[5]); - device_set_config_mac("mac", mac); + /* Generate new local MAC. */ + dev->maclocal[3] = random_generate(); + dev->maclocal[4] = random_generate(); + dev->maclocal[5] = random_generate(); + mac = (((int) dev->maclocal[3]) << 16); + mac |= (((int) dev->maclocal[4]) << 8); + mac |= ((int) dev->maclocal[5]); + device_set_config_mac("mac", mac); } else { - dev->maclocal[3] = (mac>>16) & 0xff; - dev->maclocal[4] = (mac>>8) & 0xff; - dev->maclocal[5] = (mac & 0xff); + dev->maclocal[3] = (mac >> 16) & 0xff; + dev->maclocal[4] = (mac >> 8) & 0xff; + dev->maclocal[5] = (mac & 0xff); } if ((dev->board == WD8003ETA) || (dev->board == WD8003EA) || dev->board == WD8013EPA) { - if (dev->board == WD8013EPA) - mca_add(wd_mca_read, wd_8013epa_mca_write, wd_mca_feedb, NULL, dev); - else - mca_add(wd_mca_read, wd_mca_write, wd_mca_feedb, NULL, dev); + if (dev->board == WD8013EPA) + mca_add(wd_mca_read, wd_8013epa_mca_write, wd_mca_feedb, NULL, dev); + else + mca_add(wd_mca_read, wd_mca_write, wd_mca_feedb, NULL, dev); } else { - dev->base_address = device_get_config_hex16("base"); - dev->irq = device_get_config_int("irq"); - dev->ram_addr = device_get_config_hex20("ram_addr"); + dev->base_address = device_get_config_hex16("base"); + dev->irq = device_get_config_int("irq"); + dev->ram_addr = device_get_config_hex20("ram_addr"); } - dev->dp8390 = device_add_inst(&dp8390_device, dp3890_inst++); - dev->dp8390->priv = dev; + dev->dp8390 = device_add_inst(&dp8390_device, dp3890_inst++); + dev->dp8390->priv = dev; dev->dp8390->interrupt = wd_interrupt; dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ); - switch(dev->board) { - /* Ethernet, ISA, no interface chip, RAM 8k */ - case WD8003E: - dev->board_chip = WE_TYPE_WD8003E; - dev->ram_size = 0x2000; - break; + switch (dev->board) { + /* Ethernet, ISA, no interface chip, RAM 8k */ + case WD8003E: + dev->board_chip = WE_TYPE_WD8003E; + dev->ram_size = 0x2000; + break; - /* Ethernet, ISA, 5x3 interface chip, RAM 8k or 32k */ - case WD8003EB: - dev->board_chip = WE_TYPE_WD8003EB; - dev->if_chip = 1; - dev->ram_size = device_get_config_int("ram_size"); - if (dev->ram_size == 0x8000) - dev->board_chip |= WE_ID_EXTRA_RAM; + /* Ethernet, ISA, 5x3 interface chip, RAM 8k or 32k */ + case WD8003EB: + dev->board_chip = WE_TYPE_WD8003EB; + dev->if_chip = 1; + dev->ram_size = device_get_config_int("ram_size"); + if (dev->ram_size == 0x8000) + dev->board_chip |= WE_ID_EXTRA_RAM; - /* Bit A19 is implicit 1. */ - dev->msr |= (dev->ram_addr >> 13) & 0x3f; - break; + /* Bit A19 is implicit 1. */ + dev->msr |= (dev->ram_addr >> 13) & 0x3f; + break; - /* Ethernet, ISA, no interface chip, RAM 8k or 32k (8-bit slot) / 16k or 64k (16-bit slot) */ - case WD8013EBT: - dev->board_chip = WE_TYPE_WD8013EBT; - dev->ram_size = device_get_config_int("ram_size"); - if (dev->ram_size == 0x10000) - dev->board_chip |= WE_ID_EXTRA_RAM; + /* Ethernet, ISA, no interface chip, RAM 8k or 32k (8-bit slot) / 16k or 64k (16-bit slot) */ + case WD8013EBT: + dev->board_chip = WE_TYPE_WD8013EBT; + dev->ram_size = device_get_config_int("ram_size"); + if (dev->ram_size == 0x10000) + dev->board_chip |= WE_ID_EXTRA_RAM; - dev->bit16 = 2; - if (is286) - dev->bit16 |= 1; - else { - dev->bit16 |= 0; - if (dev->irq == 9) - dev->irq = 2; - dev->ram_size >>= 1; /* Half the RAM when in 8-bit slot. */ - } - break; + dev->bit16 = 2; + if (is286) + dev->bit16 |= 1; + else { + dev->bit16 |= 0; + if (dev->irq == 9) + dev->irq = 2; + dev->ram_size >>= 1; /* Half the RAM when in 8-bit slot. */ + } + break; - /* Ethernet, MCA, 5x3 interface chip, RAM 16k */ - case WD8003EA: - dev->board_chip = WE_ID_SOFT_CONFIG; - /* Ethernet, MCA, no interface chip, RAM 16k */ - case WD8003ETA: - dev->board_chip |= WE_TYPE_WD8013EBT | WE_ID_BUS_MCA; - dev->ram_size = 0x4000; - dev->pos_regs[0] = 0xC0; - dev->pos_regs[1] = 0x6F; - dev->bit16 = 3; - break; + /* Ethernet, MCA, 5x3 interface chip, RAM 16k */ + case WD8003EA: + dev->board_chip = WE_ID_SOFT_CONFIG; + /* Ethernet, MCA, no interface chip, RAM 16k */ + case WD8003ETA: + dev->board_chip |= WE_TYPE_WD8013EBT | WE_ID_BUS_MCA; + dev->ram_size = 0x4000; + dev->pos_regs[0] = 0xC0; + dev->pos_regs[1] = 0x6F; + dev->bit16 = 3; + break; - case WD8013EPA: - dev->board_chip = WE_TYPE_WD8013EP | WE_ID_BUS_MCA; - dev->ram_size = device_get_config_int("ram_size"); - dev->pos_regs[0] = 0xC8; - dev->pos_regs[1] = 0x61; - dev->bit16 = 3; - break; + case WD8013EPA: + dev->board_chip = WE_TYPE_WD8013EP | WE_ID_BUS_MCA; + dev->ram_size = device_get_config_int("ram_size"); + dev->pos_regs[0] = 0xC8; + dev->pos_regs[1] = 0x61; + dev->bit16 = 3; + break; } dev->irr |= WE_IRR_ENABLE_IRQ; @@ -767,23 +748,23 @@ wd_init(const device_t *info) dp8390_mem_alloc(dev->dp8390, 0x0000, dev->ram_size); if (dev->base_address) - wd_io_set(dev, dev->base_address); + wd_io_set(dev, dev->base_address); memcpy(dev->dp8390->physaddr, dev->maclocal, sizeof(dev->maclocal)); wdlog("%s: I/O=%04x, IRQ=%d, MAC=%02x:%02x:%02x:%02x:%02x:%02x\n", - dev->name, dev->base_address, dev->irq, - dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2], - dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]); + dev->name, dev->base_address, dev->irq, + dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2], + dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]); /* Reset the board. */ wd_reset(dev); /* Map this system into the memory map. */ mem_mapping_add(&dev->ram_mapping, dev->ram_addr, dev->ram_size, - wd_ram_read, NULL, NULL, - wd_ram_write, NULL, NULL, - NULL, MEM_MAPPING_EXTERNAL, dev); + wd_ram_read, NULL, NULL, + wd_ram_write, NULL, NULL, + NULL, MEM_MAPPING_EXTERNAL, dev); mem_mapping_disable(&dev->ram_mapping); @@ -791,18 +772,17 @@ wd_init(const device_t *info) dev->dp8390->card = network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL); if (!(dev->board_chip & WE_ID_BUS_MCA)) { - wdlog("%s: attached IO=0x%X IRQ=%d, RAM addr=0x%06x\n", dev->name, - dev->base_address, dev->irq, dev->ram_addr); + wdlog("%s: attached IO=0x%X IRQ=%d, RAM addr=0x%06x\n", dev->name, + dev->base_address, dev->irq, dev->ram_addr); } - return(dev); + return (dev); } - static void wd_close(void *priv) { - wd_t *dev = (wd_t *)priv; + wd_t *dev = (wd_t *) priv; wdlog("%s: closed\n", dev->name); @@ -1081,85 +1061,85 @@ static const device_config_t mca_mac_config[] = { // clang-format on const device_t wd8003e_device = { - .name = "Western Digital WD8003E", + .name = "Western Digital WD8003E", .internal_name = "wd8003e", - .flags = DEVICE_ISA, - .local = WD8003E, - .init = wd_init, - .close = wd_close, - .reset = NULL, + .flags = DEVICE_ISA, + .local = WD8003E, + .init = wd_init, + .close = wd_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = wd8003_config + .force_redraw = NULL, + .config = wd8003_config }; const device_t wd8003eb_device = { - .name = "Western Digital WD8003EB", + .name = "Western Digital WD8003EB", .internal_name = "wd8003eb", - .flags = DEVICE_ISA, - .local = WD8003EB, - .init = wd_init, - .close = wd_close, - .reset = NULL, + .flags = DEVICE_ISA, + .local = WD8003EB, + .init = wd_init, + .close = wd_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = wd8003eb_config + .force_redraw = NULL, + .config = wd8003eb_config }; const device_t wd8013ebt_device = { - .name = "Western Digital WD8013EBT", + .name = "Western Digital WD8013EBT", .internal_name = "wd8013ebt", - .flags = DEVICE_ISA, - .local = WD8013EBT, - .init = wd_init, - .close = wd_close, - .reset = NULL, + .flags = DEVICE_ISA, + .local = WD8013EBT, + .init = wd_init, + .close = wd_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = wd8013_config + .force_redraw = NULL, + .config = wd8013_config }; const device_t wd8003eta_device = { - .name = "Western Digital WD8003ET/A", + .name = "Western Digital WD8003ET/A", .internal_name = "wd8003eta", - .flags = DEVICE_MCA, - .local = WD8003ETA, - .init = wd_init, - .close = wd_close, - .reset = NULL, + .flags = DEVICE_MCA, + .local = WD8003ETA, + .init = wd_init, + .close = wd_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = mca_mac_config + .force_redraw = NULL, + .config = mca_mac_config }; const device_t wd8003ea_device = { - .name = "Western Digital WD8003E/A", + .name = "Western Digital WD8003E/A", .internal_name = "wd8003ea", - .flags = DEVICE_MCA, - .local = WD8003EA, - .init = wd_init, - .close = wd_close, - .reset = NULL, + .flags = DEVICE_MCA, + .local = WD8003EA, + .init = wd_init, + .close = wd_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = mca_mac_config + .force_redraw = NULL, + .config = mca_mac_config }; const device_t wd8013epa_device = { - .name = "Western Digital WD8013EP/A", + .name = "Western Digital WD8013EP/A", .internal_name = "wd8013epa", - .flags = DEVICE_MCA, - .local = WD8013EPA, - .init = wd_init, - .close = wd_close, - .reset = NULL, + .flags = DEVICE_MCA, + .local = WD8013EPA, + .init = wd_init, + .close = wd_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = wd8013epa_config + .force_redraw = NULL, + .config = wd8013epa_config }; diff --git a/src/network/network.c b/src/network/network.c index 7c6ab0826..69df16b22 100644 --- a/src/network/network.c +++ b/src/network/network.c @@ -73,26 +73,25 @@ #include <86box/net_wd8003.h> #ifdef _WIN32 -#define WIN32_LEAN_AND_MEAN -#include -#include +# define WIN32_LEAN_AND_MEAN +# include +# include #endif static const device_t net_none_device = { - .name = "None", + .name = "None", .internal_name = "none", - .flags = 0, - .local = NET_TYPE_NONE, - .init = NULL, - .close = NULL, - .reset = NULL, + .flags = 0, + .local = NET_TYPE_NONE, + .init = NULL, + .close = NULL, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; - static const device_t *net_cards[] = { &net_none_device, &threec503_device, @@ -118,72 +117,68 @@ static const device_t *net_cards[] = { }; netcard_conf_t net_cards_conf[NET_CARD_MAX]; -int net_card_current = 0; +int net_card_current = 0; /* Global variables. */ -int network_ndev; -netdev_t network_devs[NET_HOST_INTF_MAX]; - +int network_ndev; +netdev_t network_devs[NET_HOST_INTF_MAX]; /* Local variables. */ #ifdef ENABLE_NETWORK_LOG -int network_do_log = ENABLE_NETWORK_LOG; -static FILE *network_dump = NULL; +int network_do_log = ENABLE_NETWORK_LOG; +static FILE *network_dump = NULL; static mutex_t *network_dump_mutex; - static void network_log(const char *fmt, ...) { va_list ap; if (network_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } - static void network_dump_packet(netpkt_t *pkt) { if (!network_dump) - return; + return; struct timeval tv; gettimeofday(&tv, NULL); struct { - uint32_t ts_sec, ts_usec, incl_len, orig_len; + uint32_t ts_sec, ts_usec, incl_len, orig_len; } pcap_packet_hdr = { - tv.tv_sec, tv.tv_usec, pkt->len, pkt->len + tv.tv_sec, tv.tv_usec, pkt->len, pkt->len }; if (network_dump_mutex) - thread_wait_mutex(network_dump_mutex); + thread_wait_mutex(network_dump_mutex); size_t written; if ((written = fwrite(&pcap_packet_hdr, 1, sizeof(pcap_packet_hdr), network_dump)) < sizeof(pcap_packet_hdr)) { - network_log("NETWORK: failed to write dump packet header\n"); - fseek(network_dump, -written, SEEK_CUR); + network_log("NETWORK: failed to write dump packet header\n"); + fseek(network_dump, -written, SEEK_CUR); } else { - if ((written = fwrite(pkt->data, 1, pkt->len, network_dump)) < pkt->len) { - network_log("NETWORK: failed to write dump packet data\n"); - fseek(network_dump, -written - sizeof(pcap_packet_hdr), SEEK_CUR); - } - fflush(network_dump); + if ((written = fwrite(pkt->data, 1, pkt->len, network_dump)) < pkt->len) { + network_log("NETWORK: failed to write dump packet data\n"); + fseek(network_dump, -written - sizeof(pcap_packet_hdr), SEEK_CUR); + } + fflush(network_dump); } if (network_dump_mutex) - thread_release_mutex(network_dump_mutex); + thread_release_mutex(network_dump_mutex); } #else -#define network_log(fmt, ...) -#define network_dump_packet(pkt) +# define network_log(fmt, ...) +# define network_dump_packet(pkt) #endif - #ifdef _WIN32 static void network_winsock_clean(void) @@ -218,22 +213,22 @@ network_init(void) /* Initialize the Pcap system module, if present. */ i = net_pcap_prepare(&network_devs[network_ndev]); if (i > 0) - network_ndev += i; + network_ndev += i; #ifdef ENABLE_NETWORK_LOG /* Start packet dump. */ network_dump = fopen("network.pcap", "wb"); struct { - uint32_t magic_number; - uint16_t version_major, version_minor; - int32_t thiszone; - uint32_t sigfigs, snaplen, network; + uint32_t magic_number; + uint16_t version_major, version_minor; + int32_t thiszone; + uint32_t sigfigs, snaplen, network; } pcap_hdr = { - 0xa1b2c3d4, - 2, 4, - 0, - 0, 65535, 1 + 0xa1b2c3d4, + 2, 4, + 0, + 0, 65535, 1 }; fwrite(&pcap_hdr, sizeof(pcap_hdr), 1, network_dump); fflush(network_dump); @@ -244,11 +239,10 @@ void network_queue_init(netqueue_t *queue) { queue->head = queue->tail = 0; - for (int i=0; ipackets[i].data = calloc(1, NET_MAX_FRAME); - queue->packets[i].len = 0; + queue->packets[i].len = 0; } - } static bool @@ -267,8 +261,8 @@ static inline void network_swap_packet(netpkt_t *pkt1, netpkt_t *pkt2) { netpkt_t tmp = *pkt2; - *pkt2 = *pkt1; - *pkt1 = tmp; + *pkt2 = *pkt1; + *pkt1 = tmp; } int @@ -280,7 +274,7 @@ network_queue_put(netqueue_t *queue, uint8_t *data, int len) netpkt_t *pkt = &queue->packets[queue->head]; memcpy(pkt->data, data, len); - pkt->len = len; + pkt->len = len; queue->head = (queue->head + 1) & NET_QUEUE_LEN_MASK; return 1; } @@ -300,7 +294,8 @@ network_queue_put_swap(netqueue_t *queue, netpkt_t *src_pkt) } static int -network_queue_get_swap(netqueue_t *queue, netpkt_t *dst_pkt) { +network_queue_get_swap(netqueue_t *queue, netpkt_t *dst_pkt) +{ if (network_queue_empty(queue)) return 0; @@ -333,18 +328,17 @@ network_queue_move(netqueue_t *dst_q, netqueue_t *src_q) void network_queue_clear(netqueue_t *queue) { - for (int i=0; ipackets[i].data); queue->packets[i].len = 0; } queue->tail = queue->head = 0; } - static void network_rx_queue(void *priv) { - netcard_t *card = (netcard_t *)priv; + netcard_t *card = (netcard_t *) priv; uint32_t new_link_state = net_cards_conf[card->card_num].link_state; if (new_link_state != card->link_state) { @@ -393,7 +387,7 @@ network_rx_queue(void *priv) timer_on_auto(&card->timer, timer_period); bool activity = rx_bytes || tx_bytes; - bool led_on = card->led_timer & 0x80000000; + bool led_on = card->led_timer & 0x80000000; if ((activity && !led_on) || (card->led_timer & 0x7fffffff) >= 150000) { ui_sb_update_icon(SB_NETWORK | card->card_num, activity); card->led_timer = 0 | (activity << 31); @@ -402,7 +396,6 @@ network_rx_queue(void *priv) card->led_timer += timer_period; } - /* * Attach a network card to the system. * @@ -413,29 +406,29 @@ network_rx_queue(void *priv) netcard_t * network_attach(void *card_drv, uint8_t *mac, NETRXCB rx, NETSETLINKSTATE set_link_state) { - netcard_t *card = calloc(1, sizeof(netcard_t)); + netcard_t *card = calloc(1, sizeof(netcard_t)); card->queued_pkt.data = calloc(1, NET_MAX_FRAME); - card->card_drv = card_drv; - card->rx = rx; - card->set_link_state = set_link_state; - card->tx_mutex = thread_create_mutex(); - card->rx_mutex = thread_create_mutex(); - card->card_num = net_card_current; - card->byte_period = NET_PERIOD_10M; + card->card_drv = card_drv; + card->rx = rx; + card->set_link_state = set_link_state; + card->tx_mutex = thread_create_mutex(); + card->rx_mutex = thread_create_mutex(); + card->card_num = net_card_current; + card->byte_period = NET_PERIOD_10M; - for (int i=0; i<3; i++) { + for (int i = 0; i < 3; i++) { network_queue_init(&card->queues[i]); } switch (net_cards_conf[net_card_current].net_type) { case NET_TYPE_SLIRP: default: - card->host_drv = net_slirp_drv; + card->host_drv = net_slirp_drv; card->host_drv.priv = card->host_drv.init(card, mac, NULL); break; case NET_TYPE_PCAP: - card->host_drv = net_pcap_drv; + card->host_drv = net_pcap_drv; card->host_drv.priv = card->host_drv.init(card, mac, net_cards_conf[net_card_current].host_dev_name); break; } @@ -443,7 +436,7 @@ network_attach(void *card_drv, uint8_t *mac, NETRXCB rx, NETSETLINKSTATE set_lin if (!card->host_drv.priv) { thread_close_mutex(card->tx_mutex); thread_close_mutex(card->rx_mutex); - for (int i=0; i<3; i++) { + for (int i = 0; i < 3; i++) { network_queue_clear(&card->queues[i]); } @@ -466,7 +459,7 @@ netcard_close(netcard_t *card) thread_close_mutex(card->tx_mutex); thread_close_mutex(card->rx_mutex); - for (int i=0; i<3; i++) { + for (int i = 0; i < 3; i++) { network_queue_clear(&card->queues[i]); } @@ -474,7 +467,6 @@ netcard_close(netcard_t *card) free(card); } - /* Stop any network activity. */ void network_close(void) @@ -487,7 +479,6 @@ network_close(void) network_log("NETWORK: closed.\n"); } - /* * Reset the network card(s). * @@ -508,16 +499,15 @@ network_reset(void) #endif for (i = 0; i < NET_CARD_MAX; i++) { - if (!network_dev_available(i)) { - continue; - } + if (!network_dev_available(i)) { + continue; + } - net_card_current = i; - device_add_inst(net_cards[net_cards_conf[i].device_num], i + 1); + net_card_current = i; + device_add_inst(net_cards[net_cards_conf[i].device_num], i + 1); } } - /* Queue a packet for transmission to one of the network providers. */ void network_tx(netcard_t *card, uint8_t *bufp, int len) @@ -525,7 +515,8 @@ network_tx(netcard_t *card, uint8_t *bufp, int len) network_queue_put(&card->queues[NET_QUEUE_TX_VM], bufp, len); } -int network_tx_pop(netcard_t *card, netpkt_t *out_pkt) +int +network_tx_pop(netcard_t *card, netpkt_t *out_pkt) { int ret = 0; @@ -536,7 +527,8 @@ int network_tx_pop(netcard_t *card, netpkt_t *out_pkt) return ret; } -int network_tx_popv(netcard_t *card, netpkt_t *pkt_vec, int vec_size) +int +network_tx_popv(netcard_t *card, netpkt_t *pkt_vec, int vec_size) { int pkt_count = 0; @@ -553,7 +545,8 @@ int network_tx_popv(netcard_t *card, netpkt_t *pkt_vec, int vec_size) return pkt_count; } -int network_rx_put(netcard_t *card, uint8_t *bufp, int len) +int +network_rx_put(netcard_t *card, uint8_t *bufp, int len) { int ret = 0; @@ -564,7 +557,8 @@ int network_rx_put(netcard_t *card, uint8_t *bufp, int len) return ret; } -int network_rx_put_pkt(netcard_t *card, netpkt_t *pkt) +int +network_rx_put_pkt(netcard_t *card, netpkt_t *pkt) { int ret = 0; @@ -602,16 +596,15 @@ network_dev_to_id(char *devname) { int i = 0; - for (i=0; iinternal_name, s)) - return(c); - c++; + if (!strcmp((char *) net_cards[c]->internal_name, s)) + return (c); + c++; } return 0; diff --git a/src/network/pcap_if.c b/src/network/pcap_if.c index 384b11746..800ac5848 100644 --- a/src/network/pcap_if.c +++ b/src/network/pcap_if.c @@ -58,108 +58,101 @@ #include <86box/plat.h> #include <86box/plat_dynld.h> - -static void *pcap_handle; /* handle to WinPcap DLL */ - +static void *pcap_handle; /* handle to WinPcap DLL */ /* Pointers to the real functions. */ -static int (*f_pcap_findalldevs)(pcap_if_t **,char *); -static void (*f_pcap_freealldevs)(pcap_if_t *); -static pcap_t *(*f_pcap_open_live)(const char *,int,int,int,char *); -static int (*f_pcap_next_ex)(pcap_t*,struct pcap_pkthdr**,const unsigned char**); -static void (*f_pcap_close)(pcap_t *); +static int (*f_pcap_findalldevs)(pcap_if_t **, char *); +static void (*f_pcap_freealldevs)(pcap_if_t *); +static pcap_t *(*f_pcap_open_live)(const char *, int, int, int, char *); +static int (*f_pcap_next_ex)(pcap_t *, struct pcap_pkthdr **, const unsigned char **); +static void (*f_pcap_close)(pcap_t *); static dllimp_t pcap_imports[] = { -// clang-format off + // clang-format off { "pcap_findalldevs", &f_pcap_findalldevs }, { "pcap_freealldevs", &f_pcap_freealldevs }, { "pcap_open_live", &f_pcap_open_live }, { "pcap_next_ex", &f_pcap_next_ex }, { "pcap_close", &f_pcap_close }, { NULL, NULL }, -// clang-format on + // clang-format on }; - typedef struct { - char device[128]; - char description[128]; + char device[128]; + char description[128]; } capdev_t; - /* Retrieve an easy-to-use list of devices. */ static int get_devlist(capdev_t *list) { - char errbuf[PCAP_ERRBUF_SIZE]; + char errbuf[PCAP_ERRBUF_SIZE]; pcap_if_t *devlist, *dev; - int i = 0; + int i = 0; /* Retrieve the device list from the local machine */ if (f_pcap_findalldevs(&devlist, errbuf) == -1) { - fprintf(stderr,"Error in pcap_findalldevs_ex: %s\n", errbuf); - return(-1); + fprintf(stderr, "Error in pcap_findalldevs_ex: %s\n", errbuf); + return (-1); } - for (dev=devlist; dev!=NULL; dev=dev->next) { - strcpy(list->device, dev->name); - if (dev->description) - strcpy(list->description, dev->description); - else - memset(list->description, '\0', sizeof(list->description)); - list++; - i++; + for (dev = devlist; dev != NULL; dev = dev->next) { + strcpy(list->device, dev->name); + if (dev->description) + strcpy(list->description, dev->description); + else + memset(list->description, '\0', sizeof(list->description)); + list++; + i++; } /* Release the memory. */ f_pcap_freealldevs(devlist); - return(i); + return (i); } - /* Simple HEXDUMP routine for raw data. */ static void hex_dump(unsigned char *bufp, int len) { - char asci[20]; + char asci[20]; unsigned char c; - long addr; + long addr; addr = 0; while (len-- > 0) { - c = bufp[addr]; - if ((addr % 16) == 0) - printf("%04lx %02x", addr, c); - else - printf(" %02x", c); - asci[(addr & 15)] = (uint8_t)isprint(c) ? c : '.'; - if ((++addr % 16) == 0) { - asci[16] = '\0'; - printf(" | %s |\n", asci); - } + c = bufp[addr]; + if ((addr % 16) == 0) + printf("%04lx %02x", addr, c); + else + printf(" %02x", c); + asci[(addr & 15)] = (uint8_t) isprint(c) ? c : '.'; + if ((++addr % 16) == 0) { + asci[16] = '\0'; + printf(" | %s |\n", asci); + } } if (addr % 16) { - while (addr % 16) { - printf(" "); - asci[(addr & 15)] = ' '; - addr++; - } - asci[16] = '\0'; - printf(" | %s |\n", asci); + while (addr % 16) { + printf(" "); + asci[(addr & 15)] = ' '; + addr++; + } + asci[16] = '\0'; + printf(" | %s |\n", asci); } } - /* Print a standard Ethernet MAC address. */ static void eth_praddr(unsigned char *ptr) { printf("%02x:%02x:%02x:%02x:%02x:%02x", - ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5]); + ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5]); } - /* Print a standard Ethernet header. */ static int eth_prhdr(unsigned char *ptr) @@ -167,66 +160,66 @@ eth_prhdr(unsigned char *ptr) unsigned short type; printf("Ethernet "); - eth_praddr(ptr+6); + eth_praddr(ptr + 6); printf(" > "); eth_praddr(ptr); type = (ptr[12] << 8) | ptr[13]; printf(" type %04x\n", type); - return(14); + return (14); } - /* Capture packets from the network, and print them. */ static int start_cap(char *dev) { - char temp[PCAP_ERRBUF_SIZE]; - struct pcap_pkthdr *hdr; + char temp[PCAP_ERRBUF_SIZE]; + struct pcap_pkthdr *hdr; const unsigned char *pkt; - struct tm *ltime; - time_t now; - pcap_t *pcap; - int rc; + struct tm *ltime; + time_t now; + pcap_t *pcap; + int rc; /* Open the device for reading from it. */ pcap = f_pcap_open_live(dev, - 1518, /* MTU */ - 1, /* promisc mode */ - 10, /* timeout */ - temp); + 1518, /* MTU */ + 1, /* promisc mode */ + 10, /* timeout */ + temp); if (pcap == NULL) { - fprintf(stderr, "Pcap: open_live(%s): %s\n", dev, temp); - return(2); + fprintf(stderr, "Pcap: open_live(%s): %s\n", dev, temp); + return (2); } printf("Listening on '%s'..\n", dev); for (;;) { - rc = f_pcap_next_ex(pcap, &hdr, &pkt); - if (rc < 0) break; + rc = f_pcap_next_ex(pcap, &hdr, &pkt); + if (rc < 0) + break; - /* Did we time out? */ - if (rc == 0) continue; + /* Did we time out? */ + if (rc == 0) + continue; /* Convert the timestamp to readable format. */ - now = hdr->ts.tv_sec; + now = hdr->ts.tv_sec; ltime = localtime(&now); strftime(temp, sizeof(temp), "%H:%M:%S", ltime); - /* Process and print the packet. */ + /* Process and print the packet. */ printf("\n<< %s,%.6ld len=%u\n", - temp, hdr->ts.tv_usec, hdr->len); - rc = eth_prhdr((unsigned char *)pkt); - hex_dump((unsigned char *)pkt+rc, hdr->len-rc); + temp, hdr->ts.tv_usec, hdr->len); + rc = eth_prhdr((unsigned char *) pkt); + hex_dump((unsigned char *) pkt + rc, hdr->len - rc); } /* All done, close up. */ f_pcap_close(pcap); - return(0); + return (0); } - /* Show a list of available network interfaces. */ static void show_devs(capdev_t *list, int num) @@ -234,23 +227,22 @@ show_devs(capdev_t *list, int num) int i; if (num > 0) { - printf("Available network interfaces:\n\n"); + printf("Available network interfaces:\n\n"); - for (i=0; idevice); - if (list->description[0] != '\0') - printf(" (%s)\n", list->description); - else - printf(" (No description available)\n"); - list++; - printf("\n"); - } + for (i = 0; i < num; i++) { + printf(" %d - %s\n", i + 1, list->device); + if (list->description[0] != '\0') + printf(" (%s)\n", list->description); + else + printf(" (No description available)\n"); + list++; + printf("\n"); + } } else { - printf("No interfaces found!\nMake sure WinPcap is installed.\n"); + printf("No interfaces found!\nMake sure WinPcap is installed.\n"); } } - void pclog(const char *fmt, ...) { @@ -261,12 +253,11 @@ pclog(const char *fmt, ...) va_end(ap); } - int main(int argc, char **argv) { capdev_t interfaces[32]; - int numdev, i; + int numdev, i; /* Try loading the DLL. */ #ifdef _WIN32 @@ -278,39 +269,39 @@ main(int argc, char **argv) #endif if (pcap_handle == NULL) { #ifdef _WIN32 - fprintf(stderr, "Unable to load WinPcap DLL !\n"); + fprintf(stderr, "Unable to load WinPcap DLL !\n"); #else - fprintf(stderr, "Unable to load libpcap.so !\n"); + fprintf(stderr, "Unable to load libpcap.so !\n"); #endif - return(1); + return (1); } /* Get the list. */ numdev = get_devlist(interfaces); if (argc == 1) { - /* No arguments, just show the list. */ - show_devs(interfaces, numdev); + /* No arguments, just show the list. */ + show_devs(interfaces, numdev); - dynld_close(pcap_handle); + dynld_close(pcap_handle); - return(numdev); + return (numdev); } /* Assume argument to be the interface number to listen on. */ i = atoi(argv[1]); if (i < 0 || i > numdev) { - fprintf(stderr, "Invalid interface number %d !\n", i); + fprintf(stderr, "Invalid interface number %d !\n", i); - dynld_close(pcap_handle); + dynld_close(pcap_handle); - return(1); + return (1); } - /* Looks good, go and listen.. */ - i = start_cap(interfaces[i-1].device); +/* Looks good, go and listen.. */ + i = start_cap(interfaces[i - 1].device); dynld_close(pcap_handle); - return(i); + return (i); }