Sanitize some old chipset code
Simplistic but complex shadow implementations, few corrections and clearups
This commit is contained in:
Panagiotis
GitHub
@@ -12,7 +12,7 @@
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*
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*
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* Authors: Tiseno100
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* Authors: Tiseno100
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*
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*
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* Copyright 2020 Tiseno100
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* Copyright 2021 Tiseno100
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*
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*
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*/
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*/
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@@ -28,19 +28,15 @@
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#include <86box/timer.h>
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/mem.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/port_92.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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#include <86box/chipset.h>
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typedef struct
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typedef struct
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{
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{
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uint8_t index,
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uint8_t index,
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regs[256];
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regs[256];
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port_92_t * port_92;
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port_92_t *port_92;
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} cs4031_t;
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} cs4031_t;
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#ifdef ENABLE_CS4031_LOG
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#ifdef ENABLE_CS4031_LOG
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@@ -50,10 +46,11 @@ cs4031_log(const char *fmt, ...)
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{
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{
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va_list ap;
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va_list ap;
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if (cs4031_do_log) {
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if (cs4031_do_log)
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va_start(ap, fmt);
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{
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pclog_ex(fmt, ap);
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va_start(ap, fmt);
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va_end(ap);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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}
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}
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#else
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#else
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@@ -62,139 +59,130 @@ cs4031_log(const char *fmt, ...)
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static void cs4031_shadow_recalc(cs4031_t *dev)
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static void cs4031_shadow_recalc(cs4031_t *dev)
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{
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{
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mem_set_mem_state_both(0xa0000, 0x10000, (dev->regs[0x18] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xb0000, 0x10000, (dev->regs[0x18] & 0x02) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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uint32_t romc0000, romc4000, romc8000, romcc000, romd0000, rome0000, romf0000;
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for (uint32_t i = 0; i < 7; i++)
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{
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/* Register 18h */
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if (i < 4)
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if(dev->regs[0x18] & 0x01)
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mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, ((dev->regs[0x19] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xa0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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else
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else
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mem_set_mem_state_both(0xd0000 + ((i - 4) << 16), 0x10000, ((dev->regs[0x19] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xa0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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}
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shadowbios = !!(dev->regs[0x19] & 0x40);
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if(dev->regs[0x18] & 0x02)
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shadowbios_write = !!(dev->regs[0x1a] & 0x40);
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mem_set_mem_state_both(0xb0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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else
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mem_set_mem_state_both(0xb0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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/* Register 19h-1ah-1bh*/
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shadowbios = (dev->regs[0x19] & 0x40);
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shadowbios_write = (dev->regs[0x1a] & 0x40);
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/* ROMCS only functions if shadow write is disabled */
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romc0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x01)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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romc4000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x02)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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romc8000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x04)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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romcc000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x08)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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romd0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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rome0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x20)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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romf0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x40)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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mem_set_mem_state_both(0xc0000, 0x4000, ((dev->regs[0x19] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x01) ? MEM_WRITE_INTERNAL : romc0000));
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mem_set_mem_state_both(0xc4000, 0x4000, ((dev->regs[0x19] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x02) ? MEM_WRITE_INTERNAL : romc4000));
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mem_set_mem_state_both(0xc8000, 0x4000, ((dev->regs[0x19] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x04) ? MEM_WRITE_INTERNAL : romc8000));
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mem_set_mem_state_both(0xcc000, 0x4000, ((dev->regs[0x19] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x08) ? MEM_WRITE_INTERNAL : romcc000));
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mem_set_mem_state_both(0xd0000, 0x10000, ((dev->regs[0x19] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x10) ? MEM_WRITE_INTERNAL : romd0000));
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mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[0x19] & 0x20) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x20) ? MEM_WRITE_INTERNAL : rome0000));
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mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[0x19] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x40) ? MEM_WRITE_INTERNAL : romf0000));
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}
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}
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static void
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static void
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cs4031_write(uint16_t addr, uint8_t val, void *priv)
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cs4031_write(uint16_t addr, uint8_t val, void *priv)
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{
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{
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cs4031_t *dev = (cs4031_t *) priv;
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cs4031_t *dev = (cs4031_t *)priv;
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switch (addr) {
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switch (addr)
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case 0x22:
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{
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dev->index = val;
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case 0x22:
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break;
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dev->index = val;
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case 0x23:
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break;
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case 0x23:
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cs4031_log("CS4031: dev->regs[%02x] = %02x\n", dev->index, val);
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cs4031_log("CS4031: dev->regs[%02x] = %02x\n", dev->index, val);
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dev->regs[dev->index] = val;
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switch (dev->index)
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{
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switch(dev->index){
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case 0x05:
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case 0x06:
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dev->regs[dev->index] = val & 0x3f;
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cpu_update_waitstates();
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break;
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break;
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case 0x18:
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case 0x06:
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case 0x19:
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dev->regs[dev->index] = val & 0xbc;
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case 0x1a:
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break;
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case 0x1b:
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case 0x07:
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dev->regs[dev->index] = val & 0x0f;
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break;
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case 0x10:
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dev->regs[dev->index] = val & 0x3d;
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break;
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case 0x11:
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dev->regs[dev->index] = val & 0x8d;
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break;
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case 0x12:
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case 0x13:
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dev->regs[dev->index] = val & 0x8d;
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break;
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17:
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dev->regs[dev->index] = val & 0x7f;
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break;
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case 0x18:
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dev->regs[dev->index] = val & 0xf3;
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cs4031_shadow_recalc(dev);
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cs4031_shadow_recalc(dev);
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break;
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break;
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case 0x1c:
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case 0x19:
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case 0x1a:
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if(dev->regs[0x1c] & 0x20)
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dev->regs[dev->index] = val & 0x7f;
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port_92_add(dev->port_92);
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cs4031_shadow_recalc(dev);
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else
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port_92_remove(dev->port_92);
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break;
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break;
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case 0x1b:
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dev->regs[dev->index] = val;
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break;
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case 0x1c:
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dev->regs[dev->index] = val & 0xb3;
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port_92_set_features(dev->port_92, val & 0x10, val & 0x20);
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break;
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}
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}
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break;
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break;
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}
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}
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}
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}
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static uint8_t
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static uint8_t
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cs4031_read(uint16_t addr, void *priv)
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cs4031_read(uint16_t addr, void *priv)
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{
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{
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uint8_t ret = 0xff;
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cs4031_t *dev = (cs4031_t *)priv;
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cs4031_t *dev = (cs4031_t *) priv;
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switch (addr) {
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return (addr == 0x23) ? dev->regs[dev->index] : 0xff;
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case 0x23:
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ret = dev->regs[dev->index];
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break;
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}
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return ret;
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}
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}
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static void
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static void
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cs4031_close(void *priv)
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cs4031_close(void *priv)
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{
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{
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cs4031_t *dev = (cs4031_t *) priv;
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cs4031_t *dev = (cs4031_t *)priv;
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free(dev);
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free(dev);
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}
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}
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static void *
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static void *
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cs4031_init(const device_t *info)
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cs4031_init(const device_t *info)
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{
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{
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cs4031_t *dev = (cs4031_t *) malloc(sizeof(cs4031_t));
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cs4031_t *dev = (cs4031_t *)malloc(sizeof(cs4031_t));
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memset(dev, 0, sizeof(cs4031_t));
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memset(dev, 0, sizeof(cs4031_t));
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dev->port_92 = device_add(&port_92_device);
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dev->port_92 = device_add(&port_92_device);
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io_sethandler(0x022, 0x0001, cs4031_read, NULL, NULL, cs4031_write, NULL, NULL, dev);
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io_sethandler(0x023, 0x0001, cs4031_read, NULL, NULL, cs4031_write, NULL, NULL, dev);
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dev->regs[0x05] = 0x05;
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dev->regs[0x05] = 0x05;
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dev->regs[0x18] = 0x00;
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dev->regs[0x19] = 0x00;
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dev->regs[0x1a] = 0x00;
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dev->regs[0x1b] = 0x60;
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dev->regs[0x1b] = 0x60;
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cs4031_shadow_recalc(dev);
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io_sethandler(0x0022, 0x0002, cs4031_read, NULL, NULL, cs4031_write, NULL, NULL, dev);
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return dev;
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return dev;
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}
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}
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const device_t cs4031_device = {
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const device_t cs4031_device = {
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"Chips & Technogies CS4031",
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"Chips & Technogies CS4031",
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0,
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0,
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0,
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0,
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cs4031_init, cs4031_close, NULL,
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cs4031_init,
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{ NULL }, NULL, NULL,
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cs4031_close,
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NULL
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NULL,
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};
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{NULL},
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NULL,
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NULL,
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NULL};
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@@ -12,7 +12,7 @@
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*
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*
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||||||
* Authors: Tiseno100
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* Authors: Tiseno100
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||||||
*
|
*
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||||||
* Copyright 2020 Tiseno100
|
* Copyright 2021 Tiseno100
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*
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*
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*/
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*/
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@@ -28,130 +28,109 @@
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#include <86box/timer.h>
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#include <86box/timer.h>
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#include <86box/io.h>
|
#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/mem.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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#include <86box/chipset.h>
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#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
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#ifdef ENABLE_OPTI283_LOG
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int opti283_do_log = ENABLE_OPTI283_LOG;
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static void
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opti283_log(const char *fmt, ...)
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{
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va_list ap;
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|
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if (opti283_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define opti283_log(fmt, ...)
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#endif
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typedef struct
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typedef struct
|
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{
|
{
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uint8_t index,
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uint8_t index,
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regs[256];
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regs[256];
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} opti283_t;
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} opti283_t;
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static void opti283_shadow_recalc(opti283_t *dev)
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static void opti283_shadow_recalc(opti283_t *dev)
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{
|
{
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uint32_t base, i;
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mem_set_mem_state_both(0xf0000, 0x10000, (dev->regs[0x11] & 0x80) ? (MEM_READ_EXTANY | MEM_WRITE_INTERNAL) : (MEM_READ_INTERNAL | ((dev->regs[0x14] & 0x80) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED)));
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uint32_t shflagsc, shflagsd, shflagse, shflagsf;
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shadowbios = !(dev->regs[0x11] & 0x80);
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for (uint32_t i = 0; i < 4; i++)
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shadowbios_write = (dev->regs[0x11] & 0x80);
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{
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if (dev->regs[0x11] & 0x40)
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mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, (dev->regs[0x12] & (1 << (4 + i))) ? (MEM_READ_INTERNAL | ((dev->regs[0x11] & 4) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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if(dev->regs[0x11] & 0x10){
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if (dev->regs[0x11] & 0x20)
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shflagsc = MEM_READ_INTERNAL;
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mem_set_mem_state_both(0xd0000 + (i << 14), 0x4000, (dev->regs[0x12] & (1 << i)) ? (MEM_READ_INTERNAL | ((dev->regs[0x11] & 2) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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shflagsc |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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else
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} else shflagsc = disabled_shadow;
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mem_set_mem_state_both(0xd0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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if(dev->regs[0x11] & 0x20){
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shflagsd = MEM_READ_INTERNAL;
|
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shflagsd |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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} else shflagsd = disabled_shadow;
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|
||||||
if(dev->regs[0x11] & 0x40){
|
|
||||||
shflagse = MEM_READ_INTERNAL;
|
|
||||||
shflagse |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
|
|
||||||
} else shflagse = disabled_shadow;
|
|
||||||
|
|
||||||
if(!(dev->regs[0x11] & 0x80)){
|
|
||||||
shflagsf = MEM_READ_INTERNAL | MEM_WRITE_DISABLED;
|
|
||||||
} else shflagsf = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
|
|
||||||
|
|
||||||
mem_set_mem_state_both(0xf0000, 0x10000, shflagsf);
|
|
||||||
|
|
||||||
for(i = 4; i < 8; i++){
|
|
||||||
base = 0xc0000 + ((i-4) << 14);
|
|
||||||
mem_set_mem_state_both(base, 0x4000, (dev->regs[0x13] & (1 << i)) ? shflagsc : disabled_shadow);
|
|
||||||
}
|
|
||||||
|
|
||||||
for(i = 0; i < 4; i++){
|
|
||||||
base = 0xd0000 + (i << 14);
|
|
||||||
mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagsd : disabled_shadow);
|
|
||||||
}
|
|
||||||
|
|
||||||
for(i = 4; i < 8; i++){
|
|
||||||
base = 0xe0000 + ((i-4) << 14);
|
|
||||||
mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagse : disabled_shadow);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
if (dev->regs[0x11] & 0x10)
|
||||||
|
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, (dev->regs[0x13] & (1 << (4 + i))) ? (MEM_READ_INTERNAL | ((dev->regs[0x11] & 1) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
|
||||||
|
else
|
||||||
|
mem_set_mem_state_both(0xc0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void
|
static void
|
||||||
opti283_write(uint16_t addr, uint8_t val, void *priv)
|
opti283_write(uint16_t addr, uint8_t val, void *priv)
|
||||||
{
|
{
|
||||||
opti283_t *dev = (opti283_t *) priv;
|
opti283_t *dev = (opti283_t *)priv;
|
||||||
|
|
||||||
switch (addr) {
|
switch (addr)
|
||||||
case 0x22:
|
{
|
||||||
dev->index = val;
|
case 0x22:
|
||||||
break;
|
dev->index = val;
|
||||||
case 0x24:
|
break;
|
||||||
/* pclog("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val); */
|
case 0x24:
|
||||||
dev->regs[dev->index] = val;
|
opti283_log("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val);
|
||||||
|
|
||||||
switch(dev->index){
|
switch (dev->index)
|
||||||
case 0x10:
|
{
|
||||||
cpu_update_waitstates();
|
case 0x10:
|
||||||
|
dev->regs[dev->index] = val;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0x11:
|
case 0x11:
|
||||||
case 0x12:
|
case 0x12:
|
||||||
case 0x13:
|
case 0x13:
|
||||||
|
case 0x14:
|
||||||
|
dev->regs[dev->index] = val;
|
||||||
opti283_shadow_recalc(dev);
|
opti283_shadow_recalc(dev);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
static uint8_t
|
static uint8_t
|
||||||
opti283_read(uint16_t addr, void *priv)
|
opti283_read(uint16_t addr, void *priv)
|
||||||
{
|
{
|
||||||
uint8_t ret = 0xff;
|
opti283_t *dev = (opti283_t *)priv;
|
||||||
opti283_t *dev = (opti283_t *) priv;
|
return (addr == 0x24) ? dev->regs[dev->index] : 0xff;
|
||||||
|
|
||||||
switch (addr) {
|
|
||||||
case 0x24:
|
|
||||||
ret = dev->regs[dev->index];
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
static void
|
static void
|
||||||
opti283_close(void *priv)
|
opti283_close(void *priv)
|
||||||
{
|
{
|
||||||
opti283_t *dev = (opti283_t *) priv;
|
opti283_t *dev = (opti283_t *)priv;
|
||||||
|
|
||||||
free(dev);
|
free(dev);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
static void *
|
static void *
|
||||||
opti283_init(const device_t *info)
|
opti283_init(const device_t *info)
|
||||||
{
|
{
|
||||||
opti283_t *dev = (opti283_t *) malloc(sizeof(opti283_t));
|
opti283_t *dev = (opti283_t *)malloc(sizeof(opti283_t));
|
||||||
memset(dev, 0, sizeof(opti283_t));
|
memset(dev, 0, sizeof(opti283_t));
|
||||||
|
|
||||||
io_sethandler(0x022, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
|
io_sethandler(0x0022, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
|
||||||
io_sethandler(0x024, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
|
io_sethandler(0x0024, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
|
||||||
|
|
||||||
dev->regs[0x10] = 0x3f;
|
dev->regs[0x10] = 0x3f;
|
||||||
dev->regs[0x11] = 0xf0;
|
dev->regs[0x11] = 0xf0;
|
||||||
@@ -160,12 +139,14 @@ opti283_init(const device_t *info)
|
|||||||
return dev;
|
return dev;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
const device_t opti283_device = {
|
const device_t opti283_device = {
|
||||||
"OPTi 82C283",
|
"OPTi 82C283",
|
||||||
0,
|
0,
|
||||||
0,
|
0,
|
||||||
opti283_init, opti283_close, NULL,
|
opti283_init,
|
||||||
{ NULL }, NULL, NULL,
|
opti283_close,
|
||||||
NULL
|
NULL,
|
||||||
};
|
{NULL},
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
NULL};
|
||||||
|
|||||||
Reference in New Issue
Block a user