diff --git a/src/86box.h b/src/86box.h
index 7df924036..30a5088e1 100644
--- a/src/86box.h
+++ b/src/86box.h
@@ -99,6 +99,7 @@ extern int vid_cga_contrast, /* (C) video */
gfxcard; /* (C) graphics/video card */
extern int serial_enabled[], /* (C) enable serial ports */
bugger_enabled, /* (C) enable ISAbugger */
+ postcard_enabled, /* (C) enable POST card */
isamem_type[], /* (C) enable ISA mem cards */
isartc_type; /* (C) enable ISA RTC card */
extern int sound_is_float, /* (C) sound uses FP values */
diff --git a/src/chipset/chipset.h b/src/chipset/chipset.h
index 025bf16a8..bedb3ee74 100644
--- a/src/chipset/chipset.h
+++ b/src/chipset/chipset.h
@@ -44,6 +44,7 @@ extern const device_t i430tx_device;
#if defined(DEV_BRANCH) && defined(USE_I686)
extern const device_t i440fx_device;
extern const device_t i440bx_device;
+extern const device_t i440zx_device;
#endif
/* NEAT */
diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c
index c03feb964..b5aba5a15 100644
--- a/src/chipset/intel_4x0.c
+++ b/src/chipset/intel_4x0.c
@@ -44,7 +44,8 @@ enum
INTEL_430TX
#if defined(DEV_BRANCH) && defined(USE_I686)
,INTEL_440FX,
- INTEL_440BX
+ INTEL_440BX,
+ INTEL_440ZX
#endif
};
@@ -64,8 +65,6 @@ typedef struct
static void
i4x0_map(uint32_t addr, uint32_t size, int state)
{
- // pclog("i4x0_map(%08X, %08X, %02X)\n", addr, size, state);
-
switch (state & 3) {
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
@@ -103,7 +102,6 @@ pm2_cntrl_read(uint16_t addr, void *p)
{
i4x0_t *dev = (i4x0_t *) p;
- // pclog("PM2_CTL read: %02X\n", dev->pm2_cntrl & 0x01);
return dev->pm2_cntrl & 0x01;
}
@@ -113,7 +111,6 @@ pm2_cntrl_write(uint16_t addr, uint8_t val, void *p)
{
i4x0_t *dev = (i4x0_t *) p;
- // pclog("PM2_CTL write: %02X\n", val);
dev->pm2_cntrl = val & 0x01;
}
@@ -131,15 +128,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#endif
#if defined(DEV_BRANCH) && defined(USE_I686)
- if (func > dev->max_func) {
+ if (func > dev->max_func)
#else
- if (func > 0) {
+ if (func > 0)
#endif
- // pclog("invalid write %02X to %02X:%02X\n", val, func, addr);
return;
- }
-
- // pclog("write %02X to %02X:%02X\n", val, func, addr);
if ((addr >= 0x10) && (addr < 0x4f))
return;
@@ -149,7 +142,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX:
#if defined(DEV_BRANCH) && defined(USE_I686)
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
#endif
default:
regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42);
@@ -166,7 +159,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
- case INTEL_440FX: case INTEL_440BX:
+ case INTEL_440FX: case INTEL_440BX: case INTEL_440ZX:
#endif
regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01);
break;
@@ -185,7 +178,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x07] &= ~(val & 0xf9);
break;
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x07] &= ~(val & 0xf0);
break;
#endif
@@ -211,7 +204,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x12:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x12] = (val & 0xc0);
i4x0_mask_bar(regs);
break;
@@ -219,7 +212,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x13:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x13] = val;
i4x0_mask_bar(regs);
break;
@@ -227,7 +220,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x2c: case 0x2d: case 0x2e: case 0x2f:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr]) {
regs[addr] = val;
regs_l[addr] = 1;
@@ -274,6 +267,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb);
break;
+ case INTEL_440ZX:
+ regs[0x50] = (regs[0x50] & 0x34) | (val & 0xcb);
+ break;
#endif
}
break;
@@ -286,7 +282,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x51] = (val & 0xc3);
break;
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f);
break;
#endif
@@ -308,7 +304,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x52] = val;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x52] = val & 0x07;
break;
#endif
@@ -326,6 +322,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX: case INTEL_430TX:
regs[0x53] = val & 0x3f;
break;
+ case INTEL_440BX:
+ /* Not applicable to 440ZX as that does not support ECC. */
+ regs[0x53] = val;
+ break;
}
break;
case 0x54:
@@ -400,6 +400,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[0x57] = val & 0x3f;
break;
+ case INTEL_440ZX:
+ regs[0x57] = val & 0x2f;
+ break;
#endif
}
break;
@@ -411,7 +414,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case INTEL_430NX:
#if defined(DEV_BRANCH) && defined(USE_I686)
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
#endif
regs[0x58] = val & 0x03;
break;
@@ -492,6 +495,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
+ case INTEL_440ZX:
#endif
default:
regs[addr] = val;
@@ -512,6 +516,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
+ case INTEL_440ZX:
#endif
regs[addr] = val;
break;
@@ -528,6 +533,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430NX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
+ case INTEL_440ZX:
#endif
regs[addr] = val;
break;
@@ -538,6 +544,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430NX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
+ case INTEL_440ZX:
#endif
regs[addr] = val;
break;
@@ -565,6 +572,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7);
break;
+ case INTEL_440ZX:
+ regs[0x68] = (regs[0x68] & 0x3f) | (val & 0xc0);
+ break;
#endif
}
break;
@@ -579,6 +589,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX:
regs[0x69] = val & 0x07;
break;
+#if defined(DEV_BRANCH) && defined(USE_I686)
+ case INTEL_440ZX:
+ regs[0x69] = val & 0x3f;
+ break;
+#endif
}
break;
case 0x6a: case 0x6b:
@@ -589,6 +604,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#endif
regs[addr] = val;
break;
+#if defined(DEV_BRANCH) && defined(USE_I686)
+ case INTEL_440ZX:
+ if (addr == 0x6a)
+ regs[addr] = val & 0xfc;
+ else
+ regs[addr] = val & 0x33;
+ break;
+#endif
}
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
@@ -597,6 +620,12 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[addr] = val;
break;
+ case INTEL_440ZX:
+ if (addr == 0x6c)
+ regs[addr] = val & 0x03;
+ else if (addr == 0x6d)
+ regs[addr] = val & 0xcf;
+ break;
}
break;
#endif
@@ -652,7 +681,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x73] = val & 0x03;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x73] = val;
break;
#endif
@@ -662,7 +691,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_430VX:
#if defined(DEV_BRANCH) && defined(USE_I686)
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
#endif
regs[0x74] = val;
break;
@@ -672,13 +701,13 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x75: case 0x76:
case 0x7b:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
}
break;
case 0x77:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x77] = val & 0x03;
}
break;
@@ -689,7 +718,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x78] = val & 0xcf;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x78] = val & 0x0f;
break;
#endif
@@ -702,10 +731,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
- // pclog("430TX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis");
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x79] = val;
break;
#endif
@@ -714,12 +742,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x7a:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x7a] = (regs[0x7a] & 0x0a) | (val & 0xf5);
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
- // pclog("440BX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis");
break;
}
break;
@@ -731,7 +758,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x7c] = val & 0x8f;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x7c] = val & 0x1f;
break;
#endif
@@ -753,7 +780,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x80:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x80] &= ~(val & 0x03);
break;
}
@@ -768,7 +795,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x80] = val & 0x1b;
break;
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x7c] = val;
break;
#endif
@@ -780,6 +807,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
#endif
+ /* Not applicable on 82443ZX. */
regs[0x91] &= ~(val & 0x11);
break;
}
@@ -787,7 +815,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x92:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x92] &= ~(val & 0x1f);
break;
}
@@ -802,28 +830,28 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xa8: case 0xa9:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0x03);
break;
}
break;
case 0xb0:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0xb0] = (val & 0x80);
break;
}
break;
case 0xb1:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0xb1] = (val & 0xa0);
break;
}
break;
case 0xb4:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0xb4] = (val & 0x3f);
i4x0_mask_bar(regs);
break;
@@ -831,17 +859,37 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xb9:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0xb9] = (val & 0xf0);
break;
}
break;
- case 0xba: case 0xbb: case 0xca: case 0xcb:
+ case 0xba: case 0xbb:
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
+ switch (dev->type) {
+ case INTEL_440BX: case INTEL_440ZX:
+ regs[addr] = val;
+ break;
+ }
+ break;
+ case 0xca:
switch (dev->type) {
case INTEL_440BX:
regs[addr] = val;
break;
+ case INTEL_440ZX:
+ regs[addr] = val & 0xe7;
+ break;
+ }
+ break;
+ case 0xcb:
+ switch (dev->type) {
+ case INTEL_440BX:
+ regs[addr] = val;
+ break;
+ case INTEL_440ZX:
+ regs[addr] = val & 0xa7;
+ break;
}
break;
case 0xcc:
@@ -849,12 +897,15 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[0xcc] = (val & 0x7f);
break;
+ case INTEL_440ZX:
+ regs[0xcc] = (val & 0x58);
+ break;
}
break;
case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4:
case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr])
regs[addr] = val;
break;
@@ -862,7 +913,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xe5: case 0xed:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr])
regs[addr] = (val & 0x3f);
break;
@@ -870,7 +921,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xe7:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0xe7] = 0x80;
for (i = 0; i < 16; i++)
regs_l[0xe0 + i] = !!(val & 0x80);
@@ -882,14 +933,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xf0:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0xf0] = (val & 0xc0);
break;
}
break;
case 0xf1:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0xf1] = (val & 0x03);
break;
}
@@ -897,21 +948,21 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
} else if (func == 1) switch (addr) {
case 0x04:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x04] = (val & 0x1f);
break;
}
break;
case 0x05:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x05] = (val & 0x01);
break;
}
break;
case 0x0d: case 0x1b:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0xf8);
break;
}
@@ -920,7 +971,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x21: case 0x23:
case 0x25: case 0x27:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
}
@@ -929,21 +980,21 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x20: case 0x22:
case 0x24: case 0x26:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0xf0);
break;
}
break;
case 0x1f:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x1f] &= ~(val & 0xf0);
break;
}
break;
case 0x3e:
switch (dev->type) {
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x3e] = (val & 0xed);
break;
}
@@ -965,13 +1016,12 @@ i4x0_read(int func, int addr, void *priv)
#endif
#if defined(DEV_BRANCH) && defined(USE_I686)
- if (func > dev->max_func) {
+ if (func > dev->max_func)
#else
- if (func > 0) {
+ if (func > 0)
#endif
ret = 0xff;
- // pclog("invalid read %02X from %02X:%02X\n", ret, func, addr);
- } else {
+ else {
ret = regs[addr];
#if defined(DEV_BRANCH) && defined(USE_I686)
/* Special behavior for 440FX register 0x93 which is basically TRC in PCI space
@@ -979,7 +1029,6 @@ i4x0_read(int func, int addr, void *priv)
if ((func == 0) && (addr == 0x93) && (dev->type == INTEL_440FX))
ret = (ret & 0xf9) | (trc_read(0x0093, NULL) & 0x06);
#endif
- // pclog("read %02X from %02X:%02X\n", ret, func, addr);
}
return ret;
@@ -1006,7 +1055,7 @@ i4x0_reset(void *priv)
i4x0_write(0, 0x72, 0x00, priv);
#if defined(DEV_BRANCH) && defined(USE_I686)
- if (dev->type == INTEL_440BX) {
+ if ((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) {
for (i = 0; i <= dev->max_func; i++)
memset(dev->regs_locked[i], 0x00, 256 * sizeof(uint8_t));
}
@@ -1185,11 +1234,12 @@ static void
regs[0x71] = 0x10;
regs[0x72] = 0x02;
break;
- case INTEL_440BX:
+ case INTEL_440BX: case INTEL_440ZX:
regs[0x7a] = (info->local >> 8) & 0xff;
dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1;
regs[0x02] = (regs[0x7a] & 0x02) ? 0x92 : 0x90; regs[0x03] = 0x71; /* 82443BX */
+ regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10;
regs[0x08] = 0x02;
regs[0x10] = 0x08;
regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0;
@@ -1234,7 +1284,7 @@ static void
smbase = 0xa0000;
#if defined(DEV_BRANCH) && defined(USE_I686)
- if ((dev->type == INTEL_440BX) && (dev->max_func == 1)) {
+ if (((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) && (dev->max_func == 1)) {
regs = (uint8_t *) dev->regs[1];
regs[0x00] = 0x86; regs[0x01] = 0x80; /* Intel */
@@ -1421,4 +1471,19 @@ const device_t i440bx_device =
NULL,
NULL
};
+
+
+const device_t i440zx_device =
+{
+ "Intel 82443ZX",
+ DEVICE_PCI,
+ 0x8000 | INTEL_440ZX,
+ i4x0_init,
+ i4x0_close,
+ i4x0_reset,
+ NULL,
+ NULL,
+ NULL,
+ NULL
+};
#endif
diff --git a/src/chipset/intel_4x0.c.old b/src/chipset/intel_4x0.c.old
deleted file mode 100644
index 3addcff70..000000000
--- a/src/chipset/intel_4x0.c.old
+++ /dev/null
@@ -1,529 +0,0 @@
-/*
- * 86Box A hypervisor and IBM PC system emulator that specializes in
- * running old operating systems and software designed for IBM
- * PC systems and compatibles from 1981 through fairly recent
- * system designs based on the PCI bus.
- *
- * This file is part of the 86Box distribution.
- *
- * Implementation of the Intel PCISet chips from 420TX to 440FX.
- *
- * Version: @(#)intel_4x0.c 1.0.3 2020/01/24
- *
- * Authors: Sarah Walker,
- * Miran Grca,
- *
- * Copyright 2019,2020 Miran Grca.
- */
-#include
-#include
-#include
-#include
-#include
-#include "86box.h"
-#include "cpu.h"
-#include "mem.h"
-#include "86box_io.h"
-#include "rom.h"
-#include "pci.h"
-#include "device.h"
-#include "keyboard.h"
-#include "chipset.h"
-
-
-enum
-{
- INTEL_420TX,
- INTEL_430LX,
- INTEL_430NX,
- INTEL_430FX,
- INTEL_430FX_PB640,
- INTEL_430HX,
- INTEL_430VX,
- INTEL_430TX
-#if defined(DEV_BRANCH) && defined(USE_I686)
- ,INTEL_440FX
-#endif
-};
-
-typedef struct
-{
- uint8_t pm2_cntrl;
- uint8_t regs[256];
- int type;
-} i4x0_t;
-static void
-i4x0_map(uint32_t addr, uint32_t size, int state)
-{
- // pclog("i4x0_map(%08X, %08X, %02X)\n", addr, size, state);
-
- switch (state & 3) {
- case 0:
- mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
- break;
- case 1:
- mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
- break;
- case 2:
- mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
- break;
- case 3:
- mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
- break;
- }
- flushmmucache_nopc();
-}
-
-
-static void
-i4x0_write(int func, int addr, uint8_t val, void *priv)
-{
- i4x0_t *dev = (i4x0_t *) priv;
-
- if (func)
- return;
-
- pclog("write %02X to %08X\n", val, addr);
-
- if ((addr >= 0x10) && (addr < 0x4f))
- return;
-
- switch (addr) {
- case 0x00: case 0x01: case 0x02: case 0x03:
- case 0x08: case 0x09: case 0x0a: case 0x0b:
- case 0x0c: case 0x0e:
- return;
-
- case 0x04: /*Command register*/
- if (dev->type >= INTEL_430FX) {
- if (dev->type == INTEL_430FX_PB640)
- val &= 0x06;
- else
- val &= 0x02;
- } else
- val &= 0x42;
- val |= 0x04;
- break;
- case 0x05:
- if (dev->type >= INTEL_430FX)
- val = 0;
- else
- val &= 0x01;
- break;
-
- case 0x06: /*Status*/
- val = 0;
- break;
- case 0x07:
- if (dev->type >= INTEL_430HX) {
- val &= 0x80;
- val |= 0x02;
- } else {
- val = 0x02;
- if (dev->type == INTEL_430FX_PB640)
- val |= 0x20;
- }
- break;
-
- case 0x52: /*Cache Control Register*/
-#if defined(DEV_BRANCH) && defined(USE_I686)
- if (dev->type < INTEL_440FX) {
-#endif
- cpu_cache_ext_enabled = (val & 0x01);
- cpu_update_waitstates();
-#if defined(DEV_BRANCH) && defined(USE_I686)
- }
-#endif
- break;
-
- case 0x59: /*PAM0*/
- if ((dev->regs[0x59] ^ val) & 0xf0) {
- i4x0_map(0xf0000, 0x10000, val >> 4);
- shadowbios = (val & 0x10);
- }
- break;
- case 0x5a: /*PAM1*/
- if ((dev->regs[0x5a] ^ val) & 0x0f)
- i4x0_map(0xc0000, 0x04000, val & 0xf);
- if ((dev->regs[0x5a] ^ val) & 0xf0)
- i4x0_map(0xc4000, 0x04000, val >> 4);
- break;
- case 0x5b: /*PAM2*/
- if ((dev->regs[0x5b] ^ val) & 0x0f)
- i4x0_map(0xc8000, 0x04000, val & 0xf);
- if ((dev->regs[0x5b] ^ val) & 0xf0)
- i4x0_map(0xcc000, 0x04000, val >> 4);
- break;
- case 0x5c: /*PAM3*/
- if ((dev->regs[0x5c] ^ val) & 0x0f)
- i4x0_map(0xd0000, 0x04000, val & 0xf);
- if ((dev->regs[0x5c] ^ val) & 0xf0)
- i4x0_map(0xd4000, 0x04000, val >> 4);
- break;
- case 0x5d: /*PAM4*/
- if ((dev->regs[0x5d] ^ val) & 0x0f)
- i4x0_map(0xd8000, 0x04000, val & 0xf);
- if ((dev->regs[0x5d] ^ val) & 0xf0)
- i4x0_map(0xdc000, 0x04000, val >> 4);
- break;
- case 0x5e: /*PAM5*/
- if ((dev->regs[0x5e] ^ val) & 0x0f)
- i4x0_map(0xe0000, 0x04000, val & 0xf);
- if ((dev->regs[0x5e] ^ val) & 0xf0)
- i4x0_map(0xe4000, 0x04000, val >> 4);
- break;
- case 0x5f: /*PAM6*/
- if ((dev->regs[0x5f] ^ val) & 0x0f)
- i4x0_map(0xe8000, 0x04000, val & 0xf);
- if ((dev->regs[0x5f] ^ val) & 0xf0)
- i4x0_map(0xec000, 0x04000, val >> 4);
- break;
- case 0x72: /*SMRAM*/
- if ((dev->type >= INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x48))
- i4x0_map(0xa0000, 0x20000, ((val & 0x48) == 0x48) ? 3 : 0);
- else if ((dev->type < INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x20))
- i4x0_map(0xa0000, 0x20000, ((val & 0x20) == 0x20) ? 3 : 0);
- break;
-
- case 0x73: case 0x74:
- // pclog("Access %i at %08X\n", dev->regs[0x73] & 3, dev->regs[0x74] << 19);
- break;
- }
-
- dev->regs[addr] = val;
-}
-
-
-static uint8_t
-i4x0_read(int func, int addr, void *priv)
-{
- i4x0_t *dev = (i4x0_t *) priv;
- uint8_t ret = 0xff;
-
- if (!func) {
- ret = dev->regs[addr];
- pclog("read %02X from %08X\n", ret, addr);
-
- // if (addr == 0x50)
- // pclog("read %02X from %08X\n", ret, addr);
- }
-
- return ret;
-}
-
-
-static void
-i4x0_reset(void *priv)
-{
- i4x0_t *i4x0 = (i4x0_t *)priv;
-
- i4x0_write(0, 0x59, 0x00, priv);
- i4x0_write(0, 0x5e, 0x00, priv);
- i4x0_write(0, 0x5f, 0x00, priv);
- if (i4x0->type >= INTEL_430FX)
- i4x0_write(0, 0x72, 0x02, priv);
-
- smbase = 0xa0000;
-}
-
-
-static void
-i4x0_close(void *p)
-{
- i4x0_t *i4x0 = (i4x0_t *)p;
-
- free(i4x0);
-}
-
-
-static uint8_t
-pm2_cntrl_read(uint16_t addr, void *p)
-{
- i4x0_t *dev = (i4x0_t *) p;
-
- return dev->pm2_cntrl & 0x01;
-}
-
-
-static void
-pm2_cntrl_write(uint16_t addr, uint8_t val, void *p)
-{
- i4x0_t *dev = (i4x0_t *) p;
-
- dev->pm2_cntrl = val & 0x01;
-}
-
-
-static void
-*i4x0_init(const device_t *info)
-{
- i4x0_t *i4x0 = (i4x0_t *) malloc(sizeof(i4x0_t));
- memset(i4x0, 0, sizeof(i4x0_t));
-
- i4x0->type = info->local;
-
- i4x0->regs[0x00] = 0x86; i4x0->regs[0x01] = 0x80; /*Intel*/
- switch(i4x0->type) {
- case INTEL_420TX:
- i4x0->regs[0x02] = 0x83; i4x0->regs[0x03] = 0x04; /*82424TX/ZX*/
- i4x0->regs[0x08] = 0x03; /*A3 stepping*/
- i4x0->regs[0x50] = 0x80;
- // i4x0->regs[0x50] = 0x23;
- i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
- break;
- case INTEL_430LX:
- i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/
- i4x0->regs[0x08] = 0x03; /*A3 stepping*/
- i4x0->regs[0x50] = 0x80;
- i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
- break;
- case INTEL_430NX:
- i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/
- i4x0->regs[0x08] = 0x10; /*A0 stepping*/
- i4x0->regs[0x50] = 0xA0;
- i4x0->regs[0x52] = 0x44; /*256kb PLB cache*/
- i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02;
- break;
- case INTEL_430FX:
- case INTEL_430FX_PB640:
- i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/
- if (i4x0->type == INTEL_430FX_PB640)
- i4x0->regs[0x08] = 0x02; /*???? stepping*/
- else
- i4x0->regs[0x08] = 0x00; /*A0 stepping*/
- i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
- break;
- case INTEL_430HX:
- i4x0->regs[0x02] = 0x50; i4x0->regs[0x03] = 0x12; /*82439HX*/
- i4x0->regs[0x08] = 0x00; /*A0 stepping*/
- i4x0->regs[0x51] = 0x20;
- i4x0->regs[0x52] = 0xB5; /*512kb cache*/
- i4x0->regs[0x56] = 0x52; /*DRAM control*/
- // i4x0->regs[0x59] = 0x40;
- // i4x0->regs[0x5A] = i4x0->regs[0x5B] = i4x0->regs[0x5C] = i4x0->regs[0x5D] = 0x44;
- // i4x0->regs[0x5E] = i4x0->regs[0x5F] = 0x44;
- i4x0->regs[0x65] = i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02;
- i4x0->regs[0x68] = 0x11;
- break;
- case INTEL_430VX:
- i4x0->regs[0x02] = 0x30; i4x0->regs[0x03] = 0x70; /*82437VX*/
- // i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/
- i4x0->regs[0x08] = 0x00; /*A0 stepping*/
- i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/
- i4x0->regs[0x53] = 0x14;
- i4x0->regs[0x56] = 0x52; /*DRAM control*/
- i4x0->regs[0x67] = 0x11;
- i4x0->regs[0x69] = 0x03;
- i4x0->regs[0x70] = 0x20;
- i4x0->regs[0x74] = 0x0e;
- i4x0->regs[0x78] = 0x23;
- break;
- case INTEL_430TX:
- io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, i4x0);
- i4x0->regs[0x02] = 0x00; i4x0->regs[0x03] = 0x71; /*82439TX*/
- i4x0->regs[0x08] = 0x01; /*A0 stepping*/
- i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/
- i4x0->regs[0x53] = 0x14;
- i4x0->regs[0x56] = 0x52; /*DRAM control*/
- i4x0->regs[0x65] = 0x02;
- i4x0->regs[0x67] = 0x80;
- i4x0->regs[0x69] = 0x03;
- i4x0->regs[0x70] = 0x20;
- break;
-#if defined(DEV_BRANCH) && defined(USE_I686)
- case INTEL_440FX:
- i4x0->regs[0x02] = 0x37; i4x0->regs[0x03] = 0x12; /*82441FX*/
- i4x0->regs[0x08] = 0x02; /*A0 stepping*/
- i4x0->regs[0x2c] = 0xf4;
- i4x0->regs[0x2d] = 0x1a;
- i4x0->regs[0x2f] = 0x11;
- i4x0->regs[0x51] = 0x01;
- i4x0->regs[0x53] = 0x80;
- i4x0->regs[0x58] = 0x10;
- i4x0->regs[0x5a] = i4x0->regs[0x5b] = i4x0->regs[0x5c] = i4x0->regs[0x5d] = 0x11;
- i4x0->regs[0x5e] = 0x11;
- i4x0->regs[0x5f] = 0x31;
- break;
-#endif
- }
- i4x0->regs[0x04] = 0x06; i4x0->regs[0x05] = 0x00;
-#if defined(DEV_BRANCH) && defined(USE_I686)
- if (i4x0->type == INTEL_440FX)
- i4x0->regs[0x06] = 0x80;
-#endif
- if (i4x0->type == INTEL_430FX)
- i4x0->regs[0x07] = 0x82;
-#if defined(DEV_BRANCH) && defined(USE_I686)
- else if (i4x0->type != INTEL_440FX)
-#else
- else
-#endif
- i4x0->regs[0x07] = 0x02;
- i4x0->regs[0x0b] = 0x06;
- if (i4x0->type >= INTEL_430FX)
- i4x0->regs[0x57] = 0x01;
- else
- i4x0->regs[0x57] = 0x31;
- i4x0->regs[0x60] = i4x0->regs[0x61] = i4x0->regs[0x62] = i4x0->regs[0x63] = 0x02;
- i4x0->regs[0x64] = 0x02;
- if (i4x0->type >= INTEL_430FX)
- i4x0->regs[0x72] = 0x02;
-
-#if defined(DEV_BRANCH) && defined(USE_I686)
- if (i4x0->type == INTEL_440FX) {
- cpu_cache_ext_enabled = 1;
- cpu_update_waitstates();
- }
-#endif
-
- pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, i4x0);
-
- i4x0_write(0, 0x59, 0x00, i4x0);
- i4x0_write(0, 0x5a, 0x00, i4x0);
- i4x0_write(0, 0x5b, 0x00, i4x0);
- i4x0_write(0, 0x5c, 0x00, i4x0);
- i4x0_write(0, 0x5d, 0x00, i4x0);
- i4x0_write(0, 0x5e, 0x00, i4x0);
- i4x0_write(0, 0x5f, 0x00, i4x0);
-
- smbase = 0xa0000;
-
- return i4x0;
-}
-
-
-const device_t i420tx_device =
-{
- "Intel 82424TX",
- DEVICE_PCI,
- INTEL_420TX,
- i4x0_init,
- i4x0_close,
- i4x0_reset,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-
-const device_t i430lx_device =
-{
- "Intel 82434LX",
- DEVICE_PCI,
- INTEL_430LX,
- i4x0_init,
- i4x0_close,
- i4x0_reset,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-
-const device_t i430nx_device =
-{
- "Intel 82434NX",
- DEVICE_PCI,
- INTEL_430NX,
- i4x0_init,
- i4x0_close,
- i4x0_reset,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-
-const device_t i430fx_device =
-{
- "Intel SB82437FX-66",
- DEVICE_PCI,
- INTEL_430FX,
- i4x0_init,
- i4x0_close,
- i4x0_reset,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-
-const device_t i430fx_pb640_device =
-{
- "Intel SB82437FX-66 (PB640)",
- DEVICE_PCI,
- INTEL_430FX_PB640,
- i4x0_init,
- i4x0_close,
- i4x0_reset,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-
-const device_t i430hx_device =
-{
- "Intel 82439HX",
- DEVICE_PCI,
- INTEL_430HX,
- i4x0_init,
- i4x0_close,
- i4x0_reset,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-
-const device_t i430vx_device =
-{
- "Intel 82437VX",
- DEVICE_PCI,
- INTEL_430VX,
- i4x0_init,
- i4x0_close,
- i4x0_reset,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-
-const device_t i430tx_device =
-{
- "Intel 82439TX",
- DEVICE_PCI,
- INTEL_430TX,
- i4x0_init,
- i4x0_close,
- i4x0_reset,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-
-#if defined(DEV_BRANCH) && defined(USE_I686)
-const device_t i440fx_device =
-{
- "Intel 82441FX",
- DEVICE_PCI,
- INTEL_440FX,
- i4x0_init,
- i4x0_close,
- i4x0_reset,
- NULL,
- NULL,
- NULL,
- NULL
-};
-#endif
diff --git a/src/chipset/sis_85c496.c b/src/chipset/sis_85c496.c
index 51888f23f..607178fb9 100644
--- a/src/chipset/sis_85c496.c
+++ b/src/chipset/sis_85c496.c
@@ -120,8 +120,6 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
if ((addr >= 4 && addr < 8) || addr >= 0x40)
dev->pci_conf[addr] = val;
- pclog("SiS 496 Write: %02X %02X %02X\n", func, addr, val);
-
valxor = old ^ val;
switch (addr) {
@@ -144,7 +142,6 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
port_92_remove(dev->port_92);
if (val & 0x02)
port_92_add(dev->port_92);
- pclog("Port 92: %sabled\n", (val & 0x02) ? "En" : "Dis");
}
break;
@@ -199,10 +196,8 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x67:
- if (valxor & 0x60) {
+ if (valxor & 0x60)
port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40));
- pclog("[Port 92] Set features: %sreset, %sA20\n", !!(val & 0x20) ? "" : "no ", !!(val & 0x40) ? "" : "no ");
- }
break;
case 0x82:
@@ -252,8 +247,6 @@ sis_85c496_read(int func, int addr, void *priv)
break;
}
- pclog("SiS 496 Read: %02X %02X %02X\n", func, addr, ret);
-
return ret;
}
diff --git a/src/config.c b/src/config.c
index 707bf0534..6daa573aa 100644
--- a/src/config.c
+++ b/src/config.c
@@ -806,6 +806,7 @@ load_other_peripherals(void)
ide_qua_enabled = !!config_get_int(cat, "ide_qua", 0);
bugger_enabled = !!config_get_int(cat, "bugger_enabled", 0);
+ postcard_enabled = !!config_get_int(cat, "postcard_enabled", 0);
for (c = 0; c < ISAMEM_MAX; c++) {
sprintf(temp, "isamem%d_type", c);
@@ -1686,6 +1687,11 @@ save_other_peripherals(void)
else
config_set_int(cat, "bugger_enabled", bugger_enabled);
+ if (postcard_enabled == 0)
+ config_delete_var(cat, "postcard_enabled");
+ else
+ config_set_int(cat, "postcard_enabled", postcard_enabled);
+
for (c = 0; c < ISAMEM_MAX; c++) {
sprintf(temp, "isamem%d_type", c);
if (isamem_type[c] == 0)
diff --git a/src/cpu_common/cpu_table.c b/src/cpu_common/cpu_table.c
index 52e01695b..c8e96ff6d 100644
--- a/src/cpu_common/cpu_table.c
+++ b/src/cpu_common/cpu_table.c
@@ -228,18 +228,18 @@ CPU cpus_486DLC[] = {
CPU cpus_i486S1[] = {
/*i486*/
- {"i486SX/16", CPU_i486SX, 16000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
- {"i486SX/20", CPU_i486SX, 20000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
- {"i486SX/25", CPU_i486SX, 25000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
- {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
- {"i486SX2/50", CPU_i486SX2, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
- {"i486SX2/66 (Q0569)", CPU_i486SX2, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
- {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
- {"i486DX/33", CPU_i486DX, 33333333, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
- {"i486DX/50", CPU_i486DX, 50000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
- {"i486DX2/40", CPU_i486DX2, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
- {"i486DX2/50", CPU_i486DX2, 50000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
- {"i486DX2/66", CPU_i486DX2, 66666666, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
+ {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
+ {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
+ {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
+ {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
+ {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
+ {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
+ {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
+ {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
+ {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
+ {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
+ {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
+ {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/
{"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0}
@@ -270,6 +270,28 @@ CPU cpus_Cx486S1[] = {
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
+CPU cpus_i486[] = {
+ /*i486/P24T*/
+ {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
+ {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
+ {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
+ {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
+ {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
+ {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
+ {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
+ {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
+ {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
+ {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
+ {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
+ {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
+ {"iDX4/75", CPU_iDX4, 75000000, 3, 0x480, 0x480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*CPUID available on DX4, >= 75 MHz*/
+ {"iDX4/100", CPU_iDX4, 100000000, 3, 0x483, 0x483, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
+ {"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9},
+ {"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
+ {"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 5/2, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
+ {"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 5/2, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
+ {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0}
+};
CPU cpus_i486[] = {
/*i486/P24T*/
{"i486SX/16", CPU_i486SX, 16000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
diff --git a/src/cpu_new/codegen_ops_misc.c b/src/cpu_new/codegen_ops_misc.c
index d4c243f96..eb73a4f81 100644
--- a/src/cpu_new/codegen_ops_misc.c
+++ b/src/cpu_new/codegen_ops_misc.c
@@ -359,11 +359,11 @@ uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
return -1;
case 0x28: /*JMP far*/
+ uop_MOVZX(ir, IREG_pc, src_reg);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2);
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
- uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc);
+ uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1);
uop_CALL_FUNC(ir, loadcsjmp);
- uop_MOVZX(ir, IREG_pc, src_reg);
return -1;
case 0x30: /*PUSH*/
@@ -466,11 +466,11 @@ uint32_t ropFF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
return -1;
case 0x28: /*JMP far*/
+ uop_MOV(ir, IREG_pc, src_reg);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 4);
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
- uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc);
+ uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1);
uop_CALL_FUNC(ir, loadcsjmp);
- uop_MOV(ir, IREG_pc, src_reg);
return -1;
case 0x30: /*PUSH*/
diff --git a/src/disk/hdc_ide.c b/src/disk/hdc_ide.c
index 5ec684bc7..78f612460 100644
--- a/src/disk/hdc_ide.c
+++ b/src/disk/hdc_ide.c
@@ -278,6 +278,8 @@ ide_irq_raise(ide_t *ide)
/* ide_log("Raising IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */
+ ide_log("IDE %i: IRQ raise\n", ide->board);
+
if (!(ide->fdisk & 2)) {
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq)
ide_bm[ide->board]->set_irq(ide->board | 0x40, ide_bm[ide->board]->priv);
@@ -298,6 +300,8 @@ ide_irq_lower(ide_t *ide)
/* ide_log("Lowering IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */
+ ide_log("IDE %i: IRQ lower\n", ide->board);
+
if (ide->irqstat) {
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq)
ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv);
@@ -318,6 +322,7 @@ ide_irq_update(ide_t *ide)
/* ide_log("Raising IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */
if (!(ide->fdisk & 2) && ide->irqstat) {
+ ide_log("IDE %i: IRQ update raise\n", ide->board);
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq) {
ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv);
ide_bm[ide->board]->set_irq(ide->board | 0x40, ide_bm[ide->board]->priv);
@@ -326,6 +331,7 @@ ide_irq_update(ide_t *ide)
picint(1 << ide_boards[ide->board]->irq);
}
} else if (ide->fdisk & 2) {
+ ide_log("IDE %i: IRQ update lower\n", ide->board);
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq)
ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv);
else if (ide_boards[ide->board]->irq != -1)
@@ -877,11 +883,17 @@ ide_atapi_callback(ide_t *ide)
switch(ide->sc->packet_status) {
case PHASE_IDLE:
+#ifdef ENABLE_IDE_LOG
+ ide_log("PHASE_IDLE\n");
+#endif
ide->sc->pos = 0;
ide->sc->phase = 1;
ide->sc->status = READY_STAT | DRQ_STAT | (ide->sc->status & ERR_STAT);
return;
case PHASE_COMMAND:
+#ifdef ENABLE_IDE_LOG
+ ide_log("PHASE_COMMAND\n");
+#endif
ide->sc->status = BUSY_STAT | (ide->sc->status & ERR_STAT);
if (ide->packet_command) {
ide->packet_command(ide->sc, ide->sc->atapi_cdb);
@@ -890,6 +902,9 @@ ide_atapi_callback(ide_t *ide)
}
return;
case PHASE_COMPLETE:
+#ifdef ENABLE_IDE_LOG
+ ide_log("PHASE_COMPLETE\n");
+#endif
ide->sc->status = READY_STAT;
ide->sc->phase = 3;
ide->sc->packet_status = PHASE_NONE;
@@ -897,12 +912,18 @@ ide_atapi_callback(ide_t *ide)
return;
case PHASE_DATA_IN:
case PHASE_DATA_OUT:
+#ifdef ENABLE_IDE_LOG
+ ide_log("PHASE_DATA_IN or PHASE_DATA_OUT\n");
+#endif
ide->sc->status = READY_STAT | DRQ_STAT | (ide->sc->status & ERR_STAT);
ide->sc->phase = !(ide->sc->packet_status & 0x01) << 1;
ide_irq_raise(ide);
return;
case PHASE_DATA_IN_DMA:
case PHASE_DATA_OUT_DMA:
+#ifdef ENABLE_IDE_LOG
+ ide_log("PHASE_DATA_IN_DMA or PHASE_DATA_OUT_DMA\n");
+#endif
out = (ide->sc->packet_status & 0x01);
if (ide_bm[ide->board] && ide_bm[ide->board]->dma) {
@@ -932,11 +953,17 @@ ide_atapi_callback(ide_t *ide)
return;
case PHASE_ERROR:
+#ifdef ENABLE_IDE_LOG
+ ide_log("PHASE_ERROR\n");
+#endif
ide->sc->status = READY_STAT | ERR_STAT;
ide->sc->phase = 3;
ide->sc->packet_status = PHASE_NONE;
ide_irq_raise(ide);
return;
+ default:
+ ide_log("PHASE_UNKNOWN %02X\n", ide->sc->packet_status);
+ return;
}
}
@@ -1001,6 +1028,9 @@ ide_atapi_packet_read(ide_t *ide, int length)
if (!dev || !dev->temp_buffer || (dev->packet_status != PHASE_DATA_IN))
return 0;
+ if (dev->packet_status == PHASE_DATA_IN)
+ ide_log("PHASE_DATA_IN read: %i, %i< %i, %i\n", dev->request_pos, dev->max_transfer_len, dev->pos, dev->packet_len);
+
bufferw = (uint16_t *) dev->temp_buffer;
bufferl = (uint32_t *) dev->temp_buffer;
@@ -1689,7 +1719,7 @@ ide_read_data(ide_t *ide, int length)
ide->secount = (ide->secount - 1) & 0xff;
if (ide->secount) {
ide_next_sector(ide);
- ide->atastat = BSY_STAT;
+ ide->atastat = BSY_STAT | READY_STAT | DSC_STAT;
if (ide->command == WIN_READ_MULTIPLE)
ide_callback(ide_boards[ide->board]);
else
diff --git a/src/disk/hdc_ide_sff8038i.c b/src/disk/hdc_ide_sff8038i.c
index 2c58042ae..5e2b19e8d 100644
--- a/src/disk/hdc_ide_sff8038i.c
+++ b/src/disk/hdc_ide_sff8038i.c
@@ -373,14 +373,16 @@ sff_bus_master_set_irq(int channel, void *priv)
channel &= 0x01;
if (dev->status & 0x04) {
- if ((dev->irq_mode == 2) && (channel & 1) && pci_use_mirq(0))
+ sff_log("SFF8038i: Channel %i IRQ raise\n", channel);
+ if ((dev->irq_mode == 2) && channel && pci_use_mirq(0))
pci_set_mirq(0, 0);
else if (dev->irq_mode == 1)
pci_set_irq(dev->slot, dev->irq_pin);
else
picint(1 << (14 + channel));
} else {
- if ((dev->irq_mode == 2) && (channel & 1) && pci_use_mirq(0))
+ sff_log("SFF8038i: Channel %i IRQ lower\n", channel);
+ if ((dev->irq_mode == 2) && channel && pci_use_mirq(0))
pci_clear_mirq(0, 0);
else if (dev->irq_mode == 1)
pci_clear_irq(dev->slot, dev->irq_pin);
@@ -419,6 +421,10 @@ sff_reset(void *p)
{
int i = 0;
+#ifdef ENABLE_SFF_LOG
+ sff_log("SFF8038i: Reset\n");
+#endif
+
for (i = 0; i < CDROM_NUM; i++) {
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) &&
(cdrom[i].ide_channel < 4) && cdrom[i].priv)
@@ -429,6 +435,9 @@ sff_reset(void *p)
(zip_drives[i].ide_channel < 4) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
}
+
+ sff_bus_master_set_irq(0x00, p);
+ sff_bus_master_set_irq(0x01, p);
}
diff --git a/src/disk/hdc_st506_at.c b/src/disk/hdc_st506_at.c
index a6da77d30..8f29d4fa4 100644
--- a/src/disk/hdc_st506_at.c
+++ b/src/disk/hdc_st506_at.c
@@ -463,7 +463,7 @@ mfm_readw(uint16_t port, void *priv)
mfm->secount = (mfm->secount - 1) & 0xff;
if (mfm->secount) {
next_sector(mfm);
- mfm->status = STAT_BUSY;
+ mfm->status = STAT_BUSY | STAT_READY | STAT_DSC;
timer_set_delay_u64(&mfm->callback_timer, SECTOR_TIME);
} else
ui_sb_update_icon(SB_HDD|HDD_BUS_MFM, 0);
diff --git a/src/disk/zip.c b/src/disk/zip.c
index e0fc5d783..429c68dab 100644
--- a/src/disk/zip.c
+++ b/src/disk/zip.c
@@ -815,8 +815,14 @@ zip_update_request_length(zip_t *dev, int len, int block_len)
/* For media access commands, make sure the requested DRQ length matches the block length. */
switch (dev->current_cdb[0]) {
case 0x08:
+ case 0x0a:
case 0x28:
+ case 0x2a:
case 0xa8:
+ case 0xaa:
+ /* Round it to the nearest 2048 bytes. */
+ dev->max_transfer_len = (dev->max_transfer_len >> 9) << 9;
+
/* Make sure total length is not bigger than sum of the lengths of
all the requested blocks. */
bt = (dev->requested_blocks * block_len);
diff --git a/src/floppy/fdc.c b/src/floppy/fdc.c
index 81274199c..d4eebc796 100644
--- a/src/floppy/fdc.c
+++ b/src/floppy/fdc.c
@@ -702,10 +702,6 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc->stat = 0x00;
fdc->pnum = fdc->ptot = 0;
}
- if (val&4) {
- fdc->stat = 0x80;
- fdc->pnum = fdc->ptot = 0;
- }
if ((val&4) && !(fdc->dor&4)) {
timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
fdc->interrupt = -1;
@@ -775,7 +771,16 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc->stat |= 0x10;
fdc_log("Starting FDC command %02X\n",fdc->command);
- switch (fdc->command & 0x1f) {
+ if (((fdc->command & 0x1f) == 0x02) || ((fdc->command & 0x1f) == 0x05) ||
+ ((fdc->command & 0x1f) == 0x06) || ((fdc->command & 0x1f) == 0x0a) ||
+ ((fdc->command & 0x1f) == 0x0c) || ((fdc->command & 0x1f) == 0x0d) ||
+ ((fdc->command & 0x1f) == 0x11) || ((fdc->command & 0x1f) == 0x16) ||
+ ((fdc->command & 0x1f) == 0x19) || ((fdc->command & 0x1f) == 0x1d))
+ fdc->processed_cmd = fdc->command & 0x1f;
+ else
+ fdc->processed_cmd = fdc->command;
+
+ switch (fdc->processed_cmd) {
case 0x01: /*Mode*/
if (fdc->flags & FDC_FLAG_NSC) {
fdc->pnum = 0;
@@ -921,7 +926,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
}
if (fdc->pnum == fdc->ptot) {
fdc_log("Got all params %02X\n", fdc->command);
- fdc->interrupt = fdc->command & 0x1F;
+ fdc->interrupt = fdc->processed_cmd;
fdc->reset_stat = 0;
/* Disable timer if enabled. */
timer_disable(&fdc->timer);
@@ -950,7 +955,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
break;
}
/* Process the firt phase of the command. */
- switch (fdc->interrupt & 0x1F) {
+ switch (fdc->processed_cmd) {
case 0x02: /* Read a track */
fdc_io_command_phase1(fdc, 0);
fdc->read_track_sector.id.c = fdc->params[1];
@@ -1072,7 +1077,8 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc->stat = (1 << fdc->drive);
if (!(fdc->flags & FDC_FLAG_PCJR))
fdc->stat |= 0x80;
- fdc->head = (fdc->params[0] & 4) ? 1 : 0;
+ /* fdc->head = (fdc->params[0] & 4) ? 1 : 0; */
+ fdc->head = 0; /* TODO: See if this is correct. */
fdc->st0 = fdc->params[0] & 0x03;
fdc->st0 |= (fdc->params[0] & 4);
fdc->st0 |= 0x80;
@@ -1210,21 +1216,22 @@ fdc_read(uint16_t addr, void *priv)
}
} else {
if (is486 || !fdc->enable_3f1)
- return 0xff;
+ ret = 0xff;
+ else {
+ ret = 0x70;
- ret = 0x70;
+ drive = real_drive(fdc, fdc->dor & 3);
- drive = real_drive(fdc, fdc->dor & 3);
+ if (drive)
+ ret &= ~0x40;
+ else
+ ret &= ~0x20;
- if (drive)
- ret &= ~0x40;
- else
- ret &= ~0x20;
-
- if (fdc->dor & 0x10)
- ret |= 1;
- if (fdc->dor & 0x20)
- ret |= 2;
+ if (fdc->dor & 0x10)
+ ret |= 1;
+ if (fdc->dor & 0x20)
+ ret |= 2;
+ }
}
break;
case 2:
diff --git a/src/floppy/fdc.h b/src/floppy/fdc.h
index 786d1bfe5..4fae14c62 100644
--- a/src/floppy/fdc.h
+++ b/src/floppy/fdc.h
@@ -36,7 +36,7 @@
typedef struct {
- uint8_t dor, stat, command, dat, st0, swap;
+ uint8_t dor, stat, command, processed_cmd, dat, st0, swap;
uint8_t swwp, disable_write;
uint8_t params[256], res[256];
uint8_t specify[256], format_dat[256];
diff --git a/src/floppy/fdd_86f.c b/src/floppy/fdd_86f.c
index d55f86734..8eb4d0f42 100644
--- a/src/floppy/fdd_86f.c
+++ b/src/floppy/fdd_86f.c
@@ -826,7 +826,7 @@ d86f_byteperiod(int drive)
int
d86f_is_mfm(int drive)
{
- return (d86f_track_flags(drive) & 8) ? 1 : 0;
+ return ((d86f_track_flags(drive) & 0x18) == 0x08) ? 1 : 0;
}
diff --git a/src/hwm.c b/src/hwm.c
new file mode 100644
index 000000000..b3142c7a4
--- /dev/null
+++ b/src/hwm.c
@@ -0,0 +1,36 @@
+/*
+ * 86Box A hypervisor and IBM PC system emulator that specializes in
+ * running old operating systems and software designed for IBM
+ * PC systems and compatibles from 1981 through fairly recent
+ * system designs based on the PCI bus.
+ *
+ * This file is part of the 86Box distribution.
+ *
+ * Common functions for hardware monitor chips.
+ *
+ * Version: @(#)hwm.c 1.0.0 2020/03/22
+ *
+ * Author: RichardG,
+ * Copyright 2020 RichardG.
+ */
+
+#include
+#include "device.h"
+#include "hwm.h"
+
+
+hwm_values_t hwm_values;
+
+
+void
+hwm_set_values(hwm_values_t new_values)
+{
+ hwm_values = new_values;
+}
+
+
+hwm_values_t*
+hwm_get_values()
+{
+ return &hwm_values;
+}
diff --git a/src/hwm.h b/src/hwm.h
new file mode 100644
index 000000000..c5d482fb7
--- /dev/null
+++ b/src/hwm.h
@@ -0,0 +1,38 @@
+/*
+ * 86Box A hypervisor and IBM PC system emulator that specializes in
+ * running old operating systems and software designed for IBM
+ * PC systems and compatibles from 1981 through fairly recent
+ * system designs based on the PCI bus.
+ *
+ * This file is part of the 86Box distribution.
+ *
+ * Definitions for the hardware monitor chips.
+ *
+ * Version: @(#)hwm.h 1.0.0 2020/03/21
+ *
+ * Author: RichardG,
+ * Copyright 2020 RichardG.
+ */
+#ifndef EMU_HWM_H
+# define EMU_HWM_H
+
+
+#define VDIV(v, r1, r2) (((v) * (r2)) / ((r1) + (r2)))
+
+
+typedef struct _hwm_values_ {
+ uint16_t fans[4];
+ uint8_t temperatures[4];
+ uint8_t voltages[8];
+} hwm_values_t;
+
+
+extern void hwm_set_values(hwm_values_t new_values);
+extern hwm_values_t* hwm_get_values();
+
+
+extern const device_t w83781d_device;
+extern const device_t as99127f_device;
+
+
+#endif /*EMU_HWM_H*/
diff --git a/src/hwm_w83781d.c b/src/hwm_w83781d.c
new file mode 100644
index 000000000..1f6b3ab26
--- /dev/null
+++ b/src/hwm_w83781d.c
@@ -0,0 +1,482 @@
+/*
+ * 86Box A hypervisor and IBM PC system emulator that specializes in
+ * running old operating systems and software designed for IBM
+ * PC systems and compatibles from 1981 through fairly recent
+ * system designs based on the PCI bus.
+ *
+ * This file is part of the 86Box distribution.
+ *
+ * Emulation of the Winbond W83781D hardware monitoring chip.
+ *
+ * Version: @(#)hwm_w83781d.c 1.0.0 2020/03/21
+ *
+ * Author: RichardG,
+ * Copyright 2020 RichardG.
+ */
+#include
+#include
+#include
+#include
+#include
+#include "86box.h"
+#include "device.h"
+#include "86box_io.h"
+#include "smbus.h"
+#include "hwm.h"
+
+
+#define W83781D_SMBUS 0x10000
+#define W83781D_AS99127F 0x20000
+#define W83781D_VENDOR_ID ((dev->local & W83781D_AS99127F) ? 0x12C3 : 0x5CA3)
+
+#define CLAMP(a, min, max) (((a) < (min)) ? (min) : (((a) > (max)) ? (max) : (a)))
+#define W83781D_RPM_TO_REG(r, d) CLAMP(1350000 / (r * d), 1, 255)
+#define W83781D_TEMP_TO_REG(t) ((t) * 8) << 5
+
+
+typedef struct {
+ uint32_t local;
+ hwm_values_t* values;
+
+ uint8_t regs[64];
+ uint8_t regs_bank1[6];
+ uint8_t regs_bank2[6];
+ uint8_t addr_register;
+ uint8_t data_register;
+
+ uint8_t smbus_addr_main;
+ uint8_t smbus_addr_temp2;
+ uint8_t smbus_addr_temp3;
+ uint8_t hbacs;
+ uint8_t active_bank;
+} w83781d_t;
+
+
+static uint8_t w83781d_isa_read(uint16_t port, void *priv);
+static uint8_t w83781d_smbus_read_byte(uint8_t addr, void *priv);
+static uint8_t w83781d_smbus_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv);
+static uint16_t w83781d_smbus_read_word_cmd(uint8_t addr, uint8_t cmd, void *priv);
+static uint8_t w83781d_read(w83781d_t *dev, uint8_t reg, uint8_t bank);
+static void w83781d_isa_write(uint16_t port, uint8_t val, void *priv);
+static void w83781d_smbus_write_byte(uint8_t addr, uint8_t val, void *priv);
+static void w83781d_smbus_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val, void *priv);
+static void w83781d_smbus_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val, void *priv);
+static uint8_t w83781d_write(w83781d_t *dev, uint8_t reg, uint8_t val, uint8_t bank);
+static void w83781d_reset(w83781d_t *dev, uint8_t initialization);
+
+
+static void
+w83781d_remap(w83781d_t *dev)
+{
+ if (!(dev->local & W83781D_SMBUS)) return;
+
+ smbus_removehandler(0x00, 0x80,
+ w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
+ w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
+ dev);
+
+ if (dev->smbus_addr_main) smbus_sethandler(dev->smbus_addr_main, 1,
+ w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
+ w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
+ dev);
+
+ if (dev->smbus_addr_temp2) smbus_sethandler(dev->smbus_addr_temp2, 1,
+ w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
+ w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
+ dev);
+
+ if (dev->smbus_addr_temp3) smbus_sethandler(dev->smbus_addr_temp3, 1,
+ w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
+ w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
+ dev);
+}
+
+
+static uint8_t
+w83781d_isa_read(uint16_t port, void *priv)
+{
+ w83781d_t *dev = (w83781d_t *) priv;
+ uint8_t ret = 0xFF;
+
+ switch (port - (dev->local & 0xFFFF)) {
+ case 0x0:
+ ret = dev->addr_register & 0x7F;
+ break;
+ case 0x1:
+ ret = w83781d_read(dev, dev->addr_register, dev->active_bank);
+
+ if (dev->active_bank == 0 &&
+ (dev->addr_register == 0x41 || dev->addr_register == 0x43 || dev->addr_register == 0x45 || dev->addr_register == 0x56 ||
+ (dev->addr_register >= 0x60 && dev->addr_register < 0x7F))) {
+ /* auto-increment registers */
+ dev->addr_register++;
+ }
+ break;
+ }
+
+ return ret;
+}
+
+
+static uint8_t
+w83781d_smbus_read_byte(uint8_t addr, void *priv)
+{
+ w83781d_t *dev = (w83781d_t *) priv;
+
+ return w83781d_read(dev, dev->addr_register, 0);
+}
+
+
+static uint8_t
+w83781d_smbus_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv)
+{
+ w83781d_t *dev = (w83781d_t *) priv;
+
+ return w83781d_read(dev, cmd, 0);
+}
+
+
+static uint16_t
+w83781d_smbus_read_word_cmd(uint8_t addr, uint8_t cmd, void *priv)
+{
+ w83781d_t *dev = (w83781d_t *) priv;
+ uint8_t rethi = 0;
+ uint8_t retlo = 0;
+ uint8_t bank = 0;
+
+ if (addr == dev->smbus_addr_temp2 || addr == dev->smbus_addr_temp3) {
+ if (addr == dev->smbus_addr_temp2)
+ bank = 2;
+ else
+ bank = 3;
+
+ switch (cmd & 0x3) {
+ case 0x0:
+ rethi = w83781d_read(dev, 0x50, bank);
+ retlo = w83781d_read(dev, 0x51, bank);
+ break;
+ case 0x1:
+ rethi = retlo = w83781d_read(dev, 0x52, bank);
+ break;
+ case 0x2:
+ rethi = w83781d_read(dev, 0x53, bank);
+ retlo = w83781d_read(dev, 0x54, bank);
+ break;
+ case 0x3:
+ rethi = w83781d_read(dev, 0x55, bank);
+ retlo = w83781d_read(dev, 0x56, bank);
+ break;
+ }
+
+ return (retlo << 8) | rethi; /* byte-swapped for some reason */
+ }
+
+ return w83781d_read(dev, cmd, bank);
+}
+
+
+static uint8_t
+w83781d_read(w83781d_t *dev, uint8_t reg, uint8_t bank)
+{
+ uint8_t ret = 0;
+
+ if ((reg >> 4) == 0x5 && bank != 0) {
+ /* bank-switched temperature registers */
+ if (bank == 1)
+ ret = dev->regs_bank1[reg - 0x50];
+ else
+ ret = dev->regs_bank2[reg - 0x50];
+ } else {
+ /* regular registers */
+ if (reg == 0x4F) /* special case for two-byte vendor ID register */
+ ret = dev->hbacs ? (W83781D_VENDOR_ID >> 8) : (W83781D_VENDOR_ID & 0xFF);
+ else if (reg >= 0x60) /* read auto-increment value RAM registers from their non-auto-increment locations */
+ ret = dev->regs[reg - 0x40];
+ else
+ ret = dev->regs[reg - 0x20];
+ }
+
+ return ret;
+}
+
+
+static void
+w83781d_isa_write(uint16_t port, uint8_t val, void *priv)
+{
+ w83781d_t *dev = (w83781d_t *) priv;
+
+ switch (port - (dev->local & 0xFFFF)) {
+ case 0x0:
+ dev->addr_register = val & 0x7F;
+ break;
+ case 0x1:
+ w83781d_write(dev, dev->addr_register, val, dev->active_bank);
+
+ if (dev->active_bank == 0 &&
+ (dev->addr_register == 0x41 || dev->addr_register == 0x43 || dev->addr_register == 0x45 || dev->addr_register == 0x56 ||
+ (dev->addr_register >= 0x60 && dev->addr_register < 0x7F))) {
+ /* auto-increment registers */
+ dev->addr_register++;
+ }
+ break;
+ }
+}
+
+
+static void
+w83781d_smbus_write_byte(uint8_t addr, uint8_t val, void *priv)
+{
+ w83781d_t *dev = (w83781d_t *) priv;
+
+ dev->addr_register = val;
+}
+
+
+static void
+w83781d_smbus_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val, void *priv)
+{
+ w83781d_t *dev = (w83781d_t *) priv;
+
+ w83781d_write(dev, cmd, val, 0);
+}
+
+
+static void
+w83781d_smbus_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val, void *priv)
+{
+ w83781d_t *dev = (w83781d_t *) priv;
+ uint8_t valhi = (val >> 8);
+ uint8_t vallo = (val & 0xFF);
+ uint8_t bank = 0;
+
+ if (addr == dev->smbus_addr_temp2 || addr == dev->smbus_addr_temp3) {
+ if (addr == dev->smbus_addr_temp2)
+ bank = 2;
+ else
+ bank = 3;
+
+ switch (cmd & 0x3) {
+ case 0x0:
+ w83781d_write(dev, 0x50, valhi, bank);
+ w83781d_write(dev, 0x51, vallo, bank);
+ break;
+ case 0x1:
+ w83781d_write(dev, 0x52, vallo, bank);
+ break;
+ case 0x2:
+ w83781d_write(dev, 0x53, valhi, bank);
+ w83781d_write(dev, 0x54, vallo, bank);
+ break;
+ case 0x3:
+ w83781d_write(dev, 0x55, valhi, bank);
+ w83781d_write(dev, 0x56, vallo, bank);
+ break;
+ break;
+ }
+ return;
+ }
+
+ w83781d_write(dev, cmd, vallo, bank);
+}
+
+
+static uint8_t
+w83781d_write(w83781d_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
+{
+ uint8_t remap = 0;
+
+ if ((reg >> 4) == 0x5 && bank != 0) {
+ /* bank-switched temperature registers */
+ switch (reg) {
+ case 0x50: case 0x51:
+ /* read-only registers */
+ return 0;
+ }
+
+ if (bank == 1)
+ dev->regs_bank1[reg - 0x50] = val;
+ else
+ dev->regs_bank2[reg - 0x50] = val;
+
+ return 1;
+ }
+
+ /* regular registers */
+ switch (reg) {
+ case 0x41: case 0x42: case 0x4F: case 0x58:
+ case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: case 0x28: case 0x29: case 0x2A:
+ case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67: case 0x68: case 0x69: case 0x6A:
+ /* read-only registers */
+ return 0;
+ }
+
+ if (reg >= 0x60) /* write auto-increment value RAM registers to their non-auto-increment locations */
+ dev->regs[reg - 0x40] = val;
+ else
+ dev->regs[reg - 0x20] = val;
+
+ switch (reg) {
+ case 0x40:
+ if (val >> 7) {
+ /* INITIALIZATION bit set: reset all registers except main SMBus address */
+ w83781d_reset(dev, 1);
+ }
+ break;
+ case 0x47:
+ /* update FAN1/FAN2 values to match the new divisor */
+ dev->regs[0x08] = W83781D_RPM_TO_REG(dev->values->fans[0], 1 << ((dev->regs[0x27] >> 4) & 0x3));
+ dev->regs[0x09] = W83781D_RPM_TO_REG(dev->values->fans[1], 1 << ((dev->regs[0x27] >> 6) & 0x3));
+ break;
+ case 0x48:
+ if (dev->local & W83781D_SMBUS) {
+ dev->smbus_addr_main = (dev->regs[0x28] & 0x7F);
+ remap = 1;
+ }
+ break;
+ case 0x4A:
+ if (dev->local & W83781D_SMBUS) {
+ /* DIS_T2 and DIS_T3 bits can disable those interfaces */
+ if ((dev->regs[0x2A] >> 3) & 0x1)
+ dev->smbus_addr_temp2 = 0x00;
+ else
+ dev->smbus_addr_temp2 = 0x48 + (dev->regs[0x2A] & 0x7);
+ if (dev->regs[0x2A] >> 7)
+ dev->smbus_addr_temp3 = 0x00;
+ else
+ dev->smbus_addr_temp3 = 0x48 + ((dev->regs[0x2A] >> 4) & 0x7);
+ remap = 1;
+ }
+ break;
+ case 0x4B:
+ /* update FAN3 value to match the new divisor */
+ dev->regs[0x0A] = W83781D_RPM_TO_REG(dev->values->fans[2], 1 << ((dev->regs[0x2B] >> 6) & 0x3));
+ break;
+ case 0x4E:
+ dev->hbacs = (dev->regs[0x2E] & 0x80);
+ /* FIXME: Winbond's datasheet does not specify how BANKSEL[0:2] work */
+ if (dev->regs[0x2E] & 0x1)
+ dev->active_bank = 0;
+ else if (dev->regs[0x2E] & 0x2)
+ dev->active_bank = 1;
+ else if (dev->regs[0x2E] & 0x4)
+ dev->active_bank = 2;
+ break;
+ }
+
+ if (remap)
+ w83781d_remap(dev);
+
+ return 1;
+}
+
+
+static void
+w83781d_reset(w83781d_t *dev, uint8_t initialization)
+{
+ memset(dev->regs, 0, 64);
+ memset(dev->regs_bank1, 0, 6);
+ memset(dev->regs_bank2, 0, 6);
+
+ /* WARNING: Array elements are register - 0x20. */
+ uint8_t i;
+ for (i = 0; i <= 6; i++)
+ dev->regs[i] = dev->values->voltages[i];
+ dev->regs[0x07] = dev->values->temperatures[0];
+ for (i = 0; i <= 2; i++)
+ dev->regs[0x08 + i] = W83781D_RPM_TO_REG(dev->values->fans[i], 2);
+ dev->regs[0x20] = 0x01;
+ dev->regs[0x26] = 0x40;
+ dev->regs[0x27] = 0x50;
+ if (dev->local & W83781D_SMBUS) {
+ if (!initialization) /* don't reset main SMBus address if the reset was triggered by the INITIALIZATION bit */
+ dev->smbus_addr_main = 0x2D;
+ dev->regs[0x28] = dev->smbus_addr_main;
+ dev->regs[0x2A] = 0x01;
+ dev->smbus_addr_temp2 = 0x48 + (dev->regs[0x2A] & 0x7);
+ dev->smbus_addr_temp3 = 0x48 + ((dev->regs[0x2A] >> 4) & 0x7);
+ } else {
+ dev->regs[0x28] = 0x00;
+ dev->regs[0x2A] = 0x88;
+ dev->smbus_addr_temp2 = dev->smbus_addr_temp3 = 0x00;
+ }
+ dev->regs[0x29] = 0x02;
+ dev->regs[0x2B] = 0x44;
+ dev->regs[0x2C] = 0x01;
+ dev->regs[0x2D] = 0x15;
+ dev->regs[0x2E] = 0x80;
+ dev->hbacs = (dev->regs[0x2E] & 0x80);
+ dev->regs[0x2F] = W83781D_VENDOR_ID >> 8;
+ dev->regs[0x37] = 0x80;
+ dev->regs[0x38] = (dev->local & W83781D_AS99127F) ? 0x31 : 0x10;
+
+ /* WARNING: Array elements are register - 0x50. */
+ uint16_t temp;
+ temp = W83781D_TEMP_TO_REG(dev->values->temperatures[1]);
+ dev->regs_bank1[0x0] = temp >> 8;
+ dev->regs_bank1[0x1] = temp & 0xFF;
+ dev->regs_bank1[0x3] = 0x4B;
+ dev->regs_bank1[0x5] = 0x50;
+ temp = W83781D_TEMP_TO_REG(dev->values->temperatures[2]);
+ dev->regs_bank2[0x0] = temp >> 8;
+ dev->regs_bank2[0x1] = temp & 0xFF;
+ dev->regs_bank2[0x3] = 0x4B;
+ dev->regs_bank2[0x5] = 0x50;
+
+ w83781d_remap(dev);
+}
+
+
+static void
+w83781d_close(void *priv)
+{
+ w83781d_t *dev = (w83781d_t *) priv;
+
+ uint16_t isa_io = dev->local & 0xFFFF;
+ if (isa_io)
+ io_removehandler(isa_io, 2, w83781d_isa_read, NULL, NULL, w83781d_isa_write, NULL, NULL, dev);
+
+ free(dev);
+}
+
+
+static void *
+w83781d_init(const device_t *info)
+{
+ w83781d_t *dev = (w83781d_t *) malloc(sizeof(w83781d_t));
+ memset(dev, 0, sizeof(w83781d_t));
+
+ dev->local = info->local;
+ dev->values = hwm_get_values();
+ w83781d_reset(dev, 0);
+
+ uint16_t isa_io = dev->local & 0xFFFF;
+ if (isa_io)
+ io_sethandler(isa_io, 2, w83781d_isa_read, NULL, NULL, w83781d_isa_write, NULL, NULL, dev);
+
+ return dev;
+}
+
+
+const device_t w83781d_device = {
+ "Winbond W83781D Hardware Monitor",
+ DEVICE_ISA,
+ 0x295 | W83781D_SMBUS,
+ w83781d_init, w83781d_close, NULL,
+ NULL, NULL, NULL,
+ NULL
+};
+
+
+/*
+ * ASUS rebadged version of the W83781D.
+ * Some claim it's SMBus-only, yet the BIOS clearly reads most values over ISA,
+ * except TEMP3 (CPU Temperature) which is read over SMBus.
+ */
+const device_t as99127f_device = {
+ "ASUS AS99127F Hardware Monitor",
+ DEVICE_ISA,
+ 0x295 | W83781D_SMBUS | W83781D_AS99127F,
+ w83781d_init, w83781d_close, NULL,
+ NULL, NULL, NULL,
+ NULL
+};
diff --git a/src/intel_flash - Cópia.c b/src/intel_flash - Cópia.c
deleted file mode 100644
index cb08eb44b..000000000
--- a/src/intel_flash - Cópia.c
+++ /dev/null
@@ -1,561 +0,0 @@
-/*
- * 86Box A hypervisor and IBM PC system emulator that specializes in
- * running old operating systems and software designed for IBM
- * PC systems and compatibles from 1981 through fairly recent
- * system designs based on the PCI bus.
- *
- * This file is part of the 86Box distribution.
- *
- * Implementation of the Intel 1 Mbit and 2 Mbit, 8-bit and
- * 16-bit flash devices.
- *
- * Version: @(#)intel_flash.c 1.0.19 2019/06/25
- *
- * Authors: Sarah Walker,
- * Miran Grca,
- *
- * Copyright 2008-2019 Sarah Walker.
- * Copyright 2016-2019 Miran Grca.
- */
-#include
-#include
-#include
-#include
-#include
-#include "86box.h"
-#include "device.h"
-#include "mem.h"
-#include "machine.h"
-#include "timer.h"
-#include "nvr.h"
-#include "plat.h"
-
-
-#define FLAG_BYTEMODE 4
-#define FLAG_WORD 4
-#define FLAG_BXB 2
-#define FLAG_INV_A16 1
-
-
-enum
-{
- BLOCK_MAIN1,
- BLOCK_MAIN2,
- BLOCK_DATA1,
- BLOCK_DATA2,
- BLOCK_BOOT,
- BLOCKS_NUM
-};
-
-enum
-{
- CMD_READ_ARRAY = 0xff,
- CMD_IID = 0x90,
- CMD_READ_STATUS = 0x70,
- CMD_CLEAR_STATUS = 0x50,
- CMD_ERASE_SETUP = 0x20,
- CMD_ERASE_CONFIRM = 0xd0,
- CMD_ERASE_SUSPEND = 0xb0,
- CMD_PROGRAM_SETUP = 0x40,
- CMD_PROGRAM_SETUP_ALT = 0x10
-};
-
-
-typedef struct flash_t
-{
- uint8_t command, status,
- pad, flags,
- *array;
-
- uint16_t flash_id, pad16;
-
- uint32_t program_addr,
- block_start[BLOCKS_NUM], block_end[BLOCKS_NUM],
- block_len[BLOCKS_NUM];
-
- mem_mapping_t mapping[4], mapping_h[8];
-} flash_t;
-
-
-static wchar_t flash_path[1024];
-
-
-static uint16_t flash_readw(uint32_t addr, void *p);
-
-
-static uint8_t
-flash_read(uint32_t addr, void *p)
-{
- flash_t *dev = (flash_t *) p;
- uint8_t ret = 0xff;
-
- if (dev->flags & FLAG_WORD)
- return flash_readw(addr, p) & 0xff;
-
- if (dev->flags & FLAG_INV_A16)
- addr ^= 0x10000;
- addr &= biosmask;
-
- switch (dev->command) {
- case CMD_READ_ARRAY:
- default:
- ret = dev->array[addr];
- break;
-
- case CMD_IID:
- /* Yes, & 2 is correct for the 100BX/200BX in BYTE mode. */
- if (addr & 1)
- ret = dev->flash_id & 0xff;
- else
- ret = 0x89;
- // pclog("id b %i: %02X\n", addr & 1, ret);
- break;
-
- case CMD_READ_STATUS:
- ret = dev->status;
- break;
- }
-
-#if 0
- if ((dev->command & 0x0f) && (dev->command != 0xff))
- ret = dev->status;
-#endif
-
- return ret;
-}
-
-
-static uint16_t
-flash_readw(uint32_t addr, void *p)
-{
- flash_t *dev = (flash_t *) p;
- uint16_t *q;
- uint16_t ret = 0xffff;
-
- if (!(dev->flags & FLAG_WORD))
- return flash_read(addr, p) | (flash_read(addr + 1, p) << 8);
-
- if (dev->flags & FLAG_INV_A16)
- addr ^= 0x10000;
- addr &= biosmask;
-
- if (dev->flags & FLAG_WORD)
- addr &= 0xfffffffe;
-
- q = (uint16_t *)&(dev->array[addr]);
- ret = *q;
-
- switch (dev->command) {
- case CMD_READ_ARRAY:
- default:
- break;
-
- case CMD_IID:
- // pclog("id w %i: %02X\n", addr & 2, ret);
- if (addr & 2)
- ret = dev->flash_id;
- else
- ret = 0x0089;
- break;
-
- case CMD_READ_STATUS:
- ret = dev->status;
- break;
- }
-
- return ret;
-}
-
-
-static uint32_t
-flash_readl(uint32_t addr, void *p)
-{
- flash_t *dev = (flash_t *)p;
- uint32_t *q;
-
- if (dev->flags & FLAG_INV_A16)
- addr ^= 0x10000;
- addr &= biosmask;
-
- q = (uint32_t *)&(dev->array[addr]);
-
- return *q;
- // return flash_readw(addr, p) | (flash_readw(addr + 2, p) << 16);
-}
-
-
-static void flash_writew(uint32_t addr, uint16_t val, void *p);
-
-
-static void
-flash_write(uint32_t addr, uint8_t val, void *p)
-{
- flash_t *dev = (flash_t *) p;
- int i;
- uint32_t bb_mask = biosmask & 0xffffe000;
- uint32_t o = addr;
- if (biosmask == 0x3ffff)
- bb_mask &= 0xffffc000;
-
- if (dev->flags & FLAG_WORD) {
- flash_writew(addr, val, p);
- return;
- }
-
- if (dev->flags & FLAG_INV_A16)
- addr ^= 0x10000;
- addr &= biosmask;
-
- if ((addr >= 0x2e400) && (addr <= 0x2e43f)) {
- dev->array[addr] = val;
- return;
- }
-
- switch (dev->command) {
- case CMD_ERASE_SETUP:
- if (val == CMD_ERASE_CONFIRM) {
- for (i = 0; i < 3; i++) {
- if ((addr >= dev->block_start[i]) && (addr <= dev->block_end[i]))
- memset(&(dev->array[dev->block_start[i]]), 0xff, dev->block_len[i]);
- }
-
- dev->status = 0x80;
- }
- dev->command = CMD_READ_STATUS;
- break;
-
- case CMD_PROGRAM_SETUP:
- case CMD_PROGRAM_SETUP_ALT:
- if (((addr & bb_mask) != (dev->block_start[4] & bb_mask)) && (addr == dev->program_addr))
- dev->array[addr] = val;
- dev->command = CMD_READ_STATUS;
- dev->status = 0x80;
- break;
-
- default:
- dev->command = val;
- // pclog("[%04X:%08X] (%08X, %02X) [%08X] command b = %02X\n", CS, cpu_state.pc, cpu_state.seg_cs.base, opcode, o, dev->command);
-#if 0
- if (val == 0x93) {
- FILE *f = fopen("d:\\queen\\86boxnew\\mem.dmp", "wb");
- for (i = 0; i < 1114096; i++)
- fputc(mem_readb_phys(i), f);
- fclose(f);
- f = fopen("d:\\queen\\86boxnew\\highbios.dmp", "wb");
- for (i = 0; i < 524288; i++)
- fputc(mem_readb_phys(i + 0xfff80000), f);
- fclose(f);
- fatal("Fo' shizzle da nizzle\n");
- }
-#endif
- switch (val) {
- case CMD_CLEAR_STATUS:
- dev->status = 0;
- break;
- case CMD_PROGRAM_SETUP:
- case CMD_PROGRAM_SETUP_ALT:
- dev->program_addr = addr;
- break;
- }
- }
-}
-
-
-static void
-flash_writew(uint32_t addr, uint16_t val, void *p)
-{
- flash_t *dev = (flash_t *) p;
- int i;
- uint32_t bb_mask = biosmask & 0xffffe000;
- if (biosmask == 0x3ffff)
- bb_mask &= 0xffffc000;
-
- if (!(dev->flags & FLAG_WORD)) {
- // flash_write(addr, val & 0xff, p);
- // flash_write(addr + 1, (val >> 8) & 0xff, p);
- return;
- }
-
- if (dev->flags & FLAG_INV_A16)
- addr ^= 0x10000;
- addr &= biosmask;
-
- if (dev->flags & FLAG_WORD) switch (dev->command) {
- case CMD_ERASE_SETUP:
- if (val == CMD_ERASE_CONFIRM) {
- for (i = 0; i < 3; i++) {
- if ((addr >= dev->block_start[i]) && (addr <= dev->block_end[i]))
- memset(&(dev->array[dev->block_start[i]]), 0xff, dev->block_len[i]);
- }
-
- dev->status = 0x80;
- }
- dev->command = CMD_READ_STATUS;
- break;
-
- case CMD_PROGRAM_SETUP:
- case CMD_PROGRAM_SETUP_ALT:
- if (((addr & bb_mask) != (dev->block_start[4] & bb_mask)) && (addr == dev->program_addr))
- *(uint16_t *) (&dev->array[addr]) = val;
- dev->command = CMD_READ_STATUS;
- dev->status = 0x80;
- break;
-
- default:
- dev->command = val & 0xff;
- // pclog("command w = %02X\n", dev->command);
- switch (val) {
- case CMD_CLEAR_STATUS:
- dev->status = 0;
- break;
- case CMD_PROGRAM_SETUP:
- case CMD_PROGRAM_SETUP_ALT:
- dev->program_addr = addr;
- break;
- }
- }
-}
-
-
-static void
-flash_writel(uint32_t addr, uint32_t val, void *p)
-{
- flash_writew(addr, val & 0xffff, p);
- flash_writew(addr + 2, (val >> 16) & 0xffff, p);
-}
-
-
-static void
-intel_flash_add_mappings(flash_t *dev)
-{
- int max = 2, i = 0;
- uint32_t base, fbase;
- uint32_t sub = 0x20000;
-
- if (biosmask == 0x3ffff) {
- sub = 0x40000;
- max = 4;
- }
-
- for (i = 0; i < max; i++) {
- if (biosmask == 0x3ffff)
- base = 0xc0000 + (i << 16);
- else
- base = 0xe0000 + (i << 16);
- fbase = base & biosmask;
- if (dev->flags & FLAG_INV_A16)
- fbase ^= 0x10000;
-
- memcpy(&dev->array[fbase], &rom[base & biosmask], 0x10000);
-
- if ((max == 2) || (i >= 2)) {
- mem_mapping_add(&(dev->mapping[i]), base, 0x10000,
- flash_read, flash_readw, flash_readl,
- flash_write, flash_writew, flash_writel,
- dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROMCS, (void *) dev);
- }
- mem_mapping_add(&(dev->mapping_h[i]), (base | 0xfff00000) - sub, 0x10000,
- flash_read, flash_readw, flash_readl,
- flash_write, flash_writew, flash_writel,
- dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROMCS, (void *) dev);
- mem_mapping_add(&(dev->mapping_h[i + 4]), (base | 0xfff00000), 0x10000,
- flash_read, flash_readw, flash_readl,
- flash_write, flash_writew, flash_writel,
- dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROMCS, (void *) dev);
- }
-}
-
-
-static void *
-intel_flash_init(const device_t *info)
-{
- FILE *f;
- int l;
- flash_t *dev;
- wchar_t *machine_name, *flash_name;
- uint8_t type = info->local & 0xff;
-
- dev = malloc(sizeof(flash_t));
- memset(dev, 0, sizeof(flash_t));
-
- l = strlen(machine_get_internal_name_ex(machine))+1;
- machine_name = (wchar_t *) malloc(l * sizeof(wchar_t));
- mbstowcs(machine_name, machine_get_internal_name_ex(machine), l);
- l = wcslen(machine_name)+5;
- flash_name = (wchar_t *)malloc(l*sizeof(wchar_t));
- swprintf(flash_name, l, L"%ls.bin", machine_name);
-
- if (wcslen(flash_name) <= 1024)
- wcscpy(flash_path, flash_name);
- else
- wcsncpy(flash_path, flash_name, 1024);
-
- dev->flags = info->local & 0xff;
-
- mem_mapping_disable(&bios_mapping);
- mem_mapping_disable(&bios_high_mapping);
-
- dev->array = (uint8_t *) malloc(biosmask + 1);
- memset(dev->array, 0xff, biosmask + 1);
-
- if (biosmask == 0x3ffff) {
- if (dev->flags & FLAG_WORD)
- dev->flash_id = (dev->flags & FLAG_BXB) ? 0x2275 : 0x2274;
- else
- dev->flash_id = (dev->flags & FLAG_BXB) ? 0x7D : 0x7C;
-
- /* The block lengths are the same both flash types. */
- dev->block_len[BLOCK_MAIN1] = 0x20000;
- dev->block_len[BLOCK_MAIN2] = 0x18000;
- dev->block_len[BLOCK_DATA1] = 0x02000;
- dev->block_len[BLOCK_DATA2] = 0x02000;
- dev->block_len[BLOCK_BOOT] = 0x04000;
-
- if (dev->flags & FLAG_BXB) { /* 28F002BX-B/28F200BX-B */
- dev->block_start[BLOCK_MAIN1] = 0x20000; /* MAIN BLOCK 1 */
- dev->block_end[BLOCK_MAIN1] = 0x3ffff;
- dev->block_start[BLOCK_MAIN2] = 0x08000; /* MAIN BLOCK 2 */
- dev->block_end[BLOCK_MAIN2] = 0x1ffff;
- dev->block_start[BLOCK_DATA1] = 0x06000; /* DATA AREA 1 BLOCK */
- dev->block_end[BLOCK_DATA1] = 0x07fff;
- dev->block_start[BLOCK_DATA2] = 0x04000; /* DATA AREA 2 BLOCK */
- dev->block_end[BLOCK_DATA2] = 0x05fff;
- dev->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */
- dev->block_end[BLOCK_BOOT] = 0x03fff;
- } else { /* 28F002BX-T/28F200BX-T */
- dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */
- dev->block_end[BLOCK_MAIN1] = 0x1ffff;
- dev->block_start[BLOCK_MAIN2] = 0x20000; /* MAIN BLOCK 2 */
- dev->block_end[BLOCK_MAIN2] = 0x37fff;
- dev->block_start[BLOCK_DATA1] = 0x38000; /* DATA AREA 1 BLOCK */
- dev->block_end[BLOCK_DATA1] = 0x39fff;
- dev->block_start[BLOCK_DATA2] = 0x3a000; /* DATA AREA 2 BLOCK */
- dev->block_end[BLOCK_DATA2] = 0x3bfff;
- dev->block_start[BLOCK_BOOT] = 0x3c000; /* BOOT BLOCK */
- dev->block_end[BLOCK_BOOT] = 0x3ffff;
- }
- } else {
- dev->flash_id = (type & FLAG_BXB) ? 0x95 : 0x94;
-
- /* The block lengths are the same both flash types. */
- dev->block_len[BLOCK_MAIN1] = 0x1c000;
- dev->block_len[BLOCK_MAIN2] = 0x00000;
- dev->block_len[BLOCK_DATA1] = 0x01000;
- dev->block_len[BLOCK_DATA2] = 0x01000;
- dev->block_len[BLOCK_BOOT] = 0x02000;
-
- if (dev->flags & FLAG_BXB) { /* 28F001BX-B/28F100BX-B */
- dev->block_start[BLOCK_MAIN1] = 0x04000; /* MAIN BLOCK 1 */
- dev->block_end[BLOCK_MAIN1] = 0x1ffff;
- dev->block_start[BLOCK_MAIN2] = 0xfffff; /* MAIN BLOCK 2 */
- dev->block_end[BLOCK_MAIN2] = 0xfffff;
- dev->block_start[BLOCK_DATA1] = 0x02000; /* DATA AREA 1 BLOCK */
- dev->block_end[BLOCK_DATA1] = 0x02fff;
- dev->block_start[BLOCK_DATA2] = 0x03000; /* DATA AREA 2 BLOCK */
- dev->block_end[BLOCK_DATA2] = 0x03fff;
- dev->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */
- dev->block_end[BLOCK_BOOT] = 0x01fff;
- } else { /* 28F001BX-T/28F100BX-T */
- dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */
- dev->block_end[BLOCK_MAIN1] = 0x1bfff;
- dev->block_start[BLOCK_MAIN2] = 0xfffff; /* MAIN BLOCK 2 */
- dev->block_end[BLOCK_MAIN2] = 0xfffff;
- dev->block_start[BLOCK_DATA1] = 0x1c000; /* DATA AREA 1 BLOCK */
- dev->block_end[BLOCK_DATA1] = 0x1cfff;
- dev->block_start[BLOCK_DATA2] = 0x1d000; /* DATA AREA 2 BLOCK */
- dev->block_end[BLOCK_DATA2] = 0x1dfff;
- dev->block_start[BLOCK_BOOT] = 0x1e000; /* BOOT BLOCK */
- dev->block_end[BLOCK_BOOT] = 0x1ffff;
- }
- }
-
- intel_flash_add_mappings(dev);
-
- dev->command = CMD_READ_ARRAY;
- dev->status = 0;
-
- f = nvr_fopen(flash_path, L"rb");
- if (f) {
- fread(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, f);
- if (dev->block_len[BLOCK_MAIN2])
- fread(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, f);
- fread(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, f);
- fread(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, f);
- fclose(f);
- }
-
- free(flash_name);
- free(machine_name);
-
- if (dev->flags & FLAG_WORD)
- dev->flags &= ~FLAG_WORD;
-
- return dev;
-}
-
-
-static void
-intel_flash_close(void *p)
-{
- FILE *f;
- flash_t *dev = (flash_t *)p;
-
- f = nvr_fopen(flash_path, L"wb");
- fwrite(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, f);
- if (dev->block_len[BLOCK_MAIN2])
- fwrite(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, f);
- fwrite(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, f);
- fwrite(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, f);
- fclose(f);
-
- free(dev);
-}
-
-
-/* For AMI BIOS'es - Intel 28F001BXT with A16 pin inverted. */
-const device_t intel_flash_bxt_ami_device =
-{
- "Intel 28F001BXT/28F002BXT Flash BIOS",
- 0,
- FLAG_INV_A16,
- intel_flash_init,
- intel_flash_close,
- NULL,
- NULL, NULL, NULL, NULL
-};
-
-
-#if defined(DEV_BRANCH) && defined(USE_TC430HX)
-const device_t intel_flash_bxtw_ami_device =
-{
- "Intel 28F100BXT/28F200BXT Flash BIOS",
- 0,
- FLAG_INV_A16 | FLAG_WORD,
- intel_flash_init,
- intel_flash_close,
- NULL,
- NULL, NULL, NULL, NULL
-};
-#endif
-
-
-const device_t intel_flash_bxt_device =
-{
- "Intel 28F001BXT/28F002BXT Flash BIOS",
- 0, 0,
- intel_flash_init,
- intel_flash_close,
- NULL,
- NULL, NULL, NULL, NULL
-};
-
-
-const device_t intel_flash_bxb_device =
-{
- "Intel 28F001BXB/28F002BXB Flash BIOS",
- 0, FLAG_BXB,
- intel_flash_init,
- intel_flash_close,
- NULL,
- NULL, NULL, NULL, NULL
-};
diff --git a/src/intel_flash.c b/src/intel_flash.c
index 59dd16cc4..396899621 100644
--- a/src/intel_flash.c
+++ b/src/intel_flash.c
@@ -90,11 +90,6 @@ flash_read(uint32_t addr, void *p)
addr &= biosmask;
switch (dev->command) {
- case 0x00:
- case 0x93:
- ret = 0xff;
- break;
-
case CMD_READ_ARRAY:
default:
ret = dev->array[addr];
@@ -102,7 +97,7 @@ flash_read(uint32_t addr, void *p)
case CMD_IID:
if (addr & 1)
- ret = dev->flash_id & 0xff;
+ ret = dev->flash_id & 0xff;
else
ret = 0x89;
break;
@@ -134,11 +129,6 @@ flash_readw(uint32_t addr, void *p)
ret = *q;
if (dev->flags & FLAG_WORD) switch (dev->command) {
- case 0x00:
- case 0x93:
- ret = 0xffff;
- break;
-
case CMD_READ_ARRAY:
default:
break;
diff --git a/src/intel_piix - Cópia.c b/src/intel_piix - Cópia.c
deleted file mode 100644
index bc7aa2173..000000000
--- a/src/intel_piix - Cópia.c
+++ /dev/null
@@ -1,1131 +0,0 @@
-/*
- * 86Box A hypervisor and IBM PC system emulator that specializes in
- * running old operating systems and software designed for IBM
- * PC systems and compatibles from 1981 through fairly recent
- * system designs based on the PCI bus.
- *
- * Emulation of the Intel PIIX and PIIX3 Xcelerators.
- *
- * PRD format :
- * word 0 - base address
- * word 1 - bits 1-15 = byte count, bit 31 = end of transfer
- *
- * Version: @(#)intel_piix.c 1.0.23 2020/01/24
- *
- * Authors: Sarah Walker,
- * Miran Grca,
- *
- * Copyright 2008-2020 Sarah Walker.
- * Copyright 2016-2020 Miran Grca.
- */
-#include
-#include
-#include
-#include
-#include
-#include
-#define HAVE_STDARG_H
-#include "86box.h"
-#include "cdrom.h"
-#include "cpu.h"
-#include "scsi_device.h"
-#include "scsi_cdrom.h"
-#include "dma.h"
-#include "86box_io.h"
-#include "device.h"
-#include "apm.h"
-#include "keyboard.h"
-#include "mem.h"
-#include "timer.h"
-#include "nvr.h"
-#include "pci.h"
-#include "pic.h"
-#include "port_92.h"
-#include "hdc.h"
-#include "hdc_ide.h"
-#include "hdc_ide_sff8038i.h"
-#include "zip.h"
-#include "machine.h"
-#include "piix.h"
-
-
-#define ACPI_TIMER_FREQ 3579545
-
-
-typedef struct
-{
- uint16_t io_base;
- int base_channel;
-} ddma_t;
-
-
-typedef struct
-{
- int type;
- uint8_t cur_readout_reg,
- readout_regs[256],
- regs[256], regs_ide[256],
- regs_usb[256], regs_power[256];
- sff8038i_t *bm[2];
- ddma_t ddma[2];
- nvr_t * nvr;
-
- struct
- {
- uint16_t io_base;
- } usb;
-
- struct
- {
- uint16_t io_base;
- } power;
-} piix_t;
-
-
-#ifdef ENABLE_PIIX_LOG
-int piix_do_log = ENABLE_PIIX_LOG;
-
-
-static void
-piix_log(const char *fmt, ...)
-{
- va_list ap;
-
- if (piix_do_log) {
- va_start(ap, fmt);
- pclog_ex(fmt, ap);
- va_end(ap);
- }
-}
-#else
-#define piix_log(fmt, ...)
-#endif
-
-
-static void
-piix_bus_master_handlers(piix_t *dev, uint16_t old_base)
-{
- uint16_t base;
-
- base = (dev->regs_ide[0x20] & 0xf0) | (dev->regs_ide[0x21] << 8);
-
- sff_bus_master_handlers(dev->bm[0], old_base, base, (dev->regs_ide[0x04] & 1));
- sff_bus_master_handlers(dev->bm[1], old_base + 8, base + 8, (dev->regs_ide[0x04] & 1));
-}
-
-
-static uint8_t
-kbc_alias_reg_read(uint16_t addr, void *p)
-{
- uint8_t ret = inb(0x61);
-
- return ret;
-}
-
-
-static void
-kbc_alias_reg_write(uint16_t addr, uint8_t val, void *p)
-{
- outb(0x61, val);
-}
-
-
-static void
-kbc_alias_update_io_mapping(piix_t *dev)
-{
- io_removehandler(0x0063, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
- io_removehandler(0x0065, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
- io_removehandler(0x0067, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
-
- if (dev->regs[0x4e] & 0x08) {
- io_sethandler(0x0063, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
- io_sethandler(0x0065, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
- io_sethandler(0x0067, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
- }
-}
-
-
-static uint8_t
-ddma_reg_read(uint16_t addr, void *p)
-{
- ddma_t *dev = (ddma_t *) p;
- uint8_t ret = 0xff;
- int rel_ch = (addr & 0x30) >> 4;
- int ch = dev->base_channel + rel_ch;
- int dmab = (ch >= 4) ? 0xc0 : 0x00;
-
- switch (addr & 0x0f) {
- case 0x00:
- ret = dma[ch].ac & 0xff;
- break;
- case 0x01:
- ret = (dma[ch].ac >> 8) & 0xff;
- break;
- case 0x02:
- ret = dma[ch].page;
- break;
- case 0x04:
- ret = dma[ch].cc & 0xff;
- break;
- case 0x05:
- ret = (dma[ch].cc >> 8) & 0xff;
- break;
- case 0x09:
- ret = inb(dmab + 0x08);
- break;
- }
-
- return ret;
-}
-
-
-static void
-ddma_reg_write(uint16_t addr, uint8_t val, void *p)
-{
- ddma_t *dev = (ddma_t *) p;
- int rel_ch = (addr & 0x30) >> 4;
- int ch = dev->base_channel + rel_ch;
- int page_regs[4] = { 7, 3, 1, 2 };
- int i, dmab = (ch >= 4) ? 0xc0 : 0x00;
-
- switch (addr & 0x0f) {
- case 0x00:
- dma[ch].ab = (dma[ch].ab & 0xffff00) | val;
- dma[ch].ac = dma[ch].ab;
- break;
- case 0x01:
- dma[ch].ab = (dma[ch].ab & 0xff00ff) | (val << 8);
- dma[ch].ac = dma[ch].ab;
- break;
- case 0x02:
- if (ch >= 4)
- outb(0x88 + page_regs[rel_ch], val);
- else
- outb(0x80 + page_regs[rel_ch], val);
- break;
- case 0x04:
- dma[ch].cb = (dma[ch].cb & 0xffff00) | val;
- dma[ch].cc = dma[ch].cb;
- break;
- case 0x05:
- dma[ch].cb = (dma[ch].cb & 0xff00ff) | (val << 8);
- dma[ch].cc = dma[ch].cb;
- break;
- case 0x08:
- outb(dmab + 0x08, val);
- break;
- case 0x09:
- outb(dmab + 0x09, val);
- break;
- case 0x0a:
- outb(dmab + 0x0a, val);
- break;
- case 0x0b:
- outb(dmab + 0x0b, val);
- break;
- case 0x0d:
- outb(dmab + 0x0d, val);
- break;
- case 0x0e:
- for (i = 0; i < 4; i++)
- outb(dmab + 0x0a, i);
- break;
- case 0x0f:
- outb(dmab + 0x0a, (val << 2) | rel_ch);
- break;
- }
-}
-
-
-static void
-ddma_update_io_mapping(piix_t *dev, int n)
-{
- int base_reg = 0x92 + (n << 1);
-
- if (dev->ddma[n].io_base != 0x0000)
- io_removehandler(dev->usb.io_base, 0x40, ddma_reg_read, NULL, NULL, ddma_reg_write, NULL, NULL, &dev->ddma[n]);
-
- dev->ddma[n].io_base = (dev->regs[base_reg] & ~0x3f) | (dev->regs[base_reg + 1] << 8);
-
- if (dev->ddma[n].io_base != 0x0000)
- io_sethandler(dev->ddma[n].io_base, 0x40, ddma_reg_read, NULL, NULL, ddma_reg_write, NULL, NULL, &dev->ddma[n]);
-}
-
-
-static uint8_t
-usb_reg_read(uint16_t addr, void *p)
-{
- uint8_t ret = 0xff;
-
- switch (addr & 0x1f) {
- case 0x10: case 0x11: case 0x12: case 0x13:
- /* Port status */
- ret = 0x00;
- break;
- }
-
- return ret;
-}
-
-
-static void
-usb_reg_write(uint16_t addr, uint8_t val, void *p)
-{
-}
-
-
-static void
-usb_update_io_mapping(piix_t *dev)
-{
- if (dev->usb.io_base != 0x0000)
- io_removehandler(dev->usb.io_base, 0x20, usb_reg_read, NULL, NULL, usb_reg_write, NULL, NULL, dev);
-
- dev->usb.io_base = (dev->regs_usb[0x20] & ~0x1f) | (dev->regs_usb[0x21] << 8);
-
- if ((dev->regs_usb[PCI_REG_COMMAND] & PCI_COMMAND_IO) && (dev->usb.io_base != 0x0000))
- io_sethandler(dev->usb.io_base, 0x20, usb_reg_read, NULL, NULL, usb_reg_write, NULL, NULL, dev);
-}
-
-
-static uint8_t
-power_reg_read(uint16_t addr, void *p)
-{
- uint32_t timer;
- uint8_t ret = 0xff;
-
- switch (addr & 0x3f) {
- case 0x08: case 0x09: case 0x0a: case 0x0b:
- /* ACPI timer */
- timer = (tsc * ACPI_TIMER_FREQ) / machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed;
- timer &= 0x00ffffff;
- ret = (timer >> (8 * (addr & 3))) & 0xff;
- break;
- }
-
- return ret;
-}
-
-
-static void
-power_reg_write(uint16_t addr, uint8_t val, void *p)
-{
-}
-
-
-static void
-power_update_io_mapping(piix_t *dev)
-{
- if (dev->power.io_base != 0x0000)
- io_removehandler(dev->power.io_base, 0x40, power_reg_read, NULL, NULL, power_reg_write, NULL, NULL, dev);
-
- dev->power.io_base = (dev->regs_power[0x41] << 8) | (dev->regs_power[0x40] & 0xc0);
-
- if ((dev->regs_power[PCI_REG_COMMAND] & PCI_COMMAND_IO) && (dev->regs_power[0x80] & 0x01) && (dev->power.io_base != 0x0000))
- io_sethandler(dev->power.io_base, 0x100, power_reg_read, NULL, NULL, power_reg_write, NULL, NULL, dev);
-}
-
-
-static void
-piix_write(int func, int addr, uint8_t val, void *priv)
-{
- piix_t *dev = (piix_t *) priv;
- int type = dev->type & 0xff;
- uint8_t valxor;
- uint16_t old_base;
-
- if ((func > 0) && (dev->type & 0x100)) /* PB640's PIIX has no IDE part. */
- return;
-
- if ((func > 1) && ((type & 0xff) < 3)) /* PIIX has no USB part. */
- return;
-
- if ((func > 2) && ((type & 0xff) < 4)) /* PIIX and PIIX3 have no Power Management part. */
- return;
-
- if (func > 3)
- return;
-
- old_base = (dev->regs_ide[0x20] & 0xf0) | (dev->regs_ide[0x21] << 8);
-
- pclog("PIIX function %i write: %02X to %02X\n", func, val, addr);
-
- if (func == 3) { /* Power Management */
- /* Read-only addresses */
- if ((addr < 4) || (addr == 5) || (addr == 6) || ((addr >= 8) && (addr < 0x3c)) ||
- ((addr >= 0x3c) && (addr < 0x40)) || (addr == 0x53) ||
- ((addr >= 0x81) && (addr < 0x90)) || ((addr >= 0x94) && (addr < 0xd2)) ||
- (addr > 0xd6))
- return;
-
- switch (addr) {
- case 0x04:
- dev->regs_power[0x04] = val & 0x01;
- power_update_io_mapping(dev);
- break;
- case 0x07:
- dev->regs_power[0x07] = val & 0x0e;
- break;
-
- case 0x3c:
- dev->regs_power[0x3c] = val;
- break;
-
- case 0x40:
- dev->regs_power[0x20] = (val & ~0x3f) | 1;
- power_update_io_mapping(dev);
- break;
- case 0x41:
- dev->regs_power[0x21] = val;
- power_update_io_mapping(dev);
- break;
-
- case 0x80:
- dev->regs_power[0x80] = val & 0x01;
- power_update_io_mapping(dev);
- break;
-
- default:
- dev->regs_power[addr] = val;
- break;
- }
- } else if (func == 2) { /* USB */
- /* Read-only addresses */
- if ((addr < 4) || (addr == 5) || (addr == 6) || ((addr >= 8) && (addr < 0xd)) ||
- ((addr >= 0xe) && (addr < 0x20)) || ((addr >= 0x22) && (addr < 0x3c)) ||
- ((addr >= 0x3e) && (addr < 0x40)) || ((addr >= 0x42) && (addr < 0x44)) ||
- ((addr >= 0x46) && (addr < 0xc0)) || (addr >= 0xc2))
- return;
-
- switch (addr) {
- case 0x04:
- dev->regs_usb[0x04] = val & 0x97;
- usb_update_io_mapping(dev);
- break;
- case 0x07:
- dev->regs_usb[0x07] = val & 0x7f;
- break;
-
- case 0x20:
- dev->regs_usb[0x20] = (val & ~0x1f) | 1;
- usb_update_io_mapping(dev);
- break;
- case 0x21:
- dev->regs_usb[0x21] = val;
- usb_update_io_mapping(dev);
- break;
-
- case 0xff:
- if (type >= 4) {
- dev->regs_usb[addr] = val & 0x10;
- nvr_at_handler(0, 0x0070, dev->nvr);
- if ((dev->regs[0xcb] & 0x01) && (dev->regs_usb[0xff] & 0x10))
- nvr_at_handler(1, 0x0070, dev->nvr);
- }
- break;
-
- default:
- dev->regs_usb[addr] = val;
- break;
- }
- } else if (func == 1) { /* IDE */
- piix_log("PIIX IDE write: %02X %02X\n", addr, val);
- valxor = val ^ dev->regs_ide[addr];
-
- switch (addr) {
- case 0x04:
- pclog("04 write: %02X\n", val);
- dev->regs_ide[0x04] = (val & 5);
- if (valxor & 0x01) {
- ide_pri_disable();
- ide_sec_disable();
- if (val & 0x01) {
- // pclog("04: I/O enabled\n");
- if (dev->regs_ide[0x41] & 0x80) {
- // pclog("04: PRI enabled\n");
- ide_pri_enable();
- }
- if (dev->regs_ide[0x43] & 0x80) {
- // pclog("04: SEC enabled\n");
- ide_sec_enable();
- }
- } else
- // pclog("04: I/O disabled\n");
-
- piix_bus_master_handlers(dev, old_base);
- }
- break;
- case 0x07:
- dev->regs_ide[0x07] = (dev->regs_ide[0x07] & 0xf9) | (val & 0x06);
- if (val & 0x20)
- dev->regs_ide[0x07] &= 0xdf;
- if (val & 0x10)
- dev->regs_ide[0x07] &= 0xef;
- if (val & 0x08)
- dev->regs_ide[0x07] &= 0xf7;
- if (val & 0x04)
- dev->regs_ide[0x07] &= 0xfb;
- break;
- case 0x0d:
- dev->regs_ide[0x0d] = val & 0xf0;
- break;
-
- case 0x20:
- dev->regs_ide[0x20] = (val & 0xf0) | 1;
- if (valxor)
- piix_bus_master_handlers(dev, old_base);
- break;
- case 0x21:
- dev->regs_ide[0x21] = val;
- if (valxor)
- piix_bus_master_handlers(dev, old_base);
- break;
-
- case 0x40:
- dev->regs_ide[0x40] = val;
- break;
- case 0x41:
- dev->regs_ide[0x41] = val & ((type >= 3) ? 0xf3 : 0xb3);
- if (valxor & 0x80) {
- ide_pri_disable();
- if ((val & 0x80) && (dev->regs_ide[0x04] & 0x01))
- ide_pri_enable();
- }
- break;
- case 0x42:
- dev->regs_ide[0x42] = val;
- break;
- case 0x43:
- dev->regs_ide[0x43] = val & ((type >= 3) ? 0xf3 : 0xb3);
- if (valxor & 0x80) {
- ide_sec_disable();
- if ((val & 0x80) && (dev->regs_ide[0x04] & 0x01))
- ide_sec_enable();
- }
- break;
- case 0x44:
- if (type >= 3) dev->regs_ide[0x44] = val;
- break;
- case 0x48:
- case 0x4a: case 0x4b:
- if (type >= 4) dev->regs_ide[addr] = val;
- break;
- }
- } else {
- piix_log("PIIX writing value %02X to register %02X\n", val, addr);
- valxor = val ^ dev->regs[addr];
-
- if ((addr >= 0x0f) && (addr < 0x4c))
- return;
-
- if ((addr >= 0xa0) && (addr < 0xb0) && (type == 4))
- return;
-
- switch (addr) {
- case 0x00: case 0x01: case 0x02: case 0x03:
- case 0x08: case 0x09: case 0x0a: case 0x0b:
- case 0x0e:
- return;
-
- case 0x07:
- dev->regs[0x07] = (dev->regs[0x07] & 0xf9) | (val & 0x06);
- if ((val & 0x40) && (type >= 3))
- dev->regs[0x07] &= 0xbf;
- if (val & 0x20)
- dev->regs[0x07] &= 0xdf;
- if (val & 0x10)
- dev->regs[0x07] &= 0xef;
- if (val & 0x08)
- dev->regs[0x07] &= 0xf7;
- if (val & 0x04)
- dev->regs[0x07] &= 0xfb;
- return;
- break;
- case 0x4c:
- if (valxor) {
- if (type >= 3)
- dma_alias_remove();
- else
- dma_alias_remove_piix();
- if (!(val & 0x80))
- dma_alias_set();
- }
- break;
- case 0x4e:
- keyboard_at_set_mouse_scan((val & 0x10) ? 1 : 0);
- if (type >= 4)
- kbc_alias_update_io_mapping(dev);
- break;
- case 0x60:
- piix_log("Set IRQ routing: INT A -> %02X\n", val);
- if (val & 0x80)
- pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
- else
- pci_set_irq_routing(PCI_INTA, val & 0xf);
- break;
- case 0x61:
- piix_log("Set IRQ routing: INT B -> %02X\n", val);
- if (val & 0x80)
- pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
- else
- pci_set_irq_routing(PCI_INTB, val & 0xf);
- break;
- case 0x62:
- piix_log("Set IRQ routing: INT C -> %02X\n", val);
- if (val & 0x80)
- pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
- else
- pci_set_irq_routing(PCI_INTC, val & 0xf);
- break;
- case 0x63:
- piix_log("Set IRQ routing: INT D -> %02X\n", val);
- if (val & 0x80)
- pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
- else
- pci_set_irq_routing(PCI_INTD, val & 0xf);
- break;
- case 0x6a:
- if (dev->type == 3)
- dev->regs[addr] = (val & 0xFD) | (dev->regs[addr] | 2);
- else
- dev->regs[addr] = (val & 0xFC) | (dev->regs[addr] | 3);
- return;
- case 0x70:
- piix_log("Set MIRQ routing: MIRQ0 -> %02X\n", val);
- if (type < 4) {
- if (val & 0x80)
- pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
- else
- pci_set_mirq_routing(PCI_MIRQ0, val & 0xf);
- }
- break;
- piix_log("MIRQ0 is %s\n", (val & 0x20) ? "disabled" : "enabled");
- case 0x71:
- if (type < 3) {
- piix_log("Set MIRQ routing: MIRQ1 -> %02X\n", val);
- if (val & 0x80)
- pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
- else
- pci_set_mirq_routing(PCI_MIRQ1, val & 0xf);
- }
- break;
- case 0x92: case 0x93: case 0x94: case 0x95:
- if (type == 4)
- ddma_update_io_mapping(dev, (addr >> 2) & 1);
- break;
- case 0xcb:
- if (type == 4) {
- nvr_at_handler(0, 0x0070, dev->nvr);
- nvr_at_handler(0, 0x0072, dev->nvr);
-
- if ((val & 0x01) && (dev->regs_usb[0xff] & 0x10))
- nvr_at_handler(1, 0x0070, dev->nvr);
- if (val & 0x04)
- nvr_at_handler(1, 0x0072, dev->nvr);
-
- nvr_wp_set(!!(val & 0x08), 0, dev->nvr);
- nvr_wp_set(!!(val & 0x10), 1, dev->nvr);
- }
- break;
- }
-
- dev->regs[addr] = val;
- }
-}
-
-
-static uint8_t
-piix_read(int func, int addr, void *priv)
-{
- piix_t *dev = (piix_t *) priv;
- int type = dev->type & 0xff;
- int ret = 0xff, ignore = 0;
-
- if ((func > 0) && (dev->type & 0x100)) /* PB640's PIIX has no IDE part. */
- ignore = 1;
-
- if ((func > 1) && ((type & 0xff) < 3)) /* PIIX has no USB part. */
- ignore = 1;
-
- if ((func > 2) && ((type & 0xff) < 4)) /* PIIX and PIIX3 have no Power Management part. */
- ignore = 1;
-
- if (func > 3)
- ignore = 1;
-
- if (!ignore) {
- ret = 0x00;
-
- if (func == 3) /* Power Management */
- ret = dev->regs_power[addr];
- else if (func == 2) /* USB */
- ret = dev->regs_usb[addr];
- else if (func == 1) switch (addr) { /* IDE */
- case 0x05: case 0x22: case 0x23:
- ret = 0x00;
- break;
- case 0x06:
- ret = 0x80;
- break;
- default:
- ret = dev->regs_ide[addr];
- break;
- } else if (func == 0) switch (addr) {
- case 0x04:
- ret = (dev->regs[addr] & 0x80) | ((dev->type & 0x100) ? 0x0f : 0x07);
- break;
- case 0x05:
- if (type >= 3)
- ret = dev->regs[addr] & 1;
- else
- ret = 0;
- break;
- case 0x06:
- ret = dev->regs[addr] & 0x80;
- break;
- case 0x07:
- if (type >= 3)
- ret = dev->regs[addr];
- else {
- if (dev->type & 0x100)
- ret = dev->regs[addr] & 0x02;
- else
- ret = dev->regs[addr] & 0x3E;
- }
- break;
- caer 0x4e:
- ret = (dev->regs[addr] & 0xef) | keyboard_at_get_mouse_scan();
- case 0x60: case 0x61: case 0x62: cae 0x63:
- ret = dev->regs[addr] & 0x8f;
- break;
- case 0x69:
- ret = dev->regs[addr] & 0xfe;
- break;
- case 0x6a:
- if (dev->type == 3)
- ret = dev->regs[addr] & 0xD1;
- else
- ret = dev->regs[addr] & 0x07;
- break;
- case 0x6b:
- if (dev->type == 3)
- ret = dev->regs[addr] & 0x80;
- else
- ret = 0x00;
- break;
- case 0x70:
- if (type < 4)
- ret = dev->regs[addr] & ((type >= 3) ? 0xef : 0xcf);
- else
- ret = 0x00;
- break;
- case 0x71:
- if (type < 3)
- ret = dev->regs[addr] & 0xcf;
- else
- ret = 0x00;
- break;
- case 0x76: case 0x77:
- if (dev->type == 3)
- ret = dev->regs[addr] & 0x87;
- else
- ret = dev->regs[addr] & 0x8F;
- break;
- case 0x80:
- if (dev->type == 3)
- ret = dev->regs[addr] & 0x7f;
- else if (dev->type == 1)
- ret = 0x00;
- break;
- case 0x82:
- if (dev->type == 3)
- ret = dev->regs[addr] & 0x0f;
- else
- ret = 0x00;
- break;
- case 0xa0:
- ret = dev->regs[addr] & 0x1f;
- break;
- case 0xa3:
- if (dev->type == 3)
- ret = dev->regs[addr] & 1;
- else
- ret = 0x00;
- break;
- case 0xa7:
- if (dev->type == 3)
- ret = dev->regs[addr];
- else
- ret = dev->regs[addr] & 0xef;
- break;
- case 0xab:
- if (dev->type == 3)
- ret = dev->regs[addr];
- else
- ret = dev->regs[addr] & 0xfe;
- break;
- default:
- ret = dev->regs[addr];
- break;
- }
- }
-
- pclog("PIIX function %i read: %02X from %02X\n", func, ret, addr);
-
- return ret;
-}
-
-
-static void
-board_write(uint16_t port, uint8_t val, void *priv)
-{
- piix_t *dev = (piix_t *) priv;
-
- // pclog("board write %02X at %04X\n", val, port);
-
- if (port == 0x00e0)
- dev->cur_readout_reg = val;
- else if (port == 0x00e1)
- dev->readout_regs[dev->cur_readout_reg] = val;
-}
-
-
-static uint8_t
-board_read(uint16_t port, void *priv)
-{
- piix_t *dev = (piix_t *) priv;
- uint8_t ret = 0xff;
-
- if (port == 0x00e0)
- ret = dev->cur_readout_reg;
- else if (port == 0x00e1)
- ret = dev->readout_regs[dev->cur_readout_reg];
-
- // pclog("board read %02X at %04X\n", ret, port);
-
- return ret;
-}
-
-
-static void
-piix_reset_hard(void *priv)
-{
- piix_t *piix = (piix_t *) priv;
- int type = (piix->type & 0xff);
-
- uint16_t old_base = (piix->regs_ide[0x20] & 0xf0) | (piix->regs_ide[0x21] << 8);
-
- if (!(piix->type & 0x100)) { /* PB640's PIIX has no IDE part. */
- sff_bus_master_reset(piix->bm[0], old_base);
- sff_bus_master_reset(piix->bm[1], old_base + 8);
-
- if (type == 4) {
- sff_set_irq_mode(piix->bm[0], 0);
- sff_set_irq_mode(piix->bm[1], 0);
- }
-
- pclog("piix_reset_hard()\n");
- ide_pri_disable();
- ide_sec_disable();
- }
-
- if (type == 4) {
- nvr_at_handler(0, 0x0072, piix->nvr);
- nvr_wp_set(0, 0, piix->nvr);
- nvr_wp_set(0, 1, piix->nvr);
- }
-
- memset(piix->regs, 0, 256);
- memset(piix->regs_ide, 0, 256);
- memset(piix->regs_usb, 0, 256);
- memset(piix->regs_power, 0, 256);
-
- piix->regs[0x00] = 0x86; piix->regs[0x01] = 0x80; /*Intel*/
- if (type == 4) {
- piix->regs[0x02] = 0x10; piix->regs[0x03] = 0x71; /*82371AB (PIIX4)*/
- } else if (type == 3) {
- piix->regs[0x02] = 0x00; piix->regs[0x03] = 0x70; /*82371SB (PIIX3)*/
- } else {
- piix->regs[0x02] = 0x2e; piix->regs[0x03] = 0x12; /*82371FB (PIIX)*/
- }
- if (piix->type & 0x100)
- piix->regs[0x04] = 0x06;
- else
- piix->regs[0x04] = 0x07;
- piix->regs[0x05] = 0x00;
- piix->regs[0x06] = 0x80; piix->regs[0x07] = 0x02;
- if (piix->type & 0x100)
- piix->regs[0x08] = 0x02; /*A0 stepping*/
- else
- piix->regs[0x08] = 0x00; /*A0 stepping*/
- piix->regs[0x09] = 0x00; piix->regs[0x0a] = 0x01; piix->regs[0x0b] = 0x06;
- if (piix->type & 0x100)
- piix->regs[0x0e] = 0x00; /*Single-function device*/
- else
- piix->regs[0x0e] = 0x80; /*Multi-function device*/
- piix->regs[0x4c] = 0x4d;
- piix->regs[0x4e] = 0x03;
- if (type >= 3)
- piix->regs[0x4f] = 0x00;
- piix->regs[0x60] = piix->regs[0x61] = piix->regs[0x62] = piix->regs[0x63] = 0x80;
- if (type == 4)
- piix->regs[0x64] = 0x10;
- piix->regs[0x69] = 0x02;
- if (type < 4)
- piix->regs[0x70] = 0xc0;
- if (type < 3)
- piix->regs[0x71] = 0xc0;
- piix->regs[0x76] = piix->regs[0x77] = 0x0c;
- piix->regs[0x78] = 0x02; piix->regs[0x79] = 0x00;
- if (type == 3) {
- piix->regs[0x80] = piix->regs[0x82] = 0x00;
- }
- piix->regs[0xa0] = 0x08;
- piix->regs[0xa2] = piix->regs[0xa3] = 0x00;
- piix->regs[0xa4] = piix->regs[0xa5] = piix->regs[0xa6] = piix->regs[0xa7] = 0x00;
- piix->regs[0xa8] = 0x0f;
- piix->regs[0xaa] = piix->regs[0xab] = 0x00;
- piix->regs[0xac] = 0x00;
- piix->regs[0xae] = 0x00;
- if (type == 4)
- piix->regs[0xcb] = 0x21;
-
- piix->regs_ide[0x00] = 0x86; piix->regs_ide[0x01] = 0x80; /*Intel*/
- if (type == 4) {
- piix->regs_ide[0x02] = 0x11; piix->regs_ide[0x03] = 0x71; /*82371AB (PIIX4)*/
- } else if (type == 3) {
- piix->regs_ide[0x02] = 0x10; piix->regs_ide[0x03] = 0x70; /*82371SB (PIIX3)*/
- } else {
- piix->regs_ide[0x02] = 0x30; piix->regs_ide[0x03] = 0x12; /*82371FB (PIIX)*/
- }
- piix->regs_ide[0x04] = 0x00; piix->regs_ide[0x05] = 0x00;
- piix->regs_ide[0x06] = 0x80; piix->regs_ide[0x07] = 0x02;
- piix->regs_ide[0x08] = 0x00;
- piix->regs_ide[0x09] = 0x80; piix->regs_ide[0x0a] = 0x01; piix->regs_ide[0x0b] = 0x01;
- piix->regs_ide[0x0d] = 0x00;
- piix->regs_ide[0x0e] = 0x00;
- piix->regs_ide[0x20] = 0x01; piix->regs_ide[0x21] = piix->regs_ide[0x22] = piix->regs_ide[0x23] = 0x00; /*Bus master interface base address*/
- piix->regs_ide[0x40] = piix->regs_ide[0x42] = 0x00;
- piix->regs_ide[0x41] = piix->regs_ide[0x43] = 0x00;
- if (type >= 3)
- piix->regs_ide[0x44] = 0x00;
- if (type == 4) {
- piix->regs_ide[0x48] = piix->regs_ide[0x4a] =
- piix->regs_ide[0x4b] = 0x00;
- }
-
- if (type >= 3) {
- piix->regs_usb[0x00] = 0x86; piix->regs_usb[0x01] = 0x80; /*Intel*/
- if (type == 4) {
- piix->regs_usb[0x02] = 0x12; piix->regs_usb[0x03] = 0x71; /*82371AB (PIIX4)*/
- } else {
- piix->regs_usb[0x02] = 0x20; piix->regs_usb[0x03] = 0x70; /*82371SB (PIIX3)*/
- }
- piix->regs_usb[0x04] = 0x00; piix->regs_usb[0x05] = 0x00;
- piix->regs_usb[0x06] = 0x00; piix->regs_usb[0x07] = 0x02;
- piix->regs_usb[0x0a] = 0x03;
- piix->regs_usb[0x0b] = 0x0c;
- piix->regs_usb[0x0d] = 0x16;
- piix->regs_usb[0x20] = 0x01;
- piix->regs_usb[0x21] = 0x03;
- piix->regs_usb[0x3d] = 0x04;
-
- piix->regs_usb[0x60] = 0x10;
- piix->regs_usb[0xc1] = 0x20;
- }
-
- if (type == 4) {
- piix->regs_power[0x00] = 0x86; piix->regs_power[0x01] = 0x80; /*Intel*/
- piix->regs_power[0x02] = 0x13; piix->regs_power[0x03] = 0x71; /*82371AB (PIIX4)*/
- piix->regs_power[0x04] = 0x00; piix->regs_power[0x05] = 0x00;
- piix->regs_power[0x06] = 0x80; piix->regs_power[0x07] = 0x02;
- piix->regs_power[0x08] = 0x00; /*Initial Stepping=00h*/
- piix->regs_power[0x0a] = 0x80;
- piix->regs_power[0x0b] = 0x06;
- piix->regs_power[0x3d] = 0x01;
- piix->regs_power[0x40] = 0x01;
- piix->regs_power[0x90] = 0x01;
- }
-
- pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
- pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
- pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
- pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
-
- if (type < 4)
- pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
- if (type < 3)
- pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
-}
-
-
-static void
-piix_close(void *p)
-{
- piix_t *piix = (piix_t *)p;
-
- free(piix);
-}
-
-
-static void
-*piix_init(const device_t *info)
-{
- piix_t *piix = (piix_t *) malloc(sizeof(piix_t));
- int type;
- memset(piix, 0, sizeof(piix_t));
-
- pci_add_card(7, piix_read, piix_write, piix);
-
- piix->type = info->local;
- type = (piix->type & 0xff);
-
- device_add(&apm_device);
-
- if (!(piix->type & 0x100)) { /* PB640's PIIX has no IDE part. */
- piix->bm[0] = device_add_inst(&sff8038i_device, 1);
- piix->bm[1] = device_add_inst(&sff8038i_device, 2);
- }
-
- if (type == 4)
- piix->nvr = device_add(&piix4_nvr_device);
-
- piix_reset_hard(piix);
-
- device_add(&port_92_pci_device);
-
- dma_alias_set();
-
- if (type < 4)
- pci_enable_mirq(0);
- if (type < 3)
- pci_enable_mirq(1);
-
- piix->readout_regs[1] = 0x40;
-
- /* Port E1 register 01 (TODO: Find how multipliers > 3.0 are defined):
-
- Bit 6: 1 = can boot, 0 = no;
- Bit 7, 1 = multiplier (00 = 2.5, 01 = 2.0, 10 = 3.0, 11 = 1.5);
- Bit 5, 4 = bus speed (00 = 50 MHz, 01 = 66 MHz, 10 = 60 MHz, 11 = ????):
- Bit 7, 5, 4, 1: 0000 = 125 MHz, 0010 = 166 MHz, 0100 = 150 MHz, 0110 = ??? MHz;
- 0001 = 100 MHz, 0011 = 133 MHz, 0101 = 120 MHz, 0111 = ??? MHz;
- 1000 = 150 MHz, 1010 = 200 MHz, 1100 = 180 MHz, 1110 = ??? MHz;
- 1001 = 75 MHz, 1011 = 100 MHz, 1101 = 90 MHz, 1111 = ??? MHz */
-
- switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].pci_speed) {
- case 20000000:
- piix->readout_regs[1] |= 0x30;
- break;
- case 25000000:
- default:
- piix->readout_regs[1] |= 0x00;
- break;
- case 30000000:
- piix->readout_regs[1] |= 0x20;
- break;
- case 33333333:
- piix->readout_regs[1] |= 0x10;
- break;
- }
-
- switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed) {
- case 75000000:
- piix->readout_regs[1] |= 0x82; /* 50 MHz * 1.5 multiplier */
- break;
- case 90000000:
- piix->readout_regs[1] |= 0x82; /* 60 MHz * 1.5 multiplier */
- break;
- case 100000000:
- if ((piix->readout_regs[1] & 0x30) == 0x10)
- piix->readout_regs[1] |= 0x82; /* 66 MHz * 1.5 multiplier */
- else
- piix->readout_regs[1] |= 0x02; /* 50 MHz * 2.0 multiplier */
- break;
- case 12000000:
- piix->readout_regs[1] |= 0x02; /* 60 MHz * 2.0 multiplier */
- break;
- case 125000000:
- piix->readout_regs[1] |= 0x00; /* 50 MHz * 2.5 multiplier */
- break;
- case 133333333:
- piix->readout_regs[1] |= 0x02; /* 66 MHz * 2.0 multiplier */
- break;
- case 150000000:
- if ((piix->readout_regs[1] & 0x30) == 0x20)
- piix->readout_regs[1] |= 0x00; /* 60 MHz * 2.5 multiplier */
- else
- piix->readout_regs[1] |= 0x80; /* 50 MHz * 3.0 multiplier */
- break;
- case 166666666:
- piix->readout_regs[1] |= 0x00; /* 66 MHz * 2.5 multiplier */
- break;
- case 180000000:
- piix->readout_regs[1] |= 0x80; /* 60 MHz * 3.0 multiplier */
- break;
- case 200000000:
- piix->readout_regs[1] |= 0x80; /* 66 MHz * 3.0 multiplier */
- break;
- }
-
- io_sethandler(0x0078, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, piix);
- io_sethandler(0x00e0, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, piix);
-
- return piix;
-}
-
-
-const device_t piix_device =
-{
- "Intel 82371FB (PIIX)",
- DEVICE_PCI,
- 1,
- piix_init,
- piix_close,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-const device_t piix_pb640_device =
-{
- "Intel 82371FB (PIIX) (PB640)",
- DEVICE_PCI,
- 0x101,
- piix_init,
- piix_close,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-const device_t piix3_device =
-{
- "Intel 82371SB (PIIX3)",
- DEVICE_PCI,
- 3,
- piix_init,
- piix_close,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL
-};
-
-const device_t piix4_device =
-{
- "Intel 82371AB (PIIX4)",
- DEVICE_PCI,
- 4,
- piix_init,
- piix_close,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL
-};
diff --git a/src/intel_piix.c b/src/intel_piix.c
index dd504cf25..bd2c42d9a 100644
--- a/src/intel_piix.c
+++ b/src/intel_piix.c
@@ -35,6 +35,7 @@
#include "device.h"
#include "apm.h"
#include "keyboard.h"
+#include "machine.h"
#include "mem.h"
#include "timer.h"
#include "nvr.h"
@@ -46,6 +47,7 @@
#include "hdc_ide_sff8038i.h"
#include "zip.h"
#include "machine.h"
+#include "smbus.h"
#include "piix.h"
@@ -87,11 +89,12 @@ typedef struct
typedef struct
{
- uint8_t stat, ctl, cmd, addr,
+ uint8_t stat, next_stat, ctl, cmd, addr,
data0, data1,
index,
data[32];
-} smbus_t;
+ pc_timer_t command_timer;
+} piix_smbus_t;
typedef struct
@@ -107,7 +110,7 @@ typedef struct
sff8038i_t *bm[2];
ddma_t ddma[2];
power_t power;
- smbus_t smbus;
+ piix_smbus_t smbus;
nvr_t * nvr;
} piix_t;
@@ -140,12 +143,18 @@ void do_irq(piix_t *dev, int func, int level)
return;
if (level) {
- // pci_set_irq(dev->pci_slot, dev->regs[func][0x3d]);
+#ifdef WRONG_SPEC
+ pci_set_irq(dev->pci_slot, dev->regs[func][0x3d]);
+#else
picintlevel(1 << 9);
+#endif
piix_log("Raising IRQ...\n");
} else {
- // pci_clear_irq(dev->pci_slot, dev->regs[func][0x3d]);
+#ifdef WRONG_SPEC
+ pci_clear_irq(dev->pci_slot, dev->regs[func][0x3d]);
+#else
picintc(1 << 9);
+#endif
piix_log("Lowering IRQ...\n");
}
}
@@ -367,7 +376,7 @@ power_reg_readl(uint16_t addr, void *p)
break;
}
- // pclog("ACPI: Read L %08X from %04X\n", ret, addr);
+ piix_log("ACPI: Read L %08X from %04X\n", ret, addr);
return ret;
}
@@ -392,7 +401,7 @@ power_reg_readw(uint16_t addr, void *p)
break;
}
- // pclog("ACPI: Read W %08X from %04X\n", ret, addr);
+ piix_log("ACPI: Read W %08X from %04X\n", ret, addr);
return ret;
}
@@ -409,11 +418,11 @@ power_reg_read(uint16_t addr, void *p)
switch (addr & 0x3f) {
case 0x30: case 0x31: case 0x32:
ret = dev->power.gporeg[addr & 0x03];
- // pclog("ACPI: Read B %02X from GPIREG %01X\n", ret, addr & 0x03);
+ piix_log("ACPI: Read B %02X from GPIREG %01X\n", ret, addr & 0x03);
break;
case 0x34: case 0x35: case 0x36: case 0x37:
ret = dev->power.gporeg[addr & 0x03];
- // pclog("ACPI: Read B %02X from GPOREG %01X\n", ret, addr & 0x03);
+ piix_log("ACPI: Read B %02X from GPOREG %01X\n", ret, addr & 0x03);
break;
default:
ret16 = power_reg_readw(addr, p);
@@ -433,7 +442,7 @@ power_reg_write(uint16_t addr, uint8_t val, void *p)
{
piix_t *dev = (piix_t *) p;
- // pclog("ACPI: Write %02X to %04X\n", val, addr);
+ piix_log("ACPI: Write %02X to %04X\n", val, addr);
switch (addr & 0x3f) {
case 0x34: case 0x35: case 0x36: case 0x37:
@@ -457,17 +466,145 @@ power_update_io_mapping(piix_t *dev)
static uint8_t
-smbus_reg_read(uint16_t addr, void *p)
+smbus_reg_read(uint16_t addr, void *priv)
{
+ piix_t *dev = (piix_t *) priv;
uint8_t ret = 0x00;
+ switch (addr - dev->smbus_io_base) {
+ case 0x00:
+ ret = dev->smbus.stat;
+ break;
+ case 0x02:
+ dev->smbus.index = 0;
+ ret = dev->smbus.ctl;
+ break;
+ case 0x03:
+ ret = dev->smbus.cmd;
+ break;
+ case 0x04:
+ ret = dev->smbus.addr;
+ break;
+ case 0x05:
+ ret = dev->smbus.data0;
+ break;
+ case 0x06:
+ ret = dev->smbus.data1;
+ break;
+ case 0x07:
+ ret = dev->smbus.data[dev->smbus.index++];
+ if (dev->smbus.index > 31)
+ dev->smbus.index = 0;
+ break;
+ }
+
+ piix_log("smbus_reg_read %02x %02x\n", addr - dev->smbus_io_base, ret);
+
return ret;
}
static void
-smbus_reg_write(uint16_t addr, uint8_t val, void *p)
+smbus_reg_write(uint16_t addr, uint8_t val, void *priv)
{
+ piix_t *dev = (piix_t *) priv;
+ uint8_t smbus_addr;
+ uint8_t smbus_read;
+ uint16_t temp;
+
+ piix_log("smbus_reg_write %02x %02x\n", addr - dev->smbus_io_base, val);
+
+ dev->smbus.next_stat = 0;
+ switch (addr - dev->smbus_io_base) {
+ case 0x00:
+ /* some status bits are reset by writing 1 to them */
+ for (smbus_addr = 0x02; smbus_addr <= 0x10; smbus_addr = smbus_addr << 1) {
+ if (val & smbus_addr)
+ dev->smbus.stat = dev->smbus.stat & ~smbus_addr;
+ }
+ break;
+ case 0x02:
+ dev->smbus.ctl = val & ~(0x40); /* START always reads 0 */
+ if (val & 0x40) { /* dispatch command if START is set */
+ smbus_addr = (dev->smbus.addr >> 1);
+ if (!smbus_has_device(smbus_addr)) {
+ /* raise DEV_ERR if no device is at this address */
+ dev->smbus.next_stat = 0x4;
+ break;
+ }
+ smbus_read = (dev->smbus.addr & 0x01);
+
+ switch ((val >> 2) & 0x7) {
+ case 0x0: /* quick R/W */
+ dev->smbus.next_stat = 0x2;
+ break;
+ case 0x1: /* byte R/W */
+ if (smbus_read)
+ dev->smbus.data0 = smbus_read_byte(smbus_addr);
+ else
+ smbus_write_byte(smbus_addr, dev->smbus.data0);
+ dev->smbus.next_stat = 0x2;
+ break;
+ case 0x2: /* byte data R/W */
+ if (smbus_read)
+ dev->smbus.data0 = smbus_read_byte_cmd(smbus_addr, dev->smbus.cmd);
+ else
+ smbus_write_byte_cmd(smbus_addr, dev->smbus.cmd, dev->smbus.data0);
+ dev->smbus.next_stat = 0x2;
+ break;
+ case 0x3: /* word data R/W */
+ if (smbus_read) {
+ temp = smbus_read_word_cmd(smbus_addr, dev->smbus.cmd);
+ dev->smbus.data0 = (temp & 0xFF);
+ dev->smbus.data1 = (temp >> 8);
+ } else {
+ temp = (dev->smbus.data1 << 8) | dev->smbus.data0;
+ smbus_write_word_cmd(smbus_addr, dev->smbus.cmd, temp);
+ }
+ dev->smbus.next_stat = 0x2;
+ break;
+ case 0x5: /* block R/W */
+ if (smbus_read)
+ dev->smbus.data0 = smbus_read_block_cmd(smbus_addr, dev->smbus.cmd, dev->smbus.data);
+ else
+ smbus_write_block_cmd(smbus_addr, dev->smbus.cmd, dev->smbus.data, dev->smbus.data0);
+ dev->smbus.next_stat = 0x2;
+ break;
+ }
+ }
+ break;
+ case 0x03:
+ dev->smbus.cmd = val;
+ break;
+ case 0x04:
+ dev->smbus.addr = val;
+ break;
+ case 0x05:
+ dev->smbus.data0 = val;
+ break;
+ case 0x06:
+ dev->smbus.data1 = val;
+ break;
+ case 0x07:
+ dev->smbus.data[dev->smbus.index++] = val;
+ if (dev->smbus.index > 31)
+ dev->smbus.index = 0;
+ break;
+ }
+
+ if (dev->smbus.next_stat) {
+ dev->smbus.stat = 0x1;
+ timer_disable(&dev->smbus.command_timer);
+ timer_set_delay_u64(&dev->smbus.command_timer, 10 * TIMER_USEC);
+ }
+}
+
+
+static void
+smbus_inter(void *priv)
+{
+ piix_t *dev = (piix_t *) priv;
+ dev->smbus.stat = dev->smbus.next_stat;
}
@@ -494,7 +631,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
if (func > dev->max_func)
return;
- // pclog("PIIX function %i write: %02X to %02X\n", func, val, addr);
+ piix_log("PIIX function %i write: %02X to %02X\n", func, val, addr);
fregs = (uint8_t *) dev->regs[func];
if (func == 0) switch (addr) {
@@ -717,6 +854,10 @@ piix_write(int func, int addr, uint8_t val, void *priv)
fregs[0x21] = val;
piix_ide_bm_handlers(dev);
break;
+ case 0x3c:
+ piix_log("IDE IRQ write: %02X\n", val);
+ fregs[0x3c] = val;
+ break;
case 0x40: case 0x42:
fregs[addr] = val;
break;
@@ -884,7 +1025,7 @@ piix_read(int func, int addr, void *priv)
fregs = (uint8_t *) dev->regs[func];
ret = fregs[addr];
- // pclog("PIIX function %i read: %02X from %02X\n", func, ret, addr);
+ piix_log("PIIX function %i read: %02X from %02X\n", func, ret, addr);
}
return ret;
@@ -944,7 +1085,9 @@ piix_reset_hard(piix_t *dev)
sff_set_irq_mode(dev->bm[1], 0);
}
- // pclog("piix_reset_hard()\n");
+#ifdef ENABLE_PIIX_LOG
+ piix_log("piix_reset_hard()\n");
+#endif
ide_pri_disable();
ide_sec_disable();
}
@@ -953,10 +1096,9 @@ piix_reset_hard(piix_t *dev)
nvr_at_handler(0, 0x0072, dev->nvr);
nvr_wp_set(0, 0, dev->nvr);
nvr_wp_set(0, 1, dev->nvr);
- } else
- nvr_at_handler(1, 0x0072, dev->nvr);
- nvr_at_handler(1, 0x0074, dev->nvr);
- nvr_at_handler(1, 0x0076, dev->nvr);
+ nvr_at_handler(1, 0x0074, dev->nvr);
+ nvr_at_handler(1, 0x0076, dev->nvr);
+ }
/* Clear all 4 functions' arrays and set their vendor and device ID's. */
for (i = 0; i < 4; i++) {
@@ -968,7 +1110,7 @@ piix_reset_hard(piix_t *dev)
/* Function 0: PCI to ISA Bridge */
fregs = (uint8_t *) dev->regs[0];
- // pclog("PIIX Function 0: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
+ piix_log("PIIX Function 0: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
fregs[0x04] = (dev->type > 0) ? 0x07 : 0x06; /* Check the value for the PB640 PIIX. */
fregs[0x06] = 0x80; fregs[0x07] = 0x02;
fregs[0x08] = (dev->type > 0) ? 0x00 : 0x02; /* Should normal PIIX alos return 0x02? */
@@ -994,7 +1136,7 @@ piix_reset_hard(piix_t *dev)
/* Function 1: IDE */
if (dev->type > 0) {
fregs = (uint8_t *) dev->regs[1];
- // pclog("PIIX Function 1: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
+ piix_log("PIIX Function 1: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
fregs[0x04] = (dev->type > 3) ? 0x05 : 0x07;
fregs[0x06] = 0x80; fregs[0x07] = 0x02;
fregs[0x09] = 0x80;
@@ -1006,7 +1148,7 @@ piix_reset_hard(piix_t *dev)
/* Function 2: USB */
if (dev->type > 2) {
fregs = (uint8_t *) dev->regs[2];
- // pclog("PIIX Function 2: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
+ piix_log("PIIX Function 2: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
fregs[0x04] = 0x05;
fregs[0x06] = 0x80; fregs[0x07] = 0x02;
fregs[0x0a] = 0x03; fregs[0x0b] = 0x0c;
@@ -1022,11 +1164,13 @@ piix_reset_hard(piix_t *dev)
/* Function 3: Power Management */
if (dev->type > 3) {
fregs = (uint8_t *) dev->regs[3];
- // pclog("PIIX Function 3: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
+ piix_log("PIIX Function 3: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
fregs[0x06] = 0x80; fregs[0x07] = 0x02;
fregs[0x0a] = 0x80; fregs[0x0b] = 0x06;
/* NOTE: The Specification Update says this should default to 0x00 and be read-only. */
- // fregs[0x3d] = 0x01;
+#ifdef WRONG_SPEC
+ fregs[0x3d] = 0x01;
+#endif
fregs[0x40] = 0x01;
fregs[0x90] = 0x01;
dev->max_func = 3;
@@ -1063,6 +1207,9 @@ piix_close(void *p)
static void
*piix_init(const device_t *info)
{
+ int i;
+ CPU *cpu_s = &machines[machine].cpu[cpu_manufacturer].cpus[cpu];
+
piix_t *dev = (piix_t *) malloc(sizeof(piix_t));
memset(dev, 0, sizeof(piix_t));
@@ -1071,14 +1218,14 @@ static void
dev->func0_id = info->local >> 16;
dev->pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, piix_read, piix_write, dev);
- // pclog("PIIX%i: Added to slot: %02X\n", dev->type, dev->pci_slot);
+ piix_log("PIIX%i: Added to slot: %02X\n", dev->type, dev->pci_slot);
if (dev->type > 0) { /* PB640's PIIX has no IDE part. */
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
}
- if (dev->type >= 3)
+ if (dev->type > 3)
dev->nvr = device_add(&piix4_nvr_device);
piix_reset_hard(dev);
@@ -1114,65 +1261,57 @@ static void
else if (cpu_busspeed > 0x60000000)
dev->readout_regs[1] |= 0x10;
-#if 0
- switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed) {
- case 75000000:
- dev->readout_regs[1] |= 0x82; /* 50 MHz * 1.5 multiplier */
- break;
- case 90000000:
- dev->readout_regs[1] |= 0x82; /* 60 MHz * 1.5 multiplier */
- break;
- case 100000000:
- if ((dev->readout_regs[1] & 0x30) == 0x10)
- dev->readout_regs[1] |= 0x82; /* 66 MHz * 1.5 multiplier */
- else
- dev->readout_regs[1] |= 0x02; /* 50 MHz * 2.0 multiplier */
- break;
- case 12000000:
- dev->readout_regs[1] |= 0x02; /* 60 MHz * 2.0 multiplier */
- break;
- case 125000000:
- dev->readout_regs[1] |= 0x00; /* 50 MHz * 2.5 multiplier */
- break;
- case 133333333:
- dev->readout_regs[1] |= 0x02; /* 66 MHz * 2.0 multiplier */
- break;
- case 150000000:
- if ((dev->readout_regs[1] & 0x30) == 0x20)
- dev->readout_regs[1] |= 0x00; /* 60 MHz * 2.5 multiplier */
- else
- dev->readout_regs[1] |= 0x80; /* 50 MHz * 3.0 multiplier */
- break;
- case 166666666:
- dev->readout_regs[1] |= 0x00; /* 66 MHz * 2.5 multiplier */
- break;
- case 180000000:
- dev->readout_regs[1] |= 0x80; /* 60 MHz * 3.0 multiplier */
- break;
- case 200000000:
- dev->readout_regs[1] |= 0x80; /* 66 MHz * 3.0 multiplier */
- break;
- }
-#else
- if (cpu_dmulti <= 1.5)
- dev->readout_regs[1] |= 0x82;
- else if ((cpu_dmulti > 1.5) && (cpu_dmulti <= 2.0))
- dev->readout_regs[1] |= 0x02;
- else if ((cpu_dmulti > 2.0) && (cpu_dmulti <= 2.5))
- dev->readout_regs[1] |= 0x00;
- else if (cpu_dmulti > 2.5)
- dev->readout_regs[1] |= 0x80;
-#endif
+ if (cpu_dmulti <= 1.5)
+ dev->readout_regs[1] |= 0x82;
+ else if ((cpu_dmulti > 1.5) && (cpu_dmulti <= 2.0))
+ dev->readout_regs[1] |= 0x02;
+ else if ((cpu_dmulti > 2.0) && (cpu_dmulti <= 2.5))
+ dev->readout_regs[1] |= 0x00;
+ else if (cpu_dmulti > 2.5)
+ dev->readout_regs[1] |= 0x80;
io_sethandler(0x0078, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, dev);
io_sethandler(0x00e0, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, dev);
dev->board_config[0] = 0xff;
/* Register 0x0079: */
+ /* Bit 7: 0 = Keep password, 0 = Clear password. */
/* Bit 6: 0 = NVRAM cleared by jumper, 1 = NVRAM normal. */
/* Bit 5: 0 = CMOS Setup disabled, 1 = CMOS Setup enabled. */
+ /* Bit 4: External CPU clock (Switch 8). */
+ /* Bit 3: External CPU clock (Switch 7). */
+ /* 50 MHz: Switch 7 = Off, Switch 8 = Off. */
+ /* 60 MHz: Switch 7 = On, Switch 8 = Off. */
+ /* 66 MHz: Switch 7 = Off, Switch 8 = On. */
/* Bit 2: 0 = On-board audio absent, 1 = On-board audio present. */
- dev->board_config[1] = 0x64;
+ /* Bit 0: 0 = 1.5x multiplier, 0 = 2x multiplier. */
+ dev->board_config[1] = 0xe0;
+ if ((cpu_s->rspeed == 75000000) && (cpu_busspeed == 50000000))
+ dev->board_config[1] |= 0x01;
+ else if ((cpu_s->rspeed == 90000000) && (cpu_busspeed == 60000000))
+ dev->board_config[1] |= (0x01 | 0x08);
+ else if ((cpu_s->rspeed == 100000000) && (cpu_busspeed == 50000000))
+ dev->board_config[1] |= 0x00;
+ else if ((cpu_s->rspeed == 100000000) && (cpu_busspeed == 66666666))
+ dev->board_config[1] |= (0x01 | 0x10);
+ else if ((cpu_s->rspeed == 120000000) && (cpu_busspeed == 60000000))
+ dev->board_config[1] |= 0x08;
+ else if ((cpu_s->rspeed == 133333333) && (cpu_busspeed == 66666666))
+ dev->board_config[1] |= 0x10;
+ else
+ dev->board_config[1] |= 0x10; /* TODO: how are the overdrive processors configured? */
+
+ smbus_init();
+ dev->smbus.stat = 0;
+ dev->smbus.ctl = 0;
+ dev->smbus.cmd = 0;
+ dev->smbus.addr = 0;
+ dev->smbus.data0 = 0;
+ dev->smbus.data1 = 0;
+ dev->smbus.index = 0;
+ for (i = 0; i < 32; i++)
+ dev->smbus.data[i] = 0;
+ timer_add(&dev->smbus.command_timer, smbus_inter, dev, 0);
return dev;
}
diff --git a/src/keyboard_at.c b/src/keyboard_at.c
index 6ee7fbd50..c81f07bfa 100644
--- a/src/keyboard_at.c
+++ b/src/keyboard_at.c
@@ -2210,7 +2210,8 @@ kbd_read(uint16_t port, void *priv)
atkbd_t *dev = (atkbd_t *)priv;
uint8_t ret = 0xff;
- sub_cycles(ISA_CYCLES(8));
+ if ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_NOREF)
+ sub_cycles(ISA_CYCLES(8));
if (((dev->flags & KBC_VEN_MASK) == KBC_VEN_XI8088) && (port == 0x63))
port = 0x61;
@@ -2622,4 +2623,4 @@ uint8_t
keyboard_at_get_mouse_scan(void)
{
return(mouse_scan ? 0x10 : 0x00);
-}
\ No newline at end of file
+}
diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c
index 9db6c31cc..3e0bfd703 100644
--- a/src/machine/m_at_socket7_s7.c
+++ b/src/machine/m_at_socket7_s7.c
@@ -315,7 +315,7 @@ machine_at_tc430hx_init(const machine_t *model)
if (bios_only || !ret)
return ret;
- machine_at_common_init_ex(model, 2);
+ machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
@@ -526,13 +526,8 @@ machine_at_txp4_init(const machine_t *model)
{
int ret;
-#if 0
- ret = bios_load_linear(L"roms/machines/txp4/5itw003.bin",
+ ret = bios_load_linear(L"roms/machines/txp4/0112L.001",
0x000e0000, 131072, 0);
-#else
- ret = bios_load_linear(L"roms/machines/txp4/TX5I0108.AWD",
- 0x000e0000, 131072, 0);
-#endif
if (bios_only || !ret)
return ret;
@@ -545,7 +540,7 @@ machine_at_txp4_init(const machine_t *model)
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
- pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
+ pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430tx_device);
@@ -605,13 +600,11 @@ machine_at_sp586tx_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
- pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
- pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
- pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
- pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
+ pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
+ pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
+ pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
+ pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
- pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
- pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
diff --git a/src/machine/m_at_socket8.c b/src/machine/m_at_socket8.c
index fa726e881..e0a75b501 100644
--- a/src/machine/m_at_socket8.c
+++ b/src/machine/m_at_socket8.c
@@ -6,7 +6,7 @@
*
* This file is part of the 86Box distribution.
*
- * Implementation of Socket 8 machines.
+ * Implementation of Socket 8 and Slot 1 machines.
*
* Version: @(#)m_at_socket8.c 1.0.0 2019/05/16
*
@@ -34,7 +34,9 @@
#include "piix.h"
#include "sio.h"
#include "sst_flash.h"
+#include "hwm.h"
#include "video.h"
+#include "cpu.h"
#include "machine.h"
@@ -114,7 +116,7 @@ machine_at_6abx3_init(const machine_t *model)
if (bios_only || !ret)
return ret;
- machine_at_common_init(model);
+ machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
@@ -136,6 +138,67 @@ machine_at_6abx3_init(const machine_t *model)
return ret;
}
+
+int
+machine_at_p2bls_init(const machine_t *model)
+{
+ int ret;
+
+ ret = bios_load_linear(L"roms/machines/p2bls/1014ls.003",
+ 0x000c0000, 262144, 0);
+
+ if (bios_only || !ret)
+ return ret;
+
+ machine_at_common_init_ex(model, 2);
+
+ pci_init(PCI_CONFIG_TYPE_1);
+ pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
+ pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3);
+ pci_register_slot(0x07, PCI_CARD_NORMAL, 3, 4, 1, 2);
+ pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
+ pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
+ pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
+ pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
+ pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
+ pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
+ device_add(&i440bx_device);
+ device_add(&piix4_device);
+ device_add(&keyboard_ps2_pci_device);
+ device_add(&w83977ef_device);
+ device_add(&sst_flash_39sf020_device);
+
+ hwm_values_t machine_hwm = {
+ { /* fan speeds */
+ 3000, /* Chassis */
+ 3000, /* CPU */
+ 3000, /* Power */
+ 0
+ }, { /* temperatures */
+ 30, /* MB */
+ 0, /* unused */
+ 27, /* CPU */
+ 0
+ }, { /* voltages (divisors other than 16 = unclear how that number was achieved) */
+ 2800 / 16, /* VCORE (2.8V by default) */
+ 0, /* unused */
+ 3300 / 16, /* +3.3V */
+ 5000 / 27, /* +5V */
+ VDIV(12000, 28, 10) / 16, /* +12V (with 28K/10K resistor divider suggested in the W83781D datasheet) */
+ 12000 / 55, /* -12V */
+ 5000 / 24, /* -5V */
+ 0
+ }
+ };
+ if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2D)
+ machine_hwm.voltages[0] = 2050 / 16; /* set lower VCORE (2.05V) for Deschutes */
+ hwm_set_values(machine_hwm);
+ device_add(&as99127f_device);
+
+ return ret;
+}
+
+
int
machine_at_p6bxt_init(const machine_t *model)
{
@@ -167,6 +230,7 @@ machine_at_p6bxt_init(const machine_t *model)
return ret;
}
+
int
machine_at_63a_init(const machine_t *model)
{
@@ -192,7 +256,7 @@ machine_at_63a_init(const machine_t *model)
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); // Integrated Sound?
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
- device_add(&i440bx_device);
+ device_add(&i440zx_device);
device_add(&piix4_device);
device_add(&w83977tf_device);
device_add(&keyboard_ps2_pci_device);
diff --git a/src/machine/machine.h b/src/machine/machine.h
index ef51fbfb0..c79b11888 100644
--- a/src/machine/machine.h
+++ b/src/machine/machine.h
@@ -306,7 +306,7 @@ extern int machine_at_i440fx_init(const machine_t *);
extern int machine_at_s1668_init(const machine_t *);
extern int machine_at_6abx3_init(const machine_t *);
-
+extern int machine_at_p2bls_init(const machine_t *);
extern int machine_at_p6bxt_init(const machine_t *);
extern int machine_at_63a_init(const machine_t *);
#endif
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index 0f9c1533d..f268ed4e4 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -226,10 +226,10 @@ const machine_t machines[] = {
{ "[Socket 7 VX] Jetway J656VXD", "j656vxd", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_j656vxd_init, NULL },
{ "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
- { "[Socket 7 TX] Acorp 5TX52", "5tx52", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_5tx52_init, NULL },
- { "[Socket 7 TX] ASUS TXP4", "txp4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_txp4_init, NULL },
- { "[Socket 7 TX] Intel YM430TX", "ym430tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_ym430tx_init, NULL },
- { "[Socket 7 TX] San-LI/Superpower SP-586TX","sp586tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_sp586tx_init, NULL },
+ { "[Socket 7 TX] Acorp 5TX52", "5tx52", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_5tx52_init, NULL },
+ { "[Socket 7 TX] ASUS TXP4", "txp4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_txp4_init, NULL },
+ { "[Socket 7 TX] Intel YM430TX", "ym430tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_ym430tx_init, NULL },
+ { "[Socket 7 TX] San-LI/Superpower SP-586TX","sp586tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_sp586tx_init, NULL },
{ "[Super Socket 7] FIC VA-503+", "ficva503p", MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_mvp3_init, NULL },
@@ -238,8 +238,7 @@ const machine_t machines[] = {
{ "[Socket 8 FX] Tyan Titan-Pro ATX", "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL },
{ "[Slot 1 BX] Lucky Star 6ABX3", "6abx3", {{"Intel", cpus_PentiumII}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_6abx3_init, NULL },
-
-
+ { "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
{ "[Socket 370 BX] ECS P6BXT-A+", "p6bxt", {{"Intel", cpus_PGA370}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p6bxt_init, NULL },
{ "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_PGA370}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_63a_init, NULL },
#endif
diff --git a/src/mouse_ps2.c b/src/mouse_ps2.c
index cb7653664..cbd3e5695 100644
--- a/src/mouse_ps2.c
+++ b/src/mouse_ps2.c
@@ -143,6 +143,27 @@ ps2_write(uint8_t val, void *priv)
keyboard_at_adddata_mouse(dev->sample_rate);
break;
+ case 0xeb: /* Get mouse data */
+ keyboard_at_adddata_mouse(0xfa);
+
+ temp = 0;
+ if (dev->x < 0)
+ temp |= 0x10;
+ if (dev->y < 0)
+ temp |= 0x20;
+ if (mouse_buttons & 1)
+ temp |= 1;
+ if (mouse_buttons & 2)
+ temp |= 2;
+ if ((mouse_buttons & 4) && (dev->flags & FLAG_INTELLI))
+ temp |= 4;
+ keyboard_at_adddata_mouse(temp);
+ keyboard_at_adddata_mouse(dev->x & 0xff);
+ keyboard_at_adddata_mouse(dev->y & 0xff);
+ if (dev->flags & FLAG_INTMODE)
+ keyboard_at_adddata_mouse(dev->z);
+ break;
+
case 0xf2: /* read ID */
keyboard_at_adddata_mouse(0xfa);
if (dev->flags & FLAG_INTMODE)
@@ -169,6 +190,7 @@ ps2_write(uint8_t val, void *priv)
case 0xff: /* reset */
dev->mode = MODE_STREAM;
dev->flags &= 0x88;
+ mouse_queue_start = mouse_queue_end = 0;
keyboard_at_adddata_mouse(0xfa);
keyboard_at_adddata_mouse(0xaa);
keyboard_at_adddata_mouse(0x00);
diff --git a/src/pc.c b/src/pc.c
index 5fbf1b3a2..3c67989c0 100644
--- a/src/pc.c
+++ b/src/pc.c
@@ -49,6 +49,7 @@
#include "nvr.h"
#include "machine.h"
#include "bugger.h"
+#include "postcard.h"
#include "isamem.h"
#include "isartc.h"
#include "lpt.h"
@@ -112,6 +113,7 @@ int vid_cga_contrast = 0, /* (C) video */
force_43 = 0; /* (C) video */
int serial_enabled[SERIAL_MAX] = {0,0}, /* (C) enable serial ports */
bugger_enabled = 0, /* (C) enable ISAbugger */
+ postcard_enabled = 0, /* (C) enable POST card */
isamem_type[ISAMEM_MAX] = { 0,0,0,0 }, /* (C) enable ISA mem cards */
isartc_type = 0; /* (C) enable ISA RTC card */
int gfxcard = 0; /* (C) graphics/video card */
@@ -779,7 +781,9 @@ pc_reset_hard_init(void)
/* Needs the status bar... */
if (bugger_enabled)
- device_add(&bugger_device);
+ device_add(&bugger_device);
+ if (postcard_enabled)
+ device_add(&postcard_device);
/* Reset the CPU module. */
resetx86();
diff --git a/src/pci.c b/src/pci.c
index 4e7eb1eba..ada976629 100644
--- a/src/pci.c
+++ b/src/pci.c
@@ -127,7 +127,15 @@ pci_write(uint16_t port, uint8_t val, void *priv)
pci_log("Writing to PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
pci_cards[slot].write(pci_func, pci_index | (port & 3), val, pci_cards[slot].priv);
}
+#ifdef ENABLE_PCI_LOG
+ else
+ pci_log("Writing to empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
+#endif
}
+#ifdef ENABLE_PCI_LOG
+ else
+ pci_log("Writing to unassigned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
+#endif
}
break;
@@ -150,7 +158,15 @@ pci_read(uint16_t port, void *priv)
if (slot != 0xff) {
if (pci_cards[slot].read)
return pci_cards[slot].read(pci_func, pci_index | (port & 3), pci_cards[slot].priv);
+#ifdef ENABLE_PCI_LOG
+ else
+ pci_log("Reading from empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
+#endif
}
+#ifdef ENABLE_PCI_LOG
+ else
+ pci_log("Reading from unasisgned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
+#endif
}
return 0xff;
@@ -237,10 +253,15 @@ pci_type2_write(uint16_t port, uint8_t val, void *priv)
if (slot != 0xff) {
if (pci_cards[slot].write)
pci_cards[slot].write(pci_func, pci_index | (port & 3), val, pci_cards[slot].priv);
+#ifdef ENABLE_PCI_LOG
else
- pclog("Writing to empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
- } else
- pclog("Writing to unassigned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
+ pci_log("Writing to empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
+#endif
+ }
+#ifdef ENABLE_PCI_LOG
+ else
+ pci_log("Writing to unassigned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
+#endif
}
}
}
@@ -265,10 +286,15 @@ pci_type2_read(uint16_t port, void *priv)
if (slot != 0xff) {
if (pci_cards[slot].read)
return pci_cards[slot].read(pci_func, pci_index | (port & 3), pci_cards[slot].priv);
+#ifdef ENABLE_PCI_LOG
else
- pclog("Reading from empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
- } else
- pclog("Reading from unasisgned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
+ pci_log("Reading from empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
+#endif
+ }
+#ifdef ENABLE_PCI_LOG
+ else
+ pci_log("Reading from unasisgned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
+#endif
}
return 0xff;
@@ -649,7 +675,6 @@ void
trc_write(uint16_t port, uint8_t val, void *priv)
{
pci_log("TRC Write: %02X\n", val);
- pclog("[%04X:%08X] TRC Write: %02X\n", CS, cpu_state.pc, val);
if (!(trc_reg & 4) && (val & 4))
trc_reset(val);
diff --git a/src/pic.c b/src/pic.c
index ac13841e6..ad8cc00d5 100644
--- a/src/pic.c
+++ b/src/pic.c
@@ -345,6 +345,35 @@ pic2_write(uint16_t addr, uint8_t val, void *priv)
pic.pend &= ~4;
pic_updatepending();
} else if (!(val & 8)) { /*OCW2*/
+#ifdef ENABLE_PIC_LOG
+ switch ((val >> 5) & 0x07) {
+ case 0x00:
+ pic_log("Rotate in automatic EOI mode (clear)\n");
+ break;
+ case 0x01:
+ pic_log("Non-specific EOI command\n");
+ break;
+ case 0x02:
+ pic_log("No operation\n");
+ break;
+ case 0x03:
+ pic_log("Specific EOI command\n");
+ break;
+ case 0x04:
+ pic_log("Rotate in automatic EOI mode (set)\n");
+ break;
+ case 0x05:
+ pic_log("Rotate on on-specific EOI command\n");
+ break;
+ case 0x06:
+ pic_log("Set priority command\n");
+ break;
+ case 0x07:
+ pic_log("Rotate on specific EOI command\n");
+ break;
+ }
+#endif
+
pic2.ocw2 = val;
if ((val & 0xE0) == 0x60) {
pic2.ins &= ~(1 << (val & 7));
@@ -512,21 +541,32 @@ pic_process_interrupt(PIC* target_pic, int c)
{
uint8_t pending = target_pic->pend & ~target_pic->mask;
int ret = -1;
+ /* TODO: On init, a PIC need to get a pointer to one of these, and rotate as needed
+ if in rotate mode. */
+ /* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
+ int priority_xt[16] = { 7, 6, 5, 4, 3, 2, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1 };
+ int priority_at[16] = { 14, 13, -1, 4, 3, 2, 1, 0, 12, 11, 10, 9, 8, 7, 6, 5 };
+ int i;
int pic_int = c & 7;
int pic_int_num = 1 << pic_int;
int in_service = 0;
- in_service = (target_pic->ins & (pic_int_num - 1)); /* Is anything of higher priority already in service? */
- in_service |= (target_pic->ins & pic_int_num); /* Is the current IRQ already in service? */
if (AT) {
- /* AT-specific stuff. */
- if (c >= 8)
- in_service |= (pic.ins & 0x03); /* IRQ 8 to 15, are IRQ's with higher priorities than the
- cascade IRQ already in service? */
- /* For IRQ 0 to 7, the cascade IRQ's in service bit indicates that one or
- more IRQ's between 8 and 15 are already in service. */
+ for (i = 0; i < 16; i++) {
+ if ((priority_at[i] != -1) && (priority_at[i] >= priority_at[c])) {
+ if (i < 8)
+ in_service |= (pic.ins & (1 << i));
+ else
+ in_service |= (pic2.ins & (1 << i));
+ }
+ }
+ } else {
+ for (i = 0; i < 16; i++) {
+ if ((priority_xt[i] != -1) && (priority_xt[i] >= priority_xt[c]))
+ in_service |= (pic.ins & (1 << i));
+ }
}
if ((pending & pic_int_num) && !in_service) {
diff --git a/src/postcard.c b/src/postcard.c
new file mode 100644
index 000000000..9662d3ae6
--- /dev/null
+++ b/src/postcard.c
@@ -0,0 +1,142 @@
+/*
+ * 86Box A hypervisor and IBM PC system emulator that specializes in
+ * running old operating systems and software designed for IBM
+ * PC systems and compatibles from 1981 through fairly recent
+ * system designs based on the PCI bus.
+ *
+ * This file is part of the 86Box distribution.
+ *
+ * Implementation of a port 80h POST diagnostic card.
+ *
+ * Version: @(#)postcard.c 1.0.0 2020/03/23
+ *
+ * Author: RichardG,
+ * Copyright 2020 RichardG.
+ */
+#include
+#include
+#include
+#include
+#include
+#define HAVE_STDARG_H
+#include "86box.h"
+#include "86box_io.h"
+#include "device.h"
+#include "machine.h"
+#include "plat.h"
+#include "ui.h"
+#include "postcard.h"
+
+
+static uint16_t postcard_port;
+static uint8_t postcard_written;
+static uint8_t postcard_code, postcard_prev_code;
+#define UISTR_LEN 13
+static char postcard_str[UISTR_LEN]; /* UI output string */
+
+
+extern void ui_sb_bugui(char *__str);
+
+
+#ifdef ENABLE_POSTCARD_LOG
+int postcard_do_log = ENABLE_POSTCARD_LOG;
+
+
+static void
+postcard_log(const char *fmt, ...)
+{
+ va_list ap;
+
+ if (postcard_do_log) {
+ va_start(ap, fmt);
+ pclog_ex(fmt, ap);
+ va_end(ap);
+ }
+}
+#else
+int postcard_do_log = 0;
+
+#define postcard_log(fmt, ...)
+#endif
+
+
+static void
+postcard_setui(void)
+{
+ if (!postcard_written)
+ sprintf(postcard_str, "POST: -- --");
+ else if (postcard_written == 1)
+ sprintf(postcard_str, "POST: %02X --", postcard_code);
+ else
+ sprintf(postcard_str, "POST: %02X %02X", postcard_code, postcard_prev_code);
+
+ ui_sb_bugui(postcard_str);
+
+ if (postcard_do_log) {
+ /* log same string sent to the UI */
+ int len = strlen(postcard_str);
+ postcard_str[len + 1] = '\0';
+ postcard_str[len] = '\n';
+ postcard_log(postcard_str);
+ }
+}
+
+
+static void
+postcard_reset(void)
+{
+ postcard_written = 0;
+ postcard_code = postcard_prev_code = 0x00;
+
+ postcard_setui();
+}
+
+
+static void
+postcard_write(uint16_t port, uint8_t val, void *priv)
+{
+ postcard_prev_code = postcard_code;
+ postcard_code = val;
+ if (postcard_written < 2)
+ postcard_written++;
+
+ postcard_setui();
+}
+
+
+static void *
+postcard_init(const device_t *info)
+{
+ postcard_reset();
+
+ if (machines[machine].flags & MACHINE_MCA)
+ postcard_port = 0x680; /* MCA machines */
+ else if (strstr(machines[machine].name, " PS/2 "))
+ postcard_port = 0x90; /* ISA PS/2 machines */
+ else
+ postcard_port = 0x80; /* AT and clone machines */
+ postcard_log("POST card initializing on port %04Xh\n", postcard_port);
+
+ if (postcard_port) io_sethandler(postcard_port, 1,
+ NULL, NULL, NULL, postcard_write, NULL, NULL, NULL);
+
+ return postcard_write;
+}
+
+
+static void
+postcard_close(UNUSED(void *priv))
+{
+ if (postcard_port) io_removehandler(postcard_port, 1,
+ NULL, NULL, NULL, postcard_write, NULL, NULL, NULL);
+}
+
+
+const device_t postcard_device = {
+ "POST Card",
+ DEVICE_ISA,
+ 0,
+ postcard_init, postcard_close, NULL,
+ NULL, NULL, NULL,
+ NULL
+};
diff --git a/src/postcard.h b/src/postcard.h
new file mode 100644
index 000000000..4bfc912f5
--- /dev/null
+++ b/src/postcard.h
@@ -0,0 +1,35 @@
+/*
+ * 86Box A hypervisor and IBM PC system emulator that specializes in
+ * running old operating systems and software designed for IBM
+ * PC systems and compatibles from 1981 through fairly recent
+ * system designs based on the PCI bus.
+ *
+ * This file is part of the 86Box distribution.
+ *
+ * Implementation of a port 80h POST diagnostic card.
+ *
+ * Version: @(#)postcard.c 1.0.0 2020/03/23
+ *
+ * Author: RichardG,
+ * Copyright 2020 RichardG.
+ */
+#ifndef POSTCARD_H
+# define POSTCARD_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Global variables. */
+extern const device_t postcard_device;
+
+
+/* Functions. */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*BUGGER_H*/
diff --git a/src/rom.c b/src/rom.c
index 174ca0479..1853fb3f0 100644
--- a/src/rom.c
+++ b/src/rom.c
@@ -121,7 +121,7 @@ rom_read(uint32_t addr, void *priv)
return 0xff;
if (addr >= (rom->mapping.base + rom->sz))
return 0xff;
- return(rom->rom[addr & rom->mask]);
+ return(rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
@@ -139,7 +139,7 @@ rom_readw(uint32_t addr, void *priv)
return 0xffff;
if (addr >= (rom->mapping.base + rom->sz))
return 0xffff;
- return(*(uint16_t *)&rom->rom[addr & rom->mask]);
+ return(*(uint16_t *)&rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
@@ -157,7 +157,7 @@ rom_readl(uint32_t addr, void *priv)
return 0xffffffff;
if (addr >= (rom->mapping.base + rom->sz))
return 0xffffffff;
- return(*(uint32_t *)&rom->rom[addr & rom->mask]);
+ return(*(uint32_t *)&rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
diff --git a/src/scsi/scsi.c b/src/scsi/scsi.c
index faa7f108d..fb1bdec79 100644
--- a/src/scsi/scsi.c
+++ b/src/scsi/scsi.c
@@ -74,7 +74,8 @@ static SCSI_CARD scsi_cards[] = {
{ "[MCA] BusLogic BT-640A", "bt640a", &buslogic_640a_device, },
{ "[PCI] BusLogic BT-958D", "bt958d", &buslogic_pci_device, },
{ "[PCI] NCR 53C810", "ncr53c810", &ncr53c810_pci_device, },
- //{ "[PCI] NCR 53C825A", "ncr53c825a", &ncr53c825a_pci_device, },
+ { "[PCI] NCR 53C825A", "ncr53c825a", &ncr53c825a_pci_device, },
+ { "[PCI] NCR 53C860", "ncr53c860", &ncr53c860_pci_device, },
{ "[PCI] NCR 53C875", "ncr53c875", &ncr53c875_pci_device, },
{ "[VLB] BusLogic BT-445S", "bt445s", &buslogic_445s_device, },
{ "", "", NULL, },
diff --git a/src/scsi/scsi_cdrom.c b/src/scsi/scsi_cdrom.c
index ccb936901..1c9c1cab4 100644
--- a/src/scsi/scsi_cdrom.c
+++ b/src/scsi/scsi_cdrom.c
@@ -562,6 +562,10 @@ scsi_cdrom_update_request_length(scsi_cdrom_t *dev, int len, int block_len)
case 0x08:
case 0x28:
case 0xa8:
+ /* Round it to the nearest 2048 bytes. */
+ dev->max_transfer_len = (dev->max_transfer_len >> 11) << 11;
+ /* FALLTHROUGH */
+
case 0xb9:
case 0xbe:
/* Make sure total length is not bigger than sum of the lengths of
diff --git a/src/scsi/scsi_ncr53c8xx.c b/src/scsi/scsi_ncr53c8xx.c
index 3161e8f7f..77c9d0143 100644
--- a/src/scsi/scsi_ncr53c8xx.c
+++ b/src/scsi/scsi_ncr53c8xx.c
@@ -49,8 +49,11 @@
#define NCR53C8XX_ROM L"roms/scsi/ncr53c8xx/NCR307.BIN"
+#define HA_ID 7
+
#define CHIP_810 0x01
#define CHIP_825 0x03
+#define CHIP_860 0x06
#define CHIP_875 0x0f
#define NCR_SCNTL0_TRG 0x01
@@ -302,6 +305,10 @@ typedef struct {
uint32_t adder;
pc_timer_t timer;
+
+#ifdef USE_WDTR
+ uint8_t tr_set[16];
+#endif
} ncr53c8xx_t;
@@ -401,7 +408,7 @@ ncr53c8xx_soft_reset(ncr53c8xx_t *dev)
dev->scntl3 = 0;
dev->sstat0 = 0;
dev->sstat1 = 0;
- dev->scid = 7;
+ dev->scid = HA_ID;
dev->sxfer = 0;
dev->socl = 0;
dev->sdid = 0;
@@ -428,13 +435,21 @@ ncr53c8xx_soft_reset(ncr53c8xx_t *dev)
if (dev->chip >= CHIP_825) {
/* This *IS* a wide SCSI controller, so reset all SCSI
devices. */
- for (i = 0; i < 16; i++)
+ for (i = 0; i < 16; i++) {
+#ifdef USE_WDTR
+ dev->tr_set[i] = 0;
+#endif
scsi_device_reset(&scsi_devices[i]);
+ }
} else {
/* This is *NOT* a wide SCSI controller, so do not touch
SCSI devices with ID's >= 8. */
- for (i = 0; i < 8; i++)
+ for (i = 0; i < 8; i++) {
+#ifdef USE_WDTR
+ dev->tr_set[i] = 0;
+#endif
scsi_device_reset(&scsi_devices[i]);
+ }
}
}
@@ -802,9 +817,9 @@ ncr53c8xx_do_wdtr(ncr53c8xx_t *dev, int exponent)
ncr53c8xx_log("Target-initiated WDTR (%08X)\n", dev);
ncr53c8xx_set_phase(dev, PHASE_MI);
dev->msg_action = 4;
- ncr53c8xx_add_msg_byte(dev, 0x01); /* EXTENDED MESSAGE */
- ncr53c8xx_add_msg_byte(dev, 0x02); /* EXTENDED MESSAGE LENGTH */
- ncr53c8xx_add_msg_byte(dev, 0x03); /* WIDE DATA TRANSFER REQUEST */
+ ncr53c8xx_add_msg_byte(dev, 0x01); /* EXTENDED MESSAGE */
+ ncr53c8xx_add_msg_byte(dev, 0x02); /* EXTENDED MESSAGE LENGTH */
+ ncr53c8xx_add_msg_byte(dev, 0x03); /* WIDE DATA TRANSFER REQUEST */
ncr53c8xx_add_msg_byte(dev, exponent); /* TRANSFER WIDTH EXPONENT (16-bit) */
}
#endif
@@ -925,13 +940,14 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
break;
case 3:
ncr53c8xx_log("WDTR (ignored)\n");
+#ifdef USE_WDTR
+ dev->tr_set[dev->sdid] = 1;
+#endif
if (arg > 0x01) {
ncr53c8xx_bad_message(dev, msg);
return;
}
-#ifdef USE_WDTR
ncr53c8xx_set_phase(dev, PHASE_CMD);
-#endif
break;
case 5:
ncr53c8xx_log("PPR (ignored)\n");
@@ -960,9 +976,14 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
scsi_device_command_stop(sd);
ncr53c8xx_disconnect(dev);
break;
+ case 0x0c:
+ /* BUS DEVICE RESET message, reset wide transfer request. */
+#ifdef USE_WDTR
+ dev->tr_set[dev->sdid] = 0;
+#endif
+ /* FALLTHROUGH */
case 0x06:
case 0x0e:
- case 0x0c:
/* clear the current I/O process */
scsi_device_command_stop(sd);
ncr53c8xx_disconnect(dev);
@@ -977,10 +998,11 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
dev->current_lun = msg & 7;
ncr53c8xx_log("Select LUN %d\n", dev->current_lun);
#ifdef USE_WDTR
- ncr53c8xx_do_wdtr(dev, 0x01);
-#else
- ncr53c8xx_set_phase(dev, PHASE_CMD);
+ if ((dev->chip == CHIP_875) && !dev->tr_set[dev->sdid])
+ ncr53c8xx_do_wdtr(dev, 0x01);
+ else
#endif
+ ncr53c8xx_set_phase(dev, PHASE_CMD);
}
break;
}
@@ -2625,6 +2647,7 @@ ncr53c8xx_init(const device_t *info)
ncr53c8xx_pci_bar[0].addr_regs[0] = 1;
ncr53c8xx_pci_bar[1].addr_regs[0] = 0;
dev->chip = info->local;
+
ncr53c8xx_pci_regs[0x04] = 3;
ncr53c8xx_mem_init(dev, 0x0fffff00);
@@ -2632,12 +2655,14 @@ ncr53c8xx_init(const device_t *info)
dev->has_bios = device_get_config_int("bios");
if (dev->has_bios)
- rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
+ rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (dev->chip >= CHIP_825) {
-
if (dev->chip == CHIP_875) {
dev->chip_rev = 0x04;
dev->nvr_path = L"ncr53c875.nvr";
+ } else if (dev->chip == CHIP_860) {
+ dev->chip_rev = 0x04;
+ dev->nvr_path = L"ncr53c860.nvr";
} else {
dev->chip_rev = 0x26;
dev->nvr_path = L"ncr53c825a.nvr";
@@ -2654,8 +2679,8 @@ ncr53c8xx_init(const device_t *info)
ncr53c8xx_bios_disable(dev);
#endif
} else {
- if (dev->has_bios)
- rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
+ /* if (dev->has_bios)
+ rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); */
dev->nvr_path = L"ncr53c810.nvr";
}
@@ -2715,6 +2740,16 @@ const device_t ncr53c825a_pci_device =
ncr53c8xx_pci_config
};
+const device_t ncr53c860_pci_device =
+{
+ "NCR 53c860 (SCSI)",
+ DEVICE_PCI,
+ CHIP_860,
+ ncr53c8xx_init, ncr53c8xx_close, NULL,
+ NULL, NULL, NULL,
+ ncr53c8xx_pci_config
+};
+
const device_t ncr53c875_pci_device =
{
"NCR 53c875 (SCSI)",
diff --git a/src/scsi/scsi_ncr53c8xx.h b/src/scsi/scsi_ncr53c8xx.h
index e50e6d954..b84c91c1c 100644
--- a/src/scsi/scsi_ncr53c8xx.h
+++ b/src/scsi/scsi_ncr53c8xx.h
@@ -27,6 +27,7 @@
extern const device_t ncr53c810_pci_device;
extern const device_t ncr53c825a_pci_device;
+extern const device_t ncr53c860_pci_device;
extern const device_t ncr53c875_pci_device;
diff --git a/src/sio.h b/src/sio.h
index fc6c2bd61..6009545ee 100644
--- a/src/sio.h
+++ b/src/sio.h
@@ -35,6 +35,7 @@ extern const device_t w83877tf_device;
extern const device_t w83877tf_acorp_device;
extern const device_t w83977f_device;
extern const device_t w83977tf_device;
+extern const device_t w83977ef_device;
#endif /*EMU_SIO_H*/
diff --git a/src/sio_um8669f - Cópia.c b/src/sio_um8669f - Cópia.c
deleted file mode 100644
index 4e86b6b3c..000000000
--- a/src/sio_um8669f - Cópia.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*um8669f :
-
- aa to 108 unlocks
- next 108 write is register select (Cx?)
- data read/write to 109
- 55 to 108 locks
-
-C1
-bit 7 - enable PnP registers
-
-PnP registers :
-
-07 - device :
- 0 = FDC
- 1 = COM1
- 2 = COM2
- 3 = LPT1
- 5 = Game port
-30 - enable
-60/61 - addr
-70 - IRQ
-74 - DMA*/
-
-#include
-#include
-#include
-#include
-#include
-#include "86box.h"
-#include "device.h"
-#include "86box_io.h"
-#include "timer.h"
-#include "pci.h"
-#include "lpt.h"
-#include "serial.h"
-#include "fdd.h"
-#include "fdc.h"
-#include "sio.h"
-
-
-#define DEV_FDC 0
-#define DEV_COM1 1
-#define DEV_COM2 2
-#define DEV_LPT1 3
-#define DEV_GAME 5
-
-#define REG_DEVICE 0x07
-#define REG_ENABLE 0x30
-#define REG_ADDRHI 0x60
-#define REG_ADDRLO 0x61
-#define REG_IRQ 0x70
-#define REG_DMA 0x74
-
-
-typedef struct um8669f_t
-{
- int locked, cur_reg_108,
- cur_reg, cur_device,
- pnp_active;
-
- uint8_t regs_108[256];
-
- struct {
- int enable;
- uint16_t addr;
- int irq;
- int dma;
- } dev[8];
-
- fdc_t *fdc;
- serial_t *uart[2];
-} um8669f_t;
-
-
-static void
-um8669f_pnp_write(uint16_t port, uint8_t val, void *priv)
-{
- um8669f_t *dev = (um8669f_t *) priv;
-
- uint8_t valxor = 0;
- uint8_t lpt_irq = 0xff;
-
- if (port == 0x279)
- dev->cur_reg = val;
- else {
- if (dev->cur_reg == REG_DEVICE)
- dev->cur_device = val & 7;
- else {
- switch (dev->cur_reg) {
- case REG_ENABLE:
- valxor = dev->dev[dev->cur_device].enable ^ val;
- dev->dev[dev->cur_device].enable = val;
- break;
- case REG_ADDRLO:
- valxor = (dev->dev[dev->cur_device].addr & 0xff) ^ val;
- dev->dev[dev->cur_device].addr = (dev->dev[dev->cur_device].addr & 0xff00) | val;
- break;
- case REG_ADDRHI:
- valxor = ((dev->dev[dev->cur_device].addr >> 8) & 0xff) ^ val;
- dev->dev[dev->cur_device].addr = (dev->dev[dev->cur_device].addr & 0x00ff) | (val << 8);
- break;
- case REG_IRQ:
- valxor = dev->dev[dev->cur_device].irq ^ val;
- dev->dev[dev->cur_device].irq = val;
- break;
- case REG_DMA:
- valxor = dev->dev[dev->cur_device].dma ^ val;
- dev->dev[dev->cur_device].dma = val;
- break;
- default:
- valxor = 0;
- break;
- }
-
- switch (dev->cur_device) {
- case DEV_FDC:
- if ((dev->cur_reg == REG_ENABLE) && valxor) {
- fdc_remove(dev->fdc);
- if (dev->dev[DEV_FDC].enable & 1)
- fdc_set_base(dev->fdc, 0x03f0);
- }
- break;
- case DEV_COM1:
- if ((dev->cur_reg == REG_ENABLE) && valxor) {
- serial_remove(dev->uart[0]);
- if (dev->dev[DEV_COM1].enable & 1)
- serial_setup(dev->uart[0], dev->dev[DEV_COM1].addr, dev->dev[DEV_COM1].irq);
- }
- break;
- case DEV_COM2:
- if ((dev->cur_reg == REG_ENABLE) && valxor) {
- serial_remove(dev->uart[1]);
- if (dev->dev[DEV_COM2].enable & 1)
- serial_setup(dev->uart[1], dev->dev[DEV_COM2].addr, dev->dev[DEV_COM2].irq);
- }
- break;
- case DEV_LPT1:
- if ((dev->cur_reg == REG_ENABLE) && valxor) {
- lpt1_remove();
- if (dev->dev[DEV_LPT1].enable & 1)
- lpt1_init(dev->dev[DEV_LPT1].addr);
- }
- if (dev->dev[DEV_LPT1].irq <= 15)
- lpt_irq = dev->dev[DEV_LPT1].irq;
- lpt1_irq(lpt_irq);
- break;
- }
- }
- }
-}
-
-
-static uint8_t
-um8669f_pnp_read(uint16_t port, void *priv)
-{
- um8669f_t *dev = (um8669f_t *) priv;
- uint8_t ret = 0xff;
-
- switch (dev->cur_reg) {
- case REG_DEVICE:
- ret = dev->cur_device;
- break;
- case REG_ENABLE:
- ret = dev->dev[dev->cur_device].enable;
- break;
- case REG_ADDRLO:
- ret = dev->dev[dev->cur_device].addr & 0xff;
- break;
- case REG_ADDRHI:
- ret = dev->dev[dev->cur_device].addr >> 8;
- break;
- case REG_IRQ:
- ret = dev->dev[dev->cur_device].irq;
- break;
- case REG_DMA:
- ret = dev->dev[dev->cur_device].dma;
- break;
- }
-
- return ret;
-}
-
-
-void um8669f_write(uint16_t port, uint8_t val, void *priv)
-{
- um8669f_t *dev = (um8669f_t *) priv;
- int new_pnp_active;
-
- if (dev->locked) {
- if ((port == 0x108) && (val == 0xaa))
- dev->locked = 0;
- } else {
- if (port == 0x108) {
- if (val == 0x55)
- dev->locked = 1;
- else
- dev->cur_reg_108 = val;
- } else {
- dev->regs_108[dev->cur_reg_108] = val;
-
- if (dev->cur_reg_108 == 0xc1) {
- new_pnp_active = !!(dev->regs_108[0xc1] & 0x80);
- if (new_pnp_active != dev->pnp_active) {
- if (new_pnp_active) {
- io_sethandler(0x0279, 0x0001,
- NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
- io_sethandler(0x0a79, 0x0001,
- NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
- io_sethandler(0x03e3, 0x0001,
- um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev);
- } else {
- io_removehandler(0x0279, 0x0001,
- NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
- io_removehandler(0x0a79, 0x0001,
- NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
- io_removehandler(0x03e3, 0x0001,
- um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev);
- }
- dev->pnp_active = new_pnp_active;
- }
- }
- }
- }
-}
-
-
-uint8_t um8669f_read(uint16_t port, void *priv)
-{
- um8669f_t *dev = (um8669f_t *) priv;
- uint8_t ret = 0xff;
-
- if (!dev->locked) {
- if (port == 0x108)
- ret = dev->cur_reg_108; /* ??? */
- else
- ret = dev->regs_108[dev->cur_reg_108];
- }
-
- return ret;
-}
-
-
-void
-um8669f_reset(um8669f_t *dev)
-{
- fdc_reset(dev->fdc);
-
- serial_remove(dev->uart[0]);
- serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
-
- serial_remove(dev->uart[1]);
- serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
-
- lpt1_remove();
- lpt1_init(0x378);
-
- if (dev->pnp_active) {
- io_removehandler(0x0279, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
- io_removehandler(0x0a79, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
- io_removehandler(0x03e3, 0x0001, um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev);
- dev->pnp_active = 0;
- }
-
- dev->locked = 1;
-
- dev->dev[DEV_FDC].enable = 1;
- dev->dev[DEV_FDC].addr = 0x03f0;
- dev->dev[DEV_FDC].irq = 6;
- dev->dev[DEV_FDC].dma = 2;
-
- dev->dev[DEV_COM1].enable = 1;
- dev->dev[DEV_COM1].addr = 0x03f8;
- dev->dev[DEV_COM1].irq = 4;
-
- dev->dev[DEV_COM2].enable = 1;
- dev->dev[DEV_COM2].addr = 0x02f8;
- dev->dev[DEV_COM2].irq = 3;
-
- dev->dev[DEV_LPT1].enable = 1;
- dev->dev[DEV_LPT1].addr = 0x0378;
- dev->dev[DEV_LPT1].irq = 7;
-}
-
-
-static void
-um8669f_close(void *priv)
-{
- um8669f_t *dev = (um8669f_t *) priv;
-
- free(dev);
-}
-
-
-static void *
-um8669f_init(const device_t *info)
-{
- um8669f_t *dev = (um8669f_t *) malloc(sizeof(um8669f_t));
- memset(dev, 0, sizeof(um8669f_t));
-
- dev->fdc = device_add(&fdc_at_device);
-
- dev->uart[0] = device_add_inst(&ns16550_device, 1);
- dev->uart[1] = device_add_inst(&ns16550_device, 2);
-
- io_sethandler(0x0108, 0x0002,
- um8669f_read, NULL, NULL, um8669f_write, NULL, NULL, dev);
-
- um8669f_reset(dev);
-
- return dev;
-}
-
-
-const device_t um8669f_device = {
- "UMC UM8669F Super I/O",
- 0,
- 0,
- um8669f_init, um8669f_close, NULL,
- NULL, NULL, NULL,
- NULL
-};
diff --git a/src/sio_um8669f.c b/src/sio_um8669f.c
index 462dfa09b..0d7b21511 100644
--- a/src/sio_um8669f.c
+++ b/src/sio_um8669f.c
@@ -80,8 +80,6 @@ um8669f_pnp_write(uint16_t port, uint8_t val, void *priv)
uint8_t valxor = 0;
uint8_t lpt_irq = 0xff;
- pclog("Write %02X at %04X\n", val, port);
-
if (port == 0x279)
dev->cur_reg = val;
else {
@@ -189,8 +187,6 @@ um8669f_write(uint16_t port, uint8_t val, void *priv)
um8669f_t *dev = (um8669f_t *) priv;
int new_pnp_active;
- pclog("Write %02X at %04X\n", val, port);
-
if (dev->locked) {
if ((port == 0x108) && (val == 0xaa))
dev->locked = 0;
@@ -297,20 +293,6 @@ um8669f_close(void *priv)
}
-void
-um8669f_detect_write(uint16_t port, uint8_t val, void *priv)
-{
- pclog("Write %02X at %04X\n", val, port);
-}
-
-
-uint8_t
-um8669f_detect_read(uint16_t port, void *priv)
-{
- return 0xff;
-}
-
-
static void *
um8669f_init(const device_t *info)
{
@@ -325,15 +307,6 @@ um8669f_init(const device_t *info)
io_sethandler(0x0108, 0x0002,
um8669f_read, NULL, NULL, um8669f_write, NULL, NULL, dev);
- io_sethandler(0x0370, 0x0002,
- um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
- io_sethandler(0x03bd, 0x0001,
- um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
- io_sethandler(0x03bf, 0x0001,
- um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
- io_sethandler(0x03f0, 0x0002,
- um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
-
um8669f_reset(dev);
return dev;
diff --git a/src/sio_w83877f.c b/src/sio_w83877f.c
index dadce5a6c..c9304e7db 100644
--- a/src/sio_w83877f.c
+++ b/src/sio_w83877f.c
@@ -253,7 +253,6 @@ w83877f_write(uint16_t port, uint8_t val, void *priv)
return;
} else if ((port == 0x252) || (port == 0x3f1)) {
if (dev->locked) {
- pclog("dev->locked\n");
if (dev->rw_locked)
return;
if ((dev->cur_reg >= 0x26) && (dev->cur_reg <= 0x27))
diff --git a/src/sio_w83977f.c b/src/sio_w83977f.c
index 286aa074a..770ce2c7a 100644
--- a/src/sio_w83977f.c
+++ b/src/sio_w83977f.c
@@ -88,7 +88,6 @@ w83977f_fdc_handler(w83977f_t *dev)
fdc_remove(dev->fdc);
- pclog("fdc: %02X %02X %04X\n", dev->dev_regs[0][0x00], dev->regs[0x22], io_base);
if ((dev->dev_regs[0][0x00] & 0x01) && (dev->regs[0x22] & 0x01) && (io_base >= 0x100) && (io_base <= 0xff8))
fdc_set_base(dev->fdc, io_base);
@@ -153,8 +152,6 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
uint8_t valxor = 0;
uint8_t ld = dev->regs[7];
- pclog("W83977F Write: %04X %02X\n", port, val);
-
if (index) {
if ((val == 0x87) && !dev->locked) {
if (dev->tries) {
@@ -191,8 +188,8 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
switch (dev->cur_reg) {
case 0x02:
- if (valxor & 0x02)
- softresetx86();
+ /* if (valxor & 0x02)
+ softresetx86(); */
break;
case 0x22:
if (valxor & 0x20)
@@ -205,8 +202,11 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
w83977f_fdc_handler(dev);
break;
case 0x26:
+ if (valxor & 0x40)
+ w83977f_remap(dev);
if (valxor & 0x20)
dev->rw_locked = (val & 0x20) ? 1 : 0;
+ break;
case 0x30:
if (valxor & 0x01) switch (ld) {
case 0x00:
@@ -329,8 +329,6 @@ w83977f_read(uint16_t port, void *priv)
}
}
- pclog("W83977F Read: %04X %02X\n", port, ret);
-
return ret;
}
@@ -344,8 +342,13 @@ w83977f_reset(w83977f_t *dev)
for (i = 0; i < 256; i++)
memset(dev->dev_regs[i], 0, 208);
- dev->regs[0x20] = 0x97;
- dev->regs[0x21] = dev->type ? 0x73 : 0x71;
+ if (dev->type < 2) {
+ dev->regs[0x20] = 0x97;
+ dev->regs[0x21] = dev->type ? 0x73 : 0x71;
+ } else {
+ dev->regs[0x20] = 0x52;
+ dev->regs[0x21] = 0xf0;
+ }
dev->regs[0x22] = 0xff;
dev->regs[0x24] = dev->type ? 0x84 : 0xa4;
@@ -368,9 +371,9 @@ w83977f_reset(w83977f_t *dev)
dev->dev_regs[1][0x30] = 0x03; dev->dev_regs[1][0x31] = 0x78;
dev->dev_regs[1][0x40] = 0x07;
if (!dev->type)
- dev->dev_regs[1][0x41] = 0x02; /* Read-only */
+ dev->dev_regs[1][0x41] = 0x01 /*0x02*/; /* Read-only */
dev->dev_regs[1][0x44] = 0x04;
- dev->dev_regs[1][0xc0] = 0x3c; /* The datasheet says default is 3f, but also default is priner mode. */
+ dev->dev_regs[1][0xc0] = 0x3c; /* The datasheet says default is 3f, but also default is printer mode. */
/* Logical Device 2 (UART A) */
dev->dev_regs[2][0x00] = 0x01;
@@ -404,6 +407,7 @@ w83977f_reset(w83977f_t *dev)
if (!dev->type)
dev->dev_regs[5][0x01] = 0x02;
dev->dev_regs[5][0x30] = 0x00; dev->dev_regs[5][0x31] = 0x60;
+ dev->dev_regs[5][0x32] = 0x00; dev->dev_regs[5][0x33] = 0x64;
dev->dev_regs[5][0x40] = 0x01;
if (!dev->type)
dev->dev_regs[5][0x41] = 0x02; /* Read-only */
@@ -448,10 +452,12 @@ w83977f_reset(w83977f_t *dev)
/* Logical Device 9 (Auxiliary I/O Part III) */
if (dev->type) {
- dev->dev_regs[7][0xb0] = 0x01; dev->dev_regs[7][0xb1] = 0x01;
- dev->dev_regs[7][0xb2] = 0x01; dev->dev_regs[7][0xb3] = 0x01;
- dev->dev_regs[7][0xb4] = 0x01; dev->dev_regs[7][0xb5] = 0x01;
- dev->dev_regs[7][0xb6] = 0x01; dev->dev_regs[7][0xb7] = 0x01;
+ dev->dev_regs[9][0xb0] = 0x01; dev->dev_regs[9][0xb1] = 0x01;
+ dev->dev_regs[9][0xb2] = 0x01; dev->dev_regs[9][0xb3] = 0x01;
+ dev->dev_regs[9][0xb4] = 0x01; dev->dev_regs[9][0xb5] = 0x01;
+ dev->dev_regs[9][0xb6] = 0x01; dev->dev_regs[9][0xb7] = 0x01;
+
+ dev->dev_regs[10][0xc0] = 0x8f;
}
fdc_reset(dev->fdc);
@@ -517,3 +523,13 @@ const device_t w83977tf_device = {
NULL, NULL, NULL,
NULL
};
+
+
+const device_t w83977ef_device = {
+ "Winbond W83977TF Super I/O",
+ 0,
+ 2,
+ w83977f_init, w83977f_close, NULL,
+ NULL, NULL, NULL,
+ NULL
+};
diff --git a/src/smbus.c b/src/smbus.c
new file mode 100644
index 000000000..171d4fad5
--- /dev/null
+++ b/src/smbus.c
@@ -0,0 +1,410 @@
+/*
+ * 86Box A hypervisor and IBM PC system emulator that specializes in
+ * running old operating systems and software designed for IBM
+ * PC systems and compatibles from 1981 through fairly recent
+ * system designs based on the PCI bus.
+ *
+ * This file is part of the 86Box distribution.
+ *
+ * Implement SMBus (System Management Bus) and its operations.
+ *
+ * Version: @(#)smbus.c 1.0.0 2020/03/21
+ *
+ * Authors: RichardG,
+ *
+ * Copyright 2020 RichardG.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#define HAVE_STDARG_H
+#include "86box.h"
+#include "smbus.h"
+
+
+#define NADDRS 128 /* SMBus supports 128 addresses */
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+
+
+typedef struct _smbus_ {
+ uint8_t (*read_byte)(uint8_t addr, void *priv);
+ uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv);
+ uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv);
+ uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv);
+
+ void (*write_byte)(uint8_t addr, uint8_t val, void *priv);
+ void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv);
+ void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv);
+ void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv);
+
+ void *priv;
+
+ struct _smbus_ *prev, *next;
+} smbus_t;
+
+int smbus_initialized = 0;
+smbus_t *smbus[NADDRS], *smbus_last[NADDRS];
+
+#define ENABLE_SMBUS_LOG 1
+#ifdef ENABLE_SMBUS_LOG
+int smbus_do_log = ENABLE_SMBUS_LOG;
+
+
+static void
+smbus_log(const char *fmt, ...)
+{
+ va_list ap;
+
+ if (smbus_do_log) {
+ va_start(ap, fmt);
+ pclog_ex(fmt, ap);
+ va_end(ap);
+ }
+}
+#else
+#define smbus_log(fmt, ...)
+#endif
+
+
+#ifdef ENABLE_SMBUS_LOG
+static uint8_t smbus_null_read_byte(uint8_t addr, void *priv) { smbus_log("SMBus: read_byte(%02x)\n", addr); return(0xff); }
+static uint8_t smbus_null_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv) { smbus_log("SMBus: read_byte_cmd(%02x, %02x)\n", addr, cmd); return(0xff); }
+static uint16_t smbus_null_read_word_cmd(uint8_t addr, uint8_t cmd, void *priv) { smbus_log("SMBus: read_word_cmd(%02x, %02x)\n", addr, cmd); return(0xffff); }
+static uint8_t smbus_null_read_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv) { smbus_log("SMBus: read_block_cmd(%02x, %02x)\n", addr, cmd); return(0x00); };
+static void smbus_null_write_byte(uint8_t addr, uint8_t val, void *priv) { smbus_log("SMBus: write_byte(%02x, %02x)\n", addr, val); }
+static void smbus_null_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val, void *priv) { smbus_log("SMBus: write_byte_cmd(%02x, %02x, %02x)\n", addr, cmd, val); }
+static void smbus_null_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val, void *priv) { smbus_log("SMBus: write_word_cmd(%02x, %02x, %04x)\n", addr, cmd, val); }
+static void smbus_null_write_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv) { smbus_log("SMBus: write_block_cmd(%02x, %02x, %02x)\n", addr, cmd, len); }
+#endif
+
+
+void
+smbus_init(void)
+{
+ int c;
+ smbus_t *p, *q;
+
+ if (!smbus_initialized) {
+ for (c=0; cprev;
+ free(p);
+ p = q;
+ }
+ p = NULL;
+ }
+
+#ifdef ENABLE_SMBUS_LOG
+ /* smbus[c] should be the only handler, pointing at the NULL catch handler. */
+ p = (smbus_t *) malloc(sizeof(smbus_t));
+ memset(p, 0, sizeof(smbus_t));
+ smbus[c] = smbus_last[c] = p;
+ p->next = NULL;
+ p->prev = NULL;
+ p->read_byte = smbus_null_read_byte;
+ p->read_byte_cmd = smbus_null_read_byte_cmd;
+ p->read_word_cmd = smbus_null_read_word_cmd;
+ p->read_block_cmd = smbus_null_read_block_cmd;
+ p->write_byte = smbus_null_write_byte;
+ p->write_byte_cmd = smbus_null_write_byte_cmd;
+ p->write_word_cmd = smbus_null_write_word_cmd;
+ p->write_block_cmd = smbus_null_write_block_cmd;
+ p->priv = NULL;
+#else
+ /* smbus[c] should be NULL. */
+ smbus[c] = smbus_last[c] = NULL;
+#endif
+ }
+}
+
+
+void
+smbus_sethandler(uint8_t base, int size,
+ uint8_t (*read_byte)(uint8_t addr, void *priv),
+ uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
+ void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
+ void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
+ void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
+ void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
+ void *priv)
+{
+ int c;
+ smbus_t *p, *q = NULL;
+
+ for (c = 0; c < size; c++) {
+ p = smbus_last[base + c];
+ q = (smbus_t *) malloc(sizeof(smbus_t));
+ memset(q, 0, sizeof(smbus_t));
+ if (p) {
+ p->next = q;
+ q->prev = p;
+ } else {
+ smbus[base + c] = q;
+ q->prev = NULL;
+ }
+
+ q->read_byte = read_byte;
+ q->read_byte_cmd = read_byte_cmd;
+ q->read_word_cmd = read_word_cmd;
+ q->read_block_cmd = read_block_cmd;
+
+ q->write_byte = write_byte;
+ q->write_byte_cmd = write_byte_cmd;
+ q->write_word_cmd = write_word_cmd;
+ q->write_block_cmd = write_block_cmd;
+
+ q->priv = priv;
+ q->next = NULL;
+
+ smbus_last[base + c] = q;
+ }
+}
+
+
+void
+smbus_removehandler(uint8_t base, int size,
+ uint8_t (*read_byte)(uint8_t addr, void *priv),
+ uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
+ void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
+ void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
+ void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
+ void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
+ void *priv)
+{
+ int c;
+ smbus_t *p;
+
+ for (c = 0; c < size; c++) {
+ p = smbus[base + c];
+ if (!p)
+ continue;
+ while(p) {
+ if ((p->read_byte == read_byte) && (p->read_byte_cmd == read_byte_cmd) &&
+ (p->read_word_cmd == read_word_cmd) && (p->read_block_cmd == read_block_cmd) &&
+ (p->write_byte == write_byte) && (p->write_byte_cmd == write_byte_cmd) &&
+ (p->write_word_cmd == write_word_cmd) && (p->write_block_cmd == write_block_cmd) &&
+ (p->priv == priv)) {
+ if (p->prev)
+ p->prev->next = p->next;
+ else
+ smbus[base + c] = p->next;
+ if (p->next)
+ p->next->prev = p->prev;
+ else
+ smbus_last[base + c] = p->prev;
+ free(p);
+ p = NULL;
+ break;
+ }
+ p = p->next;
+ }
+ }
+}
+
+
+void
+smbus_handler(int set, uint8_t base, int size,
+ uint8_t (*read_byte)(uint8_t addr, void *priv),
+ uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
+ void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
+ void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
+ void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
+ void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
+ void *priv)
+{
+ if (set)
+ smbus_sethandler(base, size, read_byte, read_byte_cmd, read_word_cmd, read_block_cmd, write_byte, write_byte_cmd, write_word_cmd, write_block_cmd, priv);
+ else
+ smbus_removehandler(base, size, read_byte, read_byte_cmd, read_word_cmd, read_block_cmd, write_byte, write_byte_cmd, write_word_cmd, write_block_cmd, priv);
+}
+
+
+uint8_t
+smbus_has_device(uint8_t addr)
+{
+ return(!!smbus[addr]);
+}
+
+
+uint8_t
+smbus_read_byte(uint8_t addr)
+{
+ uint8_t ret = 0xff;
+ smbus_t *p;
+ int found = 0;
+
+ p = smbus[addr];
+ if (p) {
+ while(p) {
+ if (p->read_byte) {
+ ret &= p->read_byte(addr, p->priv);
+ found++;
+ }
+ p = p->next;
+ }
+ }
+
+ return(ret);
+}
+
+uint8_t
+smbus_read_byte_cmd(uint8_t addr, uint8_t cmd)
+{
+ uint8_t ret = 0xff;
+ smbus_t *p;
+ int found = 0;
+
+ p = smbus[addr];
+ if (p) {
+ while(p) {
+ if (p->read_byte_cmd) {
+ ret &= p->read_byte_cmd(addr, cmd, p->priv);
+ found++;
+ }
+ p = p->next;
+ }
+ }
+
+ return(ret);
+}
+
+uint16_t
+smbus_read_word_cmd(uint8_t addr, uint8_t cmd)
+{
+ uint16_t ret = 0xffff;
+ smbus_t *p;
+ int found = 0;
+
+ p = smbus[addr];
+ if (p) {
+ while(p) {
+ if (p->read_word_cmd) {
+ ret &= p->read_word_cmd(addr, cmd, p->priv);
+ found++;
+ }
+ p = p->next;
+ }
+ }
+
+ return(ret);
+}
+
+uint8_t
+smbus_read_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data)
+{
+ uint8_t ret = 0;
+ smbus_t *p;
+ int found = 0;
+
+ p = smbus[addr];
+ if (p) {
+ while(p) {
+ if (p->read_block_cmd) {
+ ret = MAX(ret, p->read_block_cmd(addr, cmd, data, p->priv));
+ found++;
+ }
+ p = p->next;
+ }
+ }
+
+ return(ret);
+}
+
+
+void
+smbus_write_byte(uint8_t addr, uint8_t val)
+{
+ smbus_t *p;
+ int found = 0;
+
+ if (smbus[addr]) {
+ p = smbus[addr];
+ while(p) {
+ if (p->write_byte) {
+ p->write_byte(addr, val, p->priv);
+ found++;
+ }
+ p = p->next;
+ }
+ }
+
+ return;
+}
+
+void
+smbus_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val)
+{
+ smbus_t *p;
+ int found = 0;
+
+ if (smbus[addr]) {
+ p = smbus[addr];
+ while(p) {
+ if (p->write_byte_cmd) {
+ p->write_byte_cmd(addr, cmd, val, p->priv);
+ found++;
+ }
+ p = p->next;
+ }
+ }
+
+ return;
+}
+
+void
+smbus_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val)
+{
+ smbus_t *p;
+ int found = 0;
+
+ if (smbus[addr]) {
+ p = smbus[addr];
+ while(p) {
+ if (p->write_word_cmd) {
+ p->write_word_cmd(addr, cmd, val, p->priv);
+ found++;
+ }
+ p = p->next;
+ }
+ }
+
+ return;
+}
+
+void
+smbus_write_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len)
+{
+ smbus_t *p;
+ int found = 0;
+
+ p = smbus[addr];
+ if (p) {
+ while(p) {
+ if (p->write_block_cmd) {
+ p->write_block_cmd(addr, cmd, data, len, p->priv);
+ found++;
+ }
+ p = p->next;
+ }
+ }
+
+ return;
+}
diff --git a/src/smbus.h b/src/smbus.h
new file mode 100644
index 000000000..a4fec4a5c
--- /dev/null
+++ b/src/smbus.h
@@ -0,0 +1,67 @@
+/*
+ * 86Box A hypervisor and IBM PC system emulator that specializes in
+ * running old operating systems and software designed for IBM
+ * PC systems and compatibles from 1981 through fairly recent
+ * system designs based on the PCI bus.
+ *
+ * This file is part of the 86Box distribution.
+ *
+ * Definitions for the SMBus handler.
+ *
+ * Version: @(#)smbus.h 1.0.0 2020/03/21
+ *
+ * Authors: RichardG,
+ *
+ * Copyright 2020 RichardG.
+ */
+#ifndef EMU_SMBUS_H
+# define EMU_SMBUS_H
+
+
+extern void smbus_init(void);
+
+extern void smbus_sethandler(uint8_t base, int size,
+ uint8_t (*read_byte)(uint8_t addr, void *priv),
+ uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
+ void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
+ void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
+ void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
+ void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
+ void *priv);
+
+extern void smbus_removehandler(uint8_t base, int size,
+ uint8_t (*read_byte)(uint8_t addr, void *priv),
+ uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
+ void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
+ void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
+ void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
+ void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
+ void *priv);
+
+extern void smbus_handler(int set, uint8_t base, int size,
+ uint8_t (*read_byte)(uint8_t addr, void *priv),
+ uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
+ uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
+ void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
+ void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
+ void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
+ void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
+ void *priv);
+
+extern uint8_t smbus_has_device(uint8_t addr);
+extern uint8_t smbus_read_byte(uint8_t addr);
+extern uint8_t smbus_read_byte_cmd(uint8_t addr, uint8_t cmd);
+extern uint16_t smbus_read_word_cmd(uint8_t addr, uint8_t cmd);
+extern uint8_t smbus_read_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data);
+extern void smbus_write_byte(uint8_t addr, uint8_t val);
+extern void smbus_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val);
+extern void smbus_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val);
+extern void smbus_write_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len);
+
+
+#endif /*EMU_SMBUS_H*/
diff --git a/src/sound/snd_opl_backend.c b/src/sound/snd_opl_backend.c
index b2673fae0..2e8ae1df6 100644
--- a/src/sound/snd_opl_backend.c
+++ b/src/sound/snd_opl_backend.c
@@ -134,21 +134,11 @@ opl_write(int nr, uint16_t addr, uint8_t val)
uint8_t
opl_read(int nr, uint16_t addr)
{
- FILE *f;
- int i;
-
if (!(addr & 1))
return (opl[nr].status & opl[nr].status_mask) | (opl[nr].is_opl3 ? 0 : 0x06);
- if (opl[nr].is_opl3 && ((addr & 3) == 3)) {
- f = fopen("c:\\emu_dev\\awe32seg.dmp", "wb");
- for (i = 0; i < 65536; i++)
- fputc(readmembl(cs + i), f);
- fclose(f);
-
- fatal("[%04X:%08X] (%08X) Read 00 from %04X\n", CS, cpu_state.pc, cs + cpu_state.pc, addr);
+ if (opl[nr].is_opl3 && ((addr & 3) == 3))
return 0x00;
- }
return opl[nr].is_opl3 ? 0 : 0xff;
}
diff --git a/src/sound/snd_sb.c b/src/sound/snd_sb.c
index 0c5a11d2d..25ed6b87d 100644
--- a/src/sound/snd_sb.c
+++ b/src/sound/snd_sb.c
@@ -679,13 +679,9 @@ void sb_ct1745_mixer_write(uint16_t addr, uint8_t val, void *p)
sb_ct1745_mixer_t *mixer = &sb->mixer_sb16;
if (!(addr & 1))
- {
- pclog("CT1745: write IDX : %02X\n", val);
mixer->index = val;
- }
else
{
- pclog("CT1745: write REG%02X: %02X\n", mixer->index, val);
// TODO: and this? 001h:
/*DESCRIPTION
Contains previously selected register value. Mixer Data Register value
@@ -868,10 +864,8 @@ uint8_t sb_ct1745_mixer_read(uint16_t addr, void *p)
sb_ct1745_mixer_t *mixer = &sb->mixer_sb16;
uint8_t temp, ret = 0xff;
- if (!(addr & 1)) {
+ if (!(addr & 1))
ret = mixer->index;
- pclog("CT1745: read IDX : %02X\n", ret);
- }
sb_log("sb_ct1745: received register READ: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]);
@@ -1008,7 +1002,6 @@ uint8_t sb_ct1745_mixer_read(uint16_t addr, void *p)
break;
}
- pclog("CT1745: read REG%02X: %02X\n", mixer->index, ret);
return ret;
}
diff --git a/src/sst_flash.c b/src/sst_flash.c
index 724a3e724..7cb3e3292 100644
--- a/src/sst_flash.c
+++ b/src/sst_flash.c
@@ -34,18 +34,20 @@
typedef struct sst_t
{
- uint8_t id, is_39, page_bytes, pad;
+ uint8_t id, is_39, page_bytes, sdp;
int command_state, id_mode,
- erase, dirty;
+ dirty;
- uint32_t size, mask;
+ uint32_t size, mask,
+ page_mask, page_base;
+ uint8_t page_buffer[128];
uint8_t *array;
mem_mapping_t mapping[8], mapping_h[8];
- pc_timer_t page_load_timer;
+ pc_timer_t page_write_timer;
} sst_t;
@@ -53,6 +55,7 @@ static wchar_t flash_path[1024];
#define SST_CHIP_ERASE 0x10 /* Both 29 and 39, 6th cycle */
+#define SST_SDP_DISABLE 0x20 /* Only 29, Software data protect disable and write - treat as write */
#define SST_SECTOR_ERASE 0x30 /* Only 39, 6th cycle */
#define SST_SET_ID_MODE_ALT 0x60 /* Only 29, 6th cycle */
#define SST_ERASE 0x80 /* Both 29 and 39 */
@@ -74,63 +77,82 @@ static wchar_t flash_path[1024];
static void
-sst_new_command(sst_t *dev, uint8_t val)
+sst_sector_erase(sst_t *dev, uint32_t addr)
{
- switch (val) {
+ memset(&dev->array[addr & (dev->mask & ~0xfff)], 0xff, 4096);
+ dev->dirty = 1;
+}
+
+
+static void
+sst_new_command(sst_t *dev, uint32_t addr, uint8_t val)
+{
+ if (dev->command_state == 5) switch (val) {
case SST_CHIP_ERASE:
- if (dev->erase)
- memset(dev->array, 0xff, 0x20000);
+ memset(dev->array, 0xff, 0x20000);
dev->command_state = 0;
- dev->erase = 0;
break;
- case SST_ERASE:
+ case SST_SDP_DISABLE:
+ if (!dev->is_39)
+ dev->sdp = 0;
dev->command_state = 0;
- dev->erase = 1;
break;
- case SST_SET_ID_MODE:
- if (!dev->id_mode)
- dev->id_mode = 1;
+ case SST_SECTOR_ERASE:
+ if (dev->is_39)
+ sst_sector_erase(dev, addr);
dev->command_state = 0;
- dev->erase = 0;
break;
case SST_SET_ID_MODE_ALT:
- if (!dev->is_39 && dev->erase && !dev->id_mode)
- dev->id_mode = 1;
+ dev->id_mode = 1;
dev->command_state = 0;
- dev->erase = 0;
- break;
-
- case SST_BYTE_PROGRAM:
- dev->command_state = 3;
- if (!dev->is_39) {
- dev->page_bytes = 0;
- timer_set_delay_u64(&dev->page_load_timer, 100 * TIMER_USEC);
- }
- dev->erase = 0;
- break;
-
- case SST_CLEAR_ID_MODE:
- if (dev->id_mode)
- dev->id_mode = 0;
- dev->command_state = 0;
- dev->erase = 0;
break;
default:
dev->command_state = 0;
- dev->erase = 0;
+ break;
+ } else switch (val) {
+ case SST_ERASE:
+ dev->command_state = 3;
+ break;
+
+ case SST_SET_ID_MODE:
+ dev->id_mode = 1;
+ dev->command_state = 0;
+ break;
+
+ case SST_BYTE_PROGRAM:
+ if (!dev->is_39) {
+ memset(dev->page_buffer, 0xff, 128);
+ dev->page_bytes = 0;
+ timer_on_auto(&dev->page_write_timer, 210.0);
+ }
+ dev->command_state = 6;
+ break;
+
+ case SST_CLEAR_ID_MODE:
+ dev->id_mode = 0;
+ dev->command_state = 0;
+ break;
+
+ default:
+ dev->command_state = 0;
+ break;
}
}
static void
-sst_sector_erase(sst_t *dev, uint32_t addr)
+sst_page_write(void *priv)
{
- memset(&dev->array[addr & (dev->mask & ~0xfff)], 0xff, 4096);
+ sst_t *dev = (sst_t *) priv;
+
+ memcpy(&(dev->array[dev->page_base]), dev->page_buffer, 128);
dev->dirty = 1;
+ dev->page_bytes = 0;
+ dev->command_state = 0;
}
@@ -148,6 +170,19 @@ sst_read_id(uint32_t addr, void *p)
}
+static void
+sst_buf_write(sst_t *dev, uint32_t addr, uint8_t val)
+{
+ dev->page_buffer[addr & 0x0000007f] = val;
+ timer_disable(&dev->page_write_timer);
+ dev->page_bytes++;
+ if (dev->page_bytes >= 128)
+ sst_page_write(dev);
+ else
+ timer_set_delay_u64(&dev->page_write_timer, 210 * TIMER_USEC);
+}
+
+
static void
sst_write(uint32_t addr, uint8_t val, void *p)
{
@@ -155,44 +190,55 @@ sst_write(uint32_t addr, uint8_t val, void *p)
switch (dev->command_state) {
case 0:
- /* 1st Bus Write Cycle */
- if ((val == 0xf0) && dev->is_39) {
+ case 3:
+ /* 1st and 4th Bus Write Cycle */
+ if ((val == 0xf0) && dev->is_39 && (dev->command_state == 0)) {
if (dev->id_mode)
dev->id_mode = 0;
- } else if ((addr & 0xffff) == 0x5555 && val == 0xaa)
- dev->command_state = 1;
- else
dev->command_state = 0;
+ } else if (((addr & 0x7fff) == 0x5555) && (val == 0xaa))
+ dev->command_state++;
+ else {
+ if (!dev->is_39 && !dev->sdp && (dev->command_state == 0)) {
+ /* 29 series, software data protection off, start loading the page. */
+ dev->page_base = addr & dev->page_mask; /* First byte, A7 onwards of its address are the page mask. */
+ dev->command_state = 7;
+ sst_buf_write(dev, addr, val);
+ }
+ dev->command_state = 0;
+ }
break;
case 1:
- /* 2nd Bus Write Cycle */
- if ((addr & 0xffff) == 0x2aaa && val == 0x55)
- dev->command_state = 2;
+ case 4:
+ /* 2nd and 5th Bus Write Cycle */
+ if (((addr & 0x7fff) == 0x2aaa) && (val == 0x55))
+ dev->command_state++;
else
dev->command_state = 0;
break;
case 2:
- /* 3rd Bus Write Cycle */
- if ((addr & 0xffff) == 0x5555)
- sst_new_command(dev, val);
- else if (dev->is_39 && (val == SST_SECTOR_ERASE) && dev->erase) {
- sst_sector_erase(dev, addr);
- dev->command_state = 0;
- } else
+ case 5:
+ /* 3rd and 6th Bus Write Cycle */
+ if ((addr & 0x7fff) == 0x5555)
+ sst_new_command(dev, addr, val);
+ else
dev->command_state = 0;
break;
- case 3:
- dev->array[addr & dev->mask] = val;
- if (!dev->is_39) {
- timer_disable(&dev->page_load_timer);
- if (dev->page_bytes == 0)
- timer_set_delay_u64(&dev->page_load_timer, 100 * TIMER_USEC);
- else
- timer_set_delay_u64(&dev->page_load_timer, 200 * TIMER_USEC);
- dev->page_bytes++;
- } else
+ case 6:
+ /* Page Load Cycle (29) / Data Write Cycle (39SF) */
+ if (dev->is_39) {
+ dev->array[addr & dev->mask] = val;
dev->command_state = 0;
- dev->dirty = 1;
+ dev->dirty = 1;
+ } else {
+ dev->page_base = addr & dev->page_mask; /* First byte, A7 onwards of its address are the page mask. */
+ dev->command_state++;
+ sst_buf_write(dev, addr, val);
+ }
+ break;
+ case 7:
+ if (!dev->is_39 && ((addr & dev->page_mask) == dev->page_base))
+ sst_buf_write(dev, addr, val);
break;
}
}
@@ -255,15 +301,6 @@ sst_readl(uint32_t addr, void *p)
}
-static void
-sst_page_load(void *priv)
-{
- sst_t *dev = (sst_t *) priv;
-
- dev->command_state = 0;
-}
-
-
static void
sst_add_mappings(sst_t *dev)
{
@@ -331,6 +368,8 @@ sst_init(const device_t *info)
else
dev->size = 0x20000;
dev->mask = dev->size - 1;
+ dev->page_mask = dev->mask & 0xffffff80; /* Filter out A0-A6. */
+ dev->sdp = 1;
sst_add_mappings(dev);
@@ -339,13 +378,14 @@ sst_init(const device_t *info)
if (fread(&(dev->array[0x00000]), 1, dev->size, f) != dev->size)
fatal("Less than %i bytes read from the SST Flash ROM file\n", dev->size);
fclose(f);
- }
+ } else
+ dev->dirty = 1; /* It is by definition dirty on creation. */
free(flash_name);
free(machine_name);
if (!dev->is_39)
- timer_add(&dev->page_load_timer, sst_page_load, dev, 0);
+ timer_add(&dev->page_write_timer, sst_page_write, dev, 0);
return dev;
}
@@ -357,9 +397,11 @@ sst_close(void *p)
FILE *f;
sst_t *dev = (sst_t *)p;
- f = nvr_fopen(flash_path, L"wb");
- fwrite(&(dev->array[0x00000]), dev->size, 1, f);
- fclose(f);
+ if (dev->dirty) {
+ f = nvr_fopen(flash_path, L"wb");
+ fwrite(&(dev->array[0x00000]), dev->size, 1, f);
+ fclose(f);
+ }
free(dev->array);
dev->array = NULL;
diff --git a/src/video/86Box.exe b/src/video/86Box.exe
deleted file mode 100644
index 56b0faadc..000000000
Binary files a/src/video/86Box.exe and /dev/null differ
diff --git a/src/video/vid_mga - Cópia.c b/src/video/vid_mga - Cópia.c
deleted file mode 100644
index 4c26b8676..000000000
--- a/src/video/vid_mga - Cópia.c
+++ /dev/null
@@ -1,4876 +0,0 @@
-/*
- * 86Box A hypervisor and IBM PC system emulator that specializes in
- * running old operating systems and software designed for IBM
- * PC systems and compatibles from 1981 through fairly recent
- * system designs based on the PCI bus.
- *
- * This file is part of the 86Box distribution.
- *
- * Matrox MGA graphics card emulation.
- *
- * Version: @(#)vid_mga.c 1.0.3 2020/01/20
- *
- * Author: Sarah Walker,
- * Copyright 2008-2020 Sarah Walker.
- */
-#include
-#include
-#include
-#include
-#include
-#include "86box.h"
-#include "86box_io.h"
-#include "timer.h"
-#include "mem.h"
-#include "pci.h"
-#include "rom.h"
-#include "device.h"
-#include "plat.h"
-#include "video.h"
-#include "vid_svga.h"
-#include "vid_svga_render.h"
-
-
-#define ROM_MYSTIQUE L"roms/video/matrox/MYSTIQUE.VBI"
-#define ROM_MYSTIQUE_220 L"roms/video/matrox/Myst220_66-99mhz.vbi"
-
-#define FIFO_SIZE 65536
-#define FIFO_MASK (FIFO_SIZE - 1)
-#define FIFO_ENTRY_SIZE (1 << 31)
-#define FIFO_THRESHOLD 0xe000
-
-#define WAKE_DELAY (100 * TIMER_USEC) /* 100us */
-
-#define FIFO_ENTRIES (mystique->fifo_write_idx - mystique->fifo_read_idx)
-#define FIFO_FULL ((mystique->fifo_write_idx - mystique->fifo_read_idx) >= (FIFO_SIZE-1))
-#define FIFO_EMPTY (mystique->fifo_read_idx == mystique->fifo_write_idx)
-
-#define FIFO_TYPE 0xff000000
-#define FIFO_ADDR 0x00ffffff
-
-#define DMA_POLL_TIME_US 100 /*100us*/
-#define DMA_MAX_WORDS 256 /*256 quad words per 100us poll*/
-
-/*These registers are also mirrored into 0x1dxx, with the mirrored versions starting
- the blitter*/
-#define REG_DWGCTL 0x1c00
-#define REG_MACCESS 0x1c04
-#define REG_MCTLWTST 0x1c08
-#define REG_ZORG 0x1c0c
-#define REG_PAT0 0x1c10
-#define REG_PAT1 0x1c14
-#define REG_PLNWT 0x1c1c
-#define REG_BCOL 0x1c20
-#define REG_FCOL 0x1c24
-#define REG_SRC0 0x1c30
-#define REG_SRC1 0x1c34
-#define REG_SRC2 0x1c38
-#define REG_SRC3 0x1c3c
-#define REG_XYSTRT 0x1c40
-#define REG_XYEND 0x1c44
-#define REG_SHIFT 0x1c50
-#define REG_DMAPAD 0x1c54
-#define REG_SGN 0x1c58
-#define REG_LEN 0x1c5c
-#define REG_AR0 0x1c60
-#define REG_AR1 0x1c64
-#define REG_AR2 0x1c68
-#define REG_AR3 0x1c6c
-#define REG_AR4 0x1c70
-#define REG_AR5 0x1c74
-#define REG_AR6 0x1c78
-#define REG_CXBNDRY 0x1c80
-#define REG_FXBNDRY 0x1c84
-#define REG_YDSTLEN 0x1c88
-#define REG_PITCH 0x1c8c
-#define REG_YDST 0x1c90
-#define REG_YDSTORG 0x1c94
-#define REG_YTOP 0x1c98
-#define REG_YBOT 0x1c9c
-#define REG_CXLEFT 0x1ca0
-#define REG_CXRIGHT 0x1ca4
-#define REG_FXLEFT 0x1ca8
-#define REG_FXRIGHT 0x1cac
-#define REG_XDST 0x1cb0
-#define REG_DR0 0x1cc0
-#define REG_DR2 0x1cc8
-#define REG_DR3 0x1ccc
-#define REG_DR4 0x1cd0
-#define REG_DR6 0x1cd8
-#define REG_DR7 0x1cdc
-#define REG_DR8 0x1ce0
-#define REG_DR10 0x1ce8
-#define REG_DR11 0x1cec
-#define REG_DR12 0x1cf0
-#define REG_DR14 0x1cf8
-#define REG_DR15 0x1cfc
-
-#define REG_FIFOSTATUS 0x1e10
-#define REG_STATUS 0x1e14
-#define REG_ICLEAR 0x1e18
-#define REG_IEN 0x1e1c
-#define REG_VCOUNT 0x1e20
-#define REG_DMAMAP 0x1e30
-#define REG_RST 0x1e40
-#define REG_OPMODE 0x1e54
-#define REG_PRIMADDRESS 0x1e58
-#define REG_PRIMEND 0x1e5c
-#define REG_DWG_INDIR_WT 0x1e80
-
-#define REG_ATTR_IDX 0x1fc0
-#define REG_ATTR_DATA 0x1fc1
-#define REG_INSTS0 0x1fc2
-#define REG_MISC 0x1fc2
-#define REG_SEQ_IDX 0x1fc4
-#define REG_SEQ_DATA 0x1fc5
-#define REG_MISCREAD 0x1fcc
-#define REG_GCTL_IDX 0x1fce
-#define REG_GCTL_DATA 0x1fcf
-#define REG_CRTC_IDX 0x1fd4
-#define REG_CRTC_DATA 0x1fd5
-#define REG_INSTS1 0x1fda
-#define REG_CRTCEXT_IDX 0x1fde
-#define REG_CRTCEXT_DATA 0x1fdf
-#define REG_CACHEFLUSH 0x1fff
-
-#define REG_TMR0 0x2c00
-#define REG_TMR1 0x2c04
-#define REG_TMR2 0x2c08
-#define REG_TMR3 0x2c0c
-#define REG_TMR4 0x2c10
-#define REG_TMR5 0x2c14
-#define REG_TMR6 0x2c18
-#define REG_TMR7 0x2c1c
-#define REG_TMR8 0x2c20
-#define REG_TEXORG 0x2c24
-#define REG_TEXWIDTH 0x2c28
-#define REG_TEXHEIGHT 0x2c2c
-#define REG_TEXCTL 0x2c30
-#define REG_TEXTRANS 0x2c34
-#define REG_SECADDRESS 0x2c40
-#define REG_SECEND 0x2c44
-#define REG_SOFTRAP 0x2c48
-
-#define REG_PALWTADD 0x3c00
-#define REG_PALDATA 0x3c01
-#define REG_PIXRDMSK 0x3c02
-#define REG_PALRDADD 0x3c03
-#define REG_X_DATAREG 0x3c0a
-#define REG_CURPOSX 0x3c0c
-#define REG_CURPOSY 0x3c0e
-
-#define REG_STATUS_VSYNCSTS (1 << 3)
-
-#define CRTCX_R0_STARTADD_MASK (0xf << 0)
-#define CRTCX_R0_OFFSET_MASK (3 << 4)
-
-#define CRTCX_R1_HTOTAL8 (1 << 0)
-
-#define CRTCX_R2_VTOTAL10 (1 << 0)
-#define CRTCX_R2_VTOTAL11 (1 << 1)
-#define CRTCX_R2_VDISPEND10 (1 << 2)
-#define CRTCX_R2_VBLKSTR10 (1 << 3)
-#define CRTCX_R2_VBLKSTR11 (1 << 4)
-#define CRTCX_R2_VSYNCSTR10 (1 << 5)
-#define CRTCX_R2_VSYNCSTR11 (1 << 6)
-#define CRTCX_R2_LINECOMP10 (1 << 7)
-
-#define CRTCX_R3_MGAMODE (1 << 7)
-
-#define XREG_XCURADDL 0x04
-#define XREG_XCURADDH 0x05
-#define XREG_XCURCTRL 0x06
-
-#define XREG_XCURCOL0R 0x08
-#define XREG_XCURCOL0G 0x09
-#define XREG_XCURCOL0B 0x0a
-
-#define XREG_XCURCOL1R 0x0c
-#define XREG_XCURCOL1G 0x0d
-#define XREG_XCURCOL1B 0x0e
-
-#define XREG_XCURCOL2R 0x10
-#define XREG_XCURCOL2G 0x11
-#define XREG_XCURCOL2B 0x12
-
-#define XREG_XVREFCTRL 0x18
-#define XREG_XMULCTRL 0x19
-#define XREG_XPIXCLKCTRL 0x1a
-#define XREG_XGENCTRL 0x1d
-#define XREG_XMISCCTRL 0x1e
-
-#define XREG_XGENIOCTRL 0x2a
-#define XREG_XGENIODATA 0x2b
-
-#define XREG_XSYSPLLM 0x2c
-#define XREG_XSYSPLLN 0x2d
-#define XREG_XSYSPLLP 0x2e
-#define XREG_XSYSPLLSTAT 0x2f
-
-#define XREG_XZOOMCTRL 0x38
-
-#define XREG_XPIXPLLCM 0x4c
-#define XREG_XPIXPLLCN 0x4d
-#define XREG_XPIXPLLCP 0x4e
-#define XREG_XPIXPLLSTAT 0x4f
-
-#define XMISCCTRL_VGA8DAC (1 << 3)
-
-#define XMULCTRL_DEPTH_MASK (7 << 0)
-#define XMULCTRL_DEPTH_8 (0 << 0)
-#define XMULCTRL_DEPTH_15 (1 << 0)
-#define XMULCTRL_DEPTH_16 (2 << 0)
-#define XMULCTRL_DEPTH_24 (3 << 0)
-#define XMULCTRL_DEPTH_32_OVERLAYED (4 << 0)
-#define XMULCTRL_DEPTH_2G8V16 (5 << 0)
-#define XMULCTRL_DEPTH_G16V16 (6 << 0)
-#define XMULCTRL_DEPTH_32 (7 << 0)
-
-#define XSYSPLLSTAT_SYSLOCK (1 << 6)
-
-#define XPIXPLLSTAT_SYSLOCK (1 << 6)
-
-#define DWGCTRL_OPCODE_MASK (0xf << 0)
-#define DWGCTRL_OPCODE_LINE_OPEN (0x0 << 0)
-#define DWGCTRL_OPCODE_AUTOLINE_OPEN (0x1 << 0)
-#define DWGCTRL_OPCODE_AUTOLINE_CLOSE (0x3 << 0)
-#define DWGCTRL_OPCODE_TRAP (0x4 << 0)
-#define DWGCTRL_OPCODE_TEXTURE_TRAP (0x6 << 0)
-#define DWGCTRL_OPCODE_ILOAD_HIGH (0x7 << 0)
-#define DWGCTRL_OPCODE_BITBLT (0x8 << 0)
-#define DWGCTRL_OPCODE_ILOAD (0x9 << 0)
-#define DWGCTRL_OPCODE_IDUMP (0xa << 0)
-#define DWGCTRL_OPCODE_ILOAD_SCALE (0xd << 0)
-#define DWGCTRL_OPCODE_ILOAD_HIGHV (0xe << 0)
-#define DWGCTRL_OPCODE_ILOAD_FILTER (0xf << 0) /* Not implemented. */
-#define DWGCTRL_ATYPE_MASK (7 << 4)
-#define DWGCTRL_ATYPE_RPL (0 << 4)
-#define DWGCTRL_ATYPE_RSTR (1 << 4)
-#define DWGCTRL_ATYPE_ZI (3 << 4)
-#define DWGCTRL_ATYPE_BLK (4 << 4)
-#define DWGCTRL_ATYPE_I (7 << 4)
-#define DWGCTRL_LINEAR (1 << 7)
-#define DWGCTRL_ZMODE_MASK (7 << 8)
-#define DWGCTRL_ZMODE_NOZCMP (0 << 8)
-#define DWGCTRL_ZMODE_ZE (2 << 8)
-#define DWGCTRL_ZMODE_ZNE (3 << 8)
-#define DWGCTRL_ZMODE_ZLT (4 << 8)
-#define DWGCTRL_ZMODE_ZLTE (5 << 8)
-#define DWGCTRL_ZMODE_ZGT (6 << 8)
-#define DWGCTRL_ZMODE_ZGTE (7 << 8)
-#define DWGCTRL_SOLID (1 << 11)
-#define DWGCTRL_ARZERO (1 << 12)
-#define DWGCTRL_SGNZERO (1 << 13)
-#define DWGCTRL_SHTZERO (1 << 14)
-#define DWGCTRL_BOP_MASK (0xf << 16)
-#define DWGCTRL_TRANS_SHIFT (20)
-#define DWGCTRL_TRANS_MASK (0xf << DWGCTRL_TRANS_SHIFT)
-#define DWGCTRL_BLTMOD_MASK (0xf << 25)
-#define DWGCTRL_BLTMOD_BMONOLEF (0x0 << 25)
-#define DWGCTRL_BLTMOD_BFCOL (0x2 << 25)
-#define DWGCTRL_BLTMOD_BMONOWF (0x4 << 25)
-#define DWGCTRL_BLTMOD_BU32RGB (0x7 << 25)
-#define DWGCTRL_BLTMOD_BUYUV (0xe << 25)
-#define DWGCTRL_BLTMOD_BU24RGB (0xf << 25)
-#define DWGCTRL_PATTERN (1 << 29)
-#define DWGCTRL_TRANSC (1 << 30)
-#define BOP(x) ((x) << 16)
-
-#define MACCESS_PWIDTH_MASK (3 << 0)
-#define MACCESS_PWIDTH_8 (0 << 0)
-#define MACCESS_PWIDTH_16 (1 << 0)
-#define MACCESS_PWIDTH_32 (2 << 0)
-#define MACCESS_PWIDTH_24 (3 << 0)
-#define MACCESS_TLUTLOAD (1 << 29)
-#define MACCESS_NODITHER (1 << 30)
-#define MACCESS_DIT555 (1 << 31)
-
-#define PITCH_MASK 0x7e0
-#define PITCH_YLIN (1 << 15)
-
-#define SGN_SDYDXL (1 << 0)
-#define SGN_SCANLEFT (1 << 0)
-#define SGN_SDXL (1 << 1)
-#define SGN_SDY (1 << 2)
-#define SGN_SDXR (1 << 5)
-
-#define DMA_ADDR_MASK 0xfffffffc
-#define DMA_MODE_MASK 3
-
-#define DMA_MODE_REG 0
-#define DMA_MODE_BLIT 1
-#define DMA_MODE_VECTOR 2
-
-#define STATUS_SOFTRAPEN (1 << 0)
-#define STATUS_VLINEPEN (1 << 5)
-#define STATUS_DWGENGSTS (1 << 16)
-#define STATUS_ENDPRDMASTS (1 << 17)
-
-#define ICLEAR_SOFTRAPICLR (1 << 0)
-#define ICLEAR_VLINEICLR (1 << 5)
-
-#define IEN_SOFTRAPEN (1 << 0)
-
-#define TEXCTL_TEXFORMAT_MASK (7 << 0)
-#define TEXCTL_TEXFORMAT_TW4 (0 << 0)
-#define TEXCTL_TEXFORMAT_TW8 (1 << 0)
-#define TEXCTL_TEXFORMAT_TW15 (2 << 0)
-#define TEXCTL_TEXFORMAT_TW16 (3 << 0)
-#define TEXCTL_TEXFORMAT_TW12 (4 << 0)
-#define TEXCTL_PALSEL_MASK (0xf << 4)
-#define TEXCTL_TPITCH_SHIFT (16)
-#define TEXCTL_TPITCH_MASK (7 << TEXCTL_TPITCH_SHIFT)
-#define TEXCTL_NPCEN (1 << 21)
-#define TEXCTL_DECALCKEY (1 << 24)
-#define TEXCTL_TAKEY (1 << 25)
-#define TEXCTL_TAMASK (1 << 26)
-#define TEXCTL_CLAMPV (1 << 27)
-#define TEXCTL_CLAMPU (1 << 28)
-#define TEXCTL_TMODULATE (1 << 29)
-#define TEXCTL_STRANS (1 << 30)
-#define TEXCTL_ITRANS (1 << 31)
-
-#define TEXHEIGHT_TH_MASK (0x3f << 0)
-#define TEXHEIGHT_THMASK_SHIFT (18)
-#define TEXHEIGHT_THMASK_MASK (0x7ff << TEXHEIGHT_THMASK_SHIFT)
-
-#define TEXWIDTH_TW_MASK (0x3f << 0)
-#define TEXWIDTH_TWMASK_SHIFT (18)
-#define TEXWIDTH_TWMASK_MASK (0x7ff << TEXWIDTH_TWMASK_SHIFT)
-
-#define TEXTRANS_TCKEY_MASK (0xffff)
-#define TEXTRANS_TKMASK_SHIFT (16)
-#define TEXTRANS_TKMASK_MASK (0xffff << TEXTRANS_TKMASK_SHIFT)
-
-#define DITHER_565 0
-#define DITHER_NONE_565 1
-#define DITHER_555 2
-#define DITHER_NONE_555 3
-
-
-enum
-{
- FIFO_INVALID = (0x00 << 24),
- FIFO_WRITE_CTRL_BYTE = (0x01 << 24),
- FIFO_WRITE_CTRL_LONG = (0x02 << 24),
- FIFO_WRITE_ILOAD_LONG = (0x03 << 24)
-};
-
-enum
-{
- DMA_STATE_IDLE = 0,
- DMA_STATE_PRI,
- DMA_STATE_SEC
-};
-
-
-typedef struct
-{
- uint32_t addr_type;
- uint32_t val;
-} fifo_entry_t;
-
-typedef struct mystique_t
-{
- svga_t svga;
-
- rom_t bios_rom;
-
- mem_mapping_t lfb_mapping, ctrl_mapping,
- iload_mapping;
-
- uint8_t int_line, xcurctrl,
- xsyspllm, xsysplln, xsyspllp,
- xgenioctrl, xgeniodata,
- xmulctrl, xgenctrl,
- xmiscctrl, xpixclkctrl,
- xvrefctrl, ien, dmamod,
- dmadatasiz, dirdatasiz;
-
- uint8_t pci_regs[256], crtcext_regs[6],
- xreg_regs[256], dmamap[16];
-
- int card, vram_size, crtcext_idx, xreg_idx,
- xzoomctrl,
- pixel_count, trap_count;
-
- volatile int busy, blitter_submit_refcount,
- blitter_submit_dma_refcount, blitter_complete_refcount,
- endprdmasts_pending, softrap_pending,
- fifo_read_idx, fifo_write_idx;
-
- uint32_t vram_mask, vram_mask_w, vram_mask_l,
- lfb_base, ctrl_base, iload_base,
- ma_latch_old, maccess, mctlwtst, maccess_running,
- status, softrap_pending_val;
-
- uint64_t blitter_time, status_time;
-
- pc_timer_t softrap_pending_timer, wake_timer;
-
- fifo_entry_t fifo[FIFO_SIZE];
-
- thread_t *fifo_thread;
-
- event_t *wake_fifo_thread, *fifo_not_full_event;
-
- struct
- {
- int m, n, p, s;
- } xpixpll[3];
-
- struct
- {
- uint8_t funcnt, stylelen,
- dmamod;
-
- int16_t fxleft, fxright,
- xdst;
-
- uint16_t cxleft, cxright,
- length;
-
- int xoff, yoff, selline, ydst,
- length_cur, iload_rem_count, idump_end_of_line, words,
- ta_key, ta_mask, lastpix_r, lastpix_g,
- lastpix_b, highv_line, beta, dither;
-
- int pattern[8][8];
-
- uint32_t dwgctrl, dwgctrl_running, bcol, fcol,
- pitch, plnwt, ybot, ydstorg,
- ytop, texorg, texwidth, texheight,
- texctl, textrans, zorg, ydst_lin,
- src_addr, z_base, iload_rem_data, highv_data;
-
- uint32_t src[4], ar[7],
- dr[16], tmr[9];
-
- struct
- {
- int sdydxl, scanleft, sdxl, sdy,
- sdxr;
- } sgn;
- } dwgreg;
-
- struct
- {
- uint8_t r, g, b;
- } lut[256];
-
- struct
- {
- uint16_t pos_x, pos_y,
- addr;
- uint32_t col[3];
- } cursor;
-
- struct
- {
- int pri_pos, sec_pos, iload_pos,
- pri_state, sec_state, iload_state, state;
-
- uint32_t primaddress, primend, secaddress, secend,
- pri_header, sec_header,
- iload_header;
-
- mutex_t *lock;
- } dma;
-} mystique_t;
-
-
-static const uint8_t trans_masks[16][16] =
-{
- {
- 1, 1, 1, 1,
- 1, 1, 1, 1,
- 1, 1, 1, 1,
- 1, 1, 1, 1
- },
- {
- 1, 0, 1, 0,
- 0, 1, 0, 1,
- 1, 0, 1, 0,
- 0, 1, 0, 1
- },
- {
- 0, 1, 0, 1,
- 1, 0, 1, 0,
- 0, 1, 0, 1,
- 1, 0, 1, 0
- },
- {
- 1, 0, 1, 0,
- 0, 0, 0, 0,
- 1, 0, 1, 0,
- 0, 0, 0, 0
- },
- {
- 0, 1, 0, 1,
- 0, 0, 0, 0,
- 0, 1, 0, 1,
- 0, 0, 0, 0
- },
- {
- 0, 0, 0, 0,
- 1, 0, 1, 0,
- 0, 0, 0, 0,
- 1, 0, 1, 0
- },
- {
- 0, 0, 0, 0,
- 0, 1, 0, 1,
- 0, 0, 0, 0,
- 0, 1, 0, 1
- },
- {
- 1, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 1, 0,
- 0, 0, 0, 0
- },
- {
- 0, 0, 0, 0,
- 0, 1, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 1
- },
- {
- 0, 0, 0, 1,
- 0, 0, 0, 0,
- 0, 1, 0, 0,
- 0, 0, 0, 0
- },
- {
- 0, 0, 0, 0,
- 0, 0, 1, 0,
- 0, 0, 0, 0,
- 1, 0, 0, 0
- },
- {
- 0, 0, 0, 0,
- 1, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 1, 0
- },
- {
- 0, 1, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 1,
- 0, 0, 0, 0
- },
- {
- 0, 0, 0, 0,
- 0, 0, 0, 1,
- 0, 0, 0, 0,
- 0, 1, 0, 0
- },
- {
- 0, 0, 1, 0,
- 0, 0, 0, 0,
- 1, 0, 0, 0,
- 0, 0, 0, 0
- },
- {
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0
- }
-};
-
-
-static int8_t dither5[256][2][2];
-static int8_t dither6[256][2][2];
-
-static video_timings_t timing_matrox_mystique = {VIDEO_BUS, 4, 4, 4, 10, 10, 10};
-
-
-static void mystique_start_blit(mystique_t *mystique);
-static void mystique_update_irqs(mystique_t *mystique);
-
-static void wake_fifo_thread(mystique_t *mystique);
-static void wait_fifo_idle(mystique_t *mystique);
-static void mystique_queue(mystique_t *mystique, uint32_t addr, uint32_t val, uint32_t type);
-
-static uint8_t mystique_readb_linear(uint32_t addr, void *p);
-static uint16_t mystique_readw_linear(uint32_t addr, void *p);
-static uint32_t mystique_readl_linear(uint32_t addr, void *p);
-static void mystique_writeb_linear(uint32_t addr, uint8_t val, void *p);
-static void mystique_writew_linear(uint32_t addr, uint16_t val, void *p);
-static void mystique_writel_linear(uint32_t addr, uint32_t val, void *p);
-
-static void mystique_recalc_mapping(mystique_t *mystique);
-static int mystique_line_compare(svga_t *svga);
-
-static uint8_t mystique_iload_read_b(uint32_t addr, void *p);
-static uint32_t mystique_iload_read_l(uint32_t addr, void *p);
-static void mystique_iload_write_b(uint32_t addr, uint8_t val, void *p);
-static void mystique_iload_write_l(uint32_t addr, uint32_t val, void *p);
-
-static uint32_t blit_idump_read(mystique_t *mystique);
-static void blit_iload_write(mystique_t *mystique, uint32_t data, int size);
-
-
-void
-mystique_out(uint16_t addr, uint8_t val, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
- svga_t *svga = &mystique->svga;
- uint8_t old;
-
- if ((((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && addr < 0x3de) && !(svga->miscout & 1))
- addr ^= 0x60;
-
- switch (addr) {
- case 0x3c8:
- mystique->xreg_idx = val;
- break;
-
- case 0x3cf:
- if ((svga->gdcaddr & 15) == 6 && svga->gdcreg[6] != val) {
- svga->gdcreg[svga->gdcaddr & 15] = val;
- mystique_recalc_mapping(mystique);
- return;
- }
- break;
-
- case 0x3D4:
- svga->crtcreg = val & 0x3f;
- return;
- case 0x3D5:
- if (((svga->crtcreg & 31) < 7) && (svga->crtc[0x11] & 0x80))
- return;
- if (((svga->crtcreg & 31) == 7) && (svga->crtc[0x11] & 0x80))
- val = (svga->crtc[7] & ~0x10) | (val & 0x10);
- old = svga->crtc[svga->crtcreg & 0x3f];
- svga->crtc[svga->crtcreg & 31] = val;
- if (old != val) {
- if ((svga->crtcreg & 31) < 0xE || (svga->crtcreg & 31) > 0x10) {
- svga->fullchange = changeframecount;
- svga_recalctimings(svga);
- }
- }
- break;
-
- case 0x3de:
- mystique->crtcext_idx = val;
- break;
- case 0x3df:
- if (mystique->crtcext_idx < 6)
- mystique->crtcext_regs[mystique->crtcext_idx] = val;
- if (mystique->crtcext_idx < 4) {
- svga->fullchange = changeframecount;
- svga_recalctimings(svga);
- }
- if (mystique->crtcext_idx == 3) {
- if (val & CRTCX_R3_MGAMODE)
- svga->fb_only = 1;
- else
- svga->fb_only = 0;
- svga_recalctimings(svga);
- }
- if (mystique->crtcext_idx == 4) {
- if (svga->gdcreg[6] & 0xc) {
- /*64k banks*/
- svga->read_bank = (val & 0x7f) << 16;
- svga->write_bank = (val & 0x7f) << 16;
- } else {
- /*128k banks*/
- svga->read_bank = (val & 0x7e) << 16;
- svga->write_bank = (val & 0x7e) << 16;
- }
- }
- break;
- }
-
- svga_out(addr, val, svga);
-}
-
-
-uint8_t
-mystique_in(uint16_t addr, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
- svga_t *svga = &mystique->svga;
- uint8_t temp = 0xff;
-
- if ((((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && addr < 0x3de) && !(svga->miscout & 1))
- addr ^= 0x60;
-
- switch (addr) {
- case 0x3D4:
- temp = svga->crtcreg;
- break;
- case 0x3D5:
- temp = svga->crtc[svga->crtcreg & 0x3f];
- break;
-
- case 0x3df:
- if (mystique->crtcext_idx < 6)
- temp = mystique->crtcext_regs[mystique->crtcext_idx];
- break;
-
- default:
- temp = svga_in(addr, svga);
- break;
- }
-
- return temp;
-}
-
-
-static int
-mystique_line_compare(svga_t *svga)
-{
- mystique_t *mystique = (mystique_t *)svga->p;
-
- mystique->status |= STATUS_VLINEPEN;
- mystique_update_irqs(mystique);
-
- return 0;
-}
-
-
-void
-mystique_recalctimings(svga_t *svga)
-{
- mystique_t *mystique = (mystique_t *)svga->p;
- int clk_sel = (svga->miscout >> 2) & 3;
-
- if (clk_sel & 2) {
- int m = mystique->xpixpll[2].m;
- int n = mystique->xpixpll[2].n;
- int p = mystique->xpixpll[2].p;
-
- double fvco = 14318181.0 * (n + 1) / (m + 1);
- double fo = fvco / (p + 1);
-
- svga->clock = (cpuclock * (float)(1ull << 32)) / fo;
- }
-
- if (mystique->crtcext_regs[1] & CRTCX_R1_HTOTAL8)
- svga->htotal += 0x100;
- if (mystique->crtcext_regs[2] & CRTCX_R2_VTOTAL10)
- svga->vtotal += 0x400;
- if (mystique->crtcext_regs[2] & CRTCX_R2_VTOTAL11)
- svga->vtotal += 0x800;
- if (mystique->crtcext_regs[2] & CRTCX_R2_VDISPEND10)
- svga->dispend += 0x400;
- if (mystique->crtcext_regs[2] & CRTCX_R2_VBLKSTR10)
- svga->vblankstart += 0x400;
- if (mystique->crtcext_regs[2] & CRTCX_R2_VBLKSTR11)
- svga->vblankstart += 0x800;
- if (mystique->crtcext_regs[2] & CRTCX_R2_VSYNCSTR10)
- svga->vsyncstart += 0x400;
- if (mystique->crtcext_regs[2] & CRTCX_R2_VSYNCSTR11)
- svga->vsyncstart += 0x800;
- if (mystique->crtcext_regs[2] & CRTCX_R2_LINECOMP10)
- svga->split += 0x400;
-
- svga->interlace = !!(mystique->crtcext_regs[0] & 0x80);
-
- if (mystique->crtcext_regs[3] & CRTCX_R3_MGAMODE) {
- int row_offset = svga->crtc[0x13] | ((mystique->crtcext_regs[0] & CRTCX_R0_OFFSET_MASK) << 4);
-
- svga->lowres = 0;
- svga->char_width = 8;
- svga->hdisp = (svga->crtc[1] + 1) * 8;
- svga->hdisp_time = svga->hdisp;
- if (svga->interlace)
- svga->rowoffset = row_offset;
- else
- svga->rowoffset = row_offset * 2;
- svga->ma_latch = ((mystique->crtcext_regs[0] & CRTCX_R0_STARTADD_MASK) << 17) |
- (svga->crtc[0xc] << 9) | (svga->crtc[0xd] << 1);
-
- /*Mystique, unlike most SVGA cards, allows display start to take
- effect mid-screen*/
- if (svga->ma_latch != mystique->ma_latch_old) {
- if (svga->interlace && svga->oddeven)
- svga->ma = svga->maback = (svga->maback - (mystique->ma_latch_old << 2)) + (svga->ma_latch << 2) + (svga->rowoffset << 1);
- else
- svga->ma = svga->maback = (svga->maback - (mystique->ma_latch_old << 2)) + (svga->ma_latch << 2);
- mystique->ma_latch_old = svga->ma_latch;
- }
-
- switch (mystique->xmulctrl & XMULCTRL_DEPTH_MASK) {
- case XMULCTRL_DEPTH_8:
- case XMULCTRL_DEPTH_2G8V16:
- svga->render = svga_render_8bpp_highres;
- svga->bpp = 8;
- break;
- case XMULCTRL_DEPTH_15:
- case XMULCTRL_DEPTH_G16V16:
- svga->render = svga_render_15bpp_highres;
- svga->bpp = 15;
- break;
- case XMULCTRL_DEPTH_16:
- svga->render = svga_render_16bpp_highres;
- svga->bpp = 16;
- break;
- case XMULCTRL_DEPTH_24:
- svga->render = svga_render_24bpp_highres;
- svga->bpp = 24;
- break;
- case XMULCTRL_DEPTH_32:
- case XMULCTRL_DEPTH_32_OVERLAYED:
- svga->render = svga_render_32bpp_highres;
- svga->bpp = 32;
- break;
- }
-
- svga->line_compare = mystique_line_compare;
-
- mem_mapping_set_handler(&mystique->lfb_mapping,
- mystique_readb_linear, mystique_readw_linear, mystique_readl_linear,
- mystique_writeb_linear, mystique_writew_linear, mystique_writel_linear);
- } else {
- svga->line_compare = NULL;
- svga->bpp = 8;
-
- mem_mapping_set_handler(&mystique->lfb_mapping,
- svga_read_linear, svga_readw_linear, svga_readl_linear,
- svga_write_linear, svga_writew_linear, svga_writel_linear);
- }
-}
-
-
-static
-void mystique_recalc_mapping(mystique_t *mystique)
-{
- svga_t *svga = &mystique->svga;
-
- io_removehandler(0x03c0, 0x0020, mystique_in, NULL, NULL, mystique_out, NULL, NULL, mystique);
- if ((mystique->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) && (mystique->pci_regs[0x41] & 1))
- io_sethandler(0x03c0, 0x0020, mystique_in, NULL, NULL, mystique_out, NULL, NULL, mystique);
-
- if (!(mystique->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) {
- mem_mapping_disable(&svga->mapping);
- mem_mapping_disable(&mystique->ctrl_mapping);
- mem_mapping_disable(&mystique->lfb_mapping);
- mem_mapping_disable(&mystique->iload_mapping);
- return;
- }
-
- if (mystique->ctrl_base)
- mem_mapping_set_addr(&mystique->ctrl_mapping, mystique->ctrl_base, 0x4000);
- else
- mem_mapping_disable(&mystique->ctrl_mapping);
-
- if (mystique->lfb_base)
- mem_mapping_set_addr(&mystique->lfb_mapping, mystique->lfb_base, 0x800000);
- else
- mem_mapping_disable(&mystique->lfb_mapping);
-
- if (mystique->iload_base)
- mem_mapping_set_addr(&mystique->iload_mapping, mystique->iload_base, 0x800000);
- else
- mem_mapping_disable(&mystique->iload_mapping);
-
- if (mystique->pci_regs[0x41] & 1) {
- switch (svga->gdcreg[6] & 0x0C) {
- case 0x0: /*128k at A0000*/
- mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
- svga->banked_mask = 0x1ffff;
- break;
- case 0x4: /*64k at A0000*/
- mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
- svga->banked_mask = 0xffff;
- break;
- case 0x8: /*32k at B0000*/
- mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
- svga->banked_mask = 0x7fff;
- break;
- case 0xC: /*32k at B8000*/
- mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
- svga->banked_mask = 0x7fff;
- break;
- }
- if (svga->gdcreg[6] & 0xc) {
- /*64k banks*/
- svga->read_bank = (mystique->crtcext_regs[4] & 0x7f) << 16;
- svga->write_bank = (mystique->crtcext_regs[4] & 0x7f) << 16;
- } else {
- /*128k banks*/
- svga->read_bank = (mystique->crtcext_regs[4] & 0x7e) << 16;
- svga->write_bank = (mystique->crtcext_regs[4] & 0x7e) << 16;
- }
- } else
- mem_mapping_disable(&svga->mapping);
-}
-
-
-static void
-mystique_update_irqs(mystique_t *mystique)
-{
- int irq = 0;
-
- if ((mystique->status & mystique->ien) & STATUS_SOFTRAPEN)
- irq = 1;
-
- if (irq)
- pci_set_irq(mystique->card, PCI_INTA);
- else
- pci_clear_irq(mystique->card, PCI_INTA);
-}
-
-
-#define READ8(addr, var) switch ((addr) & 3) { \
- case 0: ret = (var) & 0xff; break; \
- case 1: ret = ((var) >> 8) & 0xff; break; \
- case 2: ret = ((var) >> 16) & 0xff; break; \
- case 3: ret = ((var) >> 24) & 0xff; break; \
- }
-
-#define WRITE8(addr, var, val) switch ((addr) & 3) { \
- case 0: var = (var & 0xffffff00) | (val); break; \
- case 1: var = (var & 0xffff00ff) | ((val) << 8); break; \
- case 2: var = (var & 0xff00ffff) | ((val) << 16); break; \
- case 3: var = (var & 0x00ffffff) | ((val) << 24); break; \
- }
-
-
-static uint8_t
-mystique_read_xreg(mystique_t *mystique, int reg)
-{
- uint8_t ret = 0xff;
-
- switch (reg) {
- case XREG_XCURADDL:
- ret = mystique->cursor.addr & 0xff;
- break;
- case XREG_XCURADDH:
- ret = mystique->cursor.addr >> 8;
- break;
- case XREG_XCURCTRL:
- ret = mystique->xcurctrl;
- break;
-
- case XREG_XCURCOL0R: case XREG_XCURCOL0G: case XREG_XCURCOL0B:
- READ8(reg, mystique->cursor.col[0]);
- break;
- case XREG_XCURCOL1R: case XREG_XCURCOL1G: case XREG_XCURCOL1B:
- READ8(reg, mystique->cursor.col[1]);
- break;
- case XREG_XCURCOL2R: case XREG_XCURCOL2G: case XREG_XCURCOL2B:
- READ8(reg, mystique->cursor.col[2]);
- break;
-
- case XREG_XMULCTRL:
- ret = mystique->xmulctrl;
- break;
-
- case XREG_XMISCCTRL:
- ret = mystique->xmiscctrl;
- break;
-
- case XREG_XGENCTRL:
- ret = mystique->xgenctrl;
- break;
-
- case XREG_XGENIOCTRL:
- ret = mystique->xgenioctrl;
- break;
- case XREG_XGENIODATA:
- ret = mystique->xgeniodata;
- break;
-
- case XREG_XSYSPLLM:
- ret = mystique->xsyspllm;
- break;
- case XREG_XSYSPLLN:
- ret = mystique->xsysplln;
- break;
- case XREG_XSYSPLLP:
- ret = mystique->xsyspllp;
- break;
-
- case XREG_XZOOMCTRL:
- ret = mystique->xzoomctrl;
- break;
-
- case XREG_XPIXCLKCTRL:
- ret = mystique->xpixclkctrl;
- break;
-
- case XREG_XSYSPLLSTAT:
- ret = XSYSPLLSTAT_SYSLOCK;
- break;
-
- case XREG_XPIXPLLSTAT:
- ret = XPIXPLLSTAT_SYSLOCK;
- break;
-
- case XREG_XPIXPLLCM:
- ret = mystique->xpixpll[2].m;
- break;
- case XREG_XPIXPLLCN:
- ret = mystique->xpixpll[2].n;
- break;
- case XREG_XPIXPLLCP:
- ret = mystique->xpixpll[2].p | (mystique->xpixpll[2].s << 3);
- break;
-
- case 0x00: case 0x20: case 0x3f:
- ret = 0xff;
- break;
-
- default:
- if (reg >= 0x50)
- ret = 0xff;
- break;
- }
-
- return ret;
-}
-
-
-static void
-mystique_write_xreg(mystique_t *mystique, int reg, uint8_t val)
-{
- svga_t *svga = &mystique->svga;
-
- switch (reg) {
- case XREG_XCURADDL:
- mystique->cursor.addr = (mystique->cursor.addr & 0x1f00) | val;
- svga->hwcursor.addr = mystique->cursor.addr << 10;
- break;
- case XREG_XCURADDH:
- mystique->cursor.addr = (mystique->cursor.addr & 0x00ff) | ((val & 0x1f) << 8);
- svga->hwcursor.addr = mystique->cursor.addr << 10;
- break;
-
- case XREG_XCURCTRL:
- mystique->xcurctrl = val;
- svga->hwcursor.ena = (val & 3) ? 1 : 0;
- break;
-
- case XREG_XCURCOL0R: case XREG_XCURCOL0G: case XREG_XCURCOL0B:
- WRITE8(reg, mystique->cursor.col[0], val);
- break;
- case XREG_XCURCOL1R: case XREG_XCURCOL1G: case XREG_XCURCOL1B:
- WRITE8(reg, mystique->cursor.col[1], val);
- break;
- case XREG_XCURCOL2R: case XREG_XCURCOL2G: case XREG_XCURCOL2B:
- WRITE8(reg, mystique->cursor.col[2], val);
- break;
-
- case XREG_XMULCTRL:
- mystique->xmulctrl = val;
- break;
-
- case XREG_XMISCCTRL:
- mystique->xmiscctrl = val;
- svga_set_ramdac_type(svga, (val & XMISCCTRL_VGA8DAC) ? RAMDAC_8BIT : RAMDAC_6BIT);
- break;
-
- case XREG_XGENCTRL:
- mystique->xgenctrl = val;
- break;
-
- case XREG_XVREFCTRL:
- mystique->xvrefctrl = val;
- break;
-
- case XREG_XGENIOCTRL:
- mystique->xgenioctrl = val;
- break;
- case XREG_XGENIODATA:
- mystique->xgeniodata = val;
- break;
-
- case XREG_XSYSPLLM:
- mystique->xsyspllm = val;
- break;
- case XREG_XSYSPLLN:
- mystique->xsysplln = val;
- break;
- case XREG_XSYSPLLP:
- mystique->xsyspllp = val;
- break;
-
- case XREG_XZOOMCTRL:
- mystique->xzoomctrl = val & 3;
- break;
-
- case XREG_XPIXCLKCTRL:
- mystique->xpixclkctrl = val;
- break;
-
- case XREG_XPIXPLLCM:
- mystique->xpixpll[2].m = val;
- break;
- case XREG_XPIXPLLCN:
- mystique->xpixpll[2].n = val;
- break;
- case XREG_XPIXPLLCP:
- mystique->xpixpll[2].p = val & 7;
- mystique->xpixpll[2].s = (val >> 3) & 3;
- break;
-
- case 0x00: case 0x01: case 0x02: case 0x03:
- case 0x07: case 0x0b: case 0x0f:
- case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
- case 0x1b: case 0x1c: case 0x20: case 0x39: case 0x3b: case 0x3f:
- case 0x47: case 0x4b:
- break;
-
- default:
- break;
- }
-}
-
-
-static uint8_t
-mystique_ctrl_read_b(uint32_t addr, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
- svga_t *svga = &mystique->svga;
- uint8_t ret = 0xff;
- int fifocount;
-
- switch (addr & 0x3fff) {
- case REG_FIFOSTATUS:
- fifocount = FIFO_SIZE - FIFO_ENTRIES;
- if (fifocount > 64)
- fifocount = 64;
- ret = fifocount;
- break;
- case REG_FIFOSTATUS+1:
- if (FIFO_EMPTY)
- ret |= 2;
- else if (FIFO_ENTRIES >= 64)
- ret |= 1;
- break;
- case REG_FIFOSTATUS+2: case REG_FIFOSTATUS+3:
- ret = 0;
- break;
-
- case REG_STATUS:
- ret = mystique->status & 0xff;
- if (svga->cgastat & 8)
- ret |= REG_STATUS_VSYNCSTS;
- break;
- case REG_STATUS+1:
- ret = (mystique->status >> 8) & 0xff;
- break;
- case REG_STATUS+2:
- ret = (mystique->status >> 16) & 0xff;
- if (mystique->busy ||
- ((mystique->blitter_submit_refcount + mystique->blitter_submit_dma_refcount) != mystique->blitter_complete_refcount) ||
- !FIFO_EMPTY)
- ret |= (STATUS_DWGENGSTS >> 16);
- break;
- case REG_STATUS+3:
- ret = (mystique->status >> 24) & 0xff;
- break;
-
- case REG_IEN:
- ret = mystique->ien & 0x64;
- break;
- case REG_IEN+1: case REG_IEN+2: case REG_IEN+3:
- ret = 0;
- break;
-
- case REG_OPMODE:
- ret = mystique->dmamod << 2;
- break;
- case REG_OPMODE+1:
- ret = mystique->dmadatasiz;
- break;
- case REG_OPMODE+2:
- ret = mystique->dirdatasiz;
- break;
- case REG_OPMODE+3:
- break;
-
- case REG_PRIMADDRESS: case REG_PRIMADDRESS+1: case REG_PRIMADDRESS+2: case REG_PRIMADDRESS+3:
- READ8(addr, mystique->dma.primaddress);
- break;
- case REG_PRIMEND: case REG_PRIMEND+1: case REG_PRIMEND+2: case REG_PRIMEND+3:
- READ8(addr, mystique->dma.primend);
- break;
-
- case REG_SECADDRESS: case REG_SECADDRESS+1: case REG_SECADDRESS+2: case REG_SECADDRESS+3:
- READ8(addr, mystique->dma.secaddress);
- break;
-
- case REG_VCOUNT: case REG_VCOUNT+1: case REG_VCOUNT+2: case REG_VCOUNT+3:
- READ8(addr, svga->vc);
- break;
-
- case REG_ATTR_IDX:
- ret = svga_in(0x3c0, svga);
- break;
- case REG_ATTR_DATA:
- ret = svga_in(0x3c1, svga);
- break;
-
- case REG_INSTS0:
- ret = svga_in(0x3c2, svga);
- break;
-
- case REG_SEQ_IDX:
- ret = svga_in(0x3c4, svga);
- break;
- case REG_SEQ_DATA:
- ret = svga_in(0x3c5, svga);
- break;
-
- case REG_MISCREAD:
- ret = svga_in(0x3cc, svga);
- break;
-
- case REG_GCTL_IDX:
- ret = mystique_in(0x3ce, mystique);
- break;
- case REG_GCTL_DATA:
- ret = mystique_in(0x3cf, mystique);
- break;
-
- case REG_CRTC_IDX:
- ret = mystique_in(0x3d4, mystique);
- break;
- case REG_CRTC_DATA:
- ret = mystique_in(0x3d5, mystique);
- break;
-
- case REG_INSTS1:
- ret = mystique_in(0x3da, mystique);
- break;
-
- case REG_CRTCEXT_IDX:
- ret = mystique_in(0x3de, mystique);
- break;
- case REG_CRTCEXT_DATA:
- ret = mystique_in(0x3df, mystique);
- break;
-
- case REG_PALWTADD:
- ret = svga_in(0x3c8, svga);
- break;
- case REG_PALDATA:
- ret = svga_in(0x3c9, svga);
- break;
- case REG_PIXRDMSK:
- ret = svga_in(0x3c6, svga);
- break;
- case REG_PALRDADD:
- ret = svga_in(0x3c7, svga);
- break;
-
- case REG_X_DATAREG:
- ret = mystique_read_xreg(mystique, mystique->xreg_idx);
- break;
-
- case 0x1e50: case 0x1e51: case 0x1e52: case 0x1e53:
- case REG_ICLEAR: case REG_ICLEAR+1: case REG_ICLEAR+2: case REG_ICLEAR+3:
- case 0x2c30: case 0x2c31: case 0x2c32: case 0x2c33:
- case 0x3e08:
- break;
-
- default:
- if ((addr & 0x3fff) >= 0x2c00 && (addr & 0x3fff) < 0x2c40)
- break;
- if ((addr & 0x3fff) >= 0x3e00)
- break;
- break;
- }
-
- return ret;
-}
-
-
-static void
-mystique_accel_ctrl_write_b(uint32_t addr, uint8_t val, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
- int start_blit = 0;
- int x;
-
- if ((addr & 0x300) == 0x100) {
- addr &= ~0x100;
- start_blit = 1;
- }
-
- switch (addr & 0x3fff) {
- case REG_MACCESS: case REG_MACCESS+1: case REG_MACCESS+2: case REG_MACCESS+3:
- WRITE8(addr, mystique->maccess, val);
- mystique->dwgreg.dither = mystique->maccess >> 30;
- break;
-
- case REG_MCTLWTST: case REG_MCTLWTST+1: case REG_MCTLWTST+2: case REG_MCTLWTST+3:
- WRITE8(addr, mystique->mctlwtst, val);
- break;
-
- case REG_PAT0: case REG_PAT0+1: case REG_PAT0+2: case REG_PAT0+3:
- case REG_PAT1: case REG_PAT1+1: case REG_PAT1+2: case REG_PAT1+3:
- for (x = 0; x < 8; x++)
- mystique->dwgreg.pattern[addr & 7][x] = val & (1 << (7-x));
- break;
-
- case REG_XYSTRT: case REG_XYSTRT+1:
- WRITE8(addr&1, mystique->dwgreg.ar[5], val);
- if (mystique->dwgreg.ar[5] & 0x8000)
- mystique->dwgreg.ar[5] |= 0xffff8000;
- else
- mystique->dwgreg.ar[5] &= ~0xffff8000;
- WRITE8(addr&1, mystique->dwgreg.xdst, val);
- break;
- case REG_XYSTRT+2: case REG_XYSTRT+3:
- WRITE8(addr & 1, mystique->dwgreg.ar[6], val);
- if (mystique->dwgreg.ar[6] & 0x8000)
- mystique->dwgreg.ar[6] |= 0xffff8000;
- else
- mystique->dwgreg.ar[6] &= ~0xffff8000;
- WRITE8(addr & 1, mystique->dwgreg.ydst, val);
- mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
- break;
-
- case REG_XYEND: case REG_XYEND+1:
- WRITE8(addr&1, mystique->dwgreg.ar[0], val);
- if (mystique->dwgreg.ar[0] & 0x8000)
- mystique->dwgreg.ar[0] |= 0xffff8000;
- else
- mystique->dwgreg.ar[0] &= ~0xffff8000;
- break;
- case REG_XYEND+2: case REG_XYEND+3:
- WRITE8(addr & 1, mystique->dwgreg.ar[2], val);
- if (mystique->dwgreg.ar[2] & 0x8000)
- mystique->dwgreg.ar[2] |= 0xffff8000;
- else
- mystique->dwgreg.ar[2] &= ~0xffff8000;
- break;
-
- case REG_SGN:
- mystique->dwgreg.sgn.sdydxl = val & SGN_SDYDXL;
- mystique->dwgreg.sgn.scanleft = val & SGN_SCANLEFT;
- mystique->dwgreg.sgn.sdxl = val & SGN_SDXL;
- mystique->dwgreg.sgn.sdy = val & SGN_SDY;
- mystique->dwgreg.sgn.sdxr = val & SGN_SDXR;
- break;
- case REG_SGN+1: case REG_SGN+2: case REG_SGN+3:
- break;
-
- case REG_LEN: case REG_LEN+1:
- WRITE8(addr, mystique->dwgreg.length, val);
- break;
- case REG_LEN+2:
- break;
- case REG_LEN+3:
- mystique->dwgreg.beta = val >> 4;
- if (!mystique->dwgreg.beta)
- mystique->dwgreg.beta = 16;
- break;
-
- case REG_CXBNDRY: case REG_CXBNDRY+1:
- WRITE8(addr, mystique->dwgreg.cxleft, val);
- break;
- case REG_CXBNDRY+2: case REG_CXBNDRY+3:
- WRITE8(addr & 1, mystique->dwgreg.cxright, val);
- break;
- case REG_FXBNDRY: case REG_FXBNDRY+1:
- WRITE8(addr, mystique->dwgreg.fxleft, val);
- break;
- case REG_FXBNDRY+2: case REG_FXBNDRY+3:
- WRITE8(addr & 1, mystique->dwgreg.fxright, val);
- break;
-
- case REG_YDSTLEN: case REG_YDSTLEN+1:
- WRITE8(addr, mystique->dwgreg.length, val);
- /* pclog("Write YDSTLEN+%i %i\n", addr&1, mystique->dwgreg.length); */
- break;
- case REG_YDSTLEN+2:
- mystique->dwgreg.ydst = (mystique->dwgreg.ydst & ~0xff) | val;
- if (mystique->dwgreg.pitch & PITCH_YLIN)
- mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg;
- else {
- mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
- mystique->dwgreg.selline = val & 7;
- }
- break;
- case REG_YDSTLEN+3:
- mystique->dwgreg.ydst = (mystique->dwgreg.ydst & 0xff) | (((int32_t)(int8_t)val) << 8);
- if (mystique->dwgreg.pitch & PITCH_YLIN)
- mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg;
- else
- mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
- break;
-
- case REG_XDST: case REG_XDST+1:
- WRITE8(addr & 1, mystique->dwgreg.xdst, val);
- break;
- case REG_XDST+2: case REG_XDST+3:
- break;
-
- case REG_YDSTORG: case REG_YDSTORG+1: case REG_YDSTORG+2: case REG_YDSTORG+3:
- WRITE8(addr, mystique->dwgreg.ydstorg, val);
- mystique->dwgreg.z_base = mystique->dwgreg.ydstorg*2 + mystique->dwgreg.zorg;
- break;
- case REG_YTOP: case REG_YTOP+1: case REG_YTOP+2: case REG_YTOP+3:
- WRITE8(addr, mystique->dwgreg.ytop, val);
- break;
- case REG_YBOT: case REG_YBOT+1: case REG_YBOT+2: case REG_YBOT+3:
- WRITE8(addr, mystique->dwgreg.ybot, val);
- break;
-
- case REG_CXLEFT: case REG_CXLEFT+1:
- WRITE8(addr, mystique->dwgreg.cxleft, val);
- break;
- case REG_CXLEFT+2: case REG_CXLEFT+3:
- break;
- case REG_CXRIGHT: case REG_CXRIGHT+1:
- WRITE8(addr, mystique->dwgreg.cxright, val);
- break;
- case REG_CXRIGHT+2: case REG_CXRIGHT+3:
- break;
-
- case REG_FXLEFT: case REG_FXLEFT+1:
- WRITE8(addr, mystique->dwgreg.fxleft, val);
- break;
- case REG_FXLEFT+2: case REG_FXLEFT+3:
- break;
- case REG_FXRIGHT: case REG_FXRIGHT+1:
- WRITE8(addr, mystique->dwgreg.fxright, val);
- break;
- case REG_FXRIGHT+2: case REG_FXRIGHT+3:
- break;
-
- case REG_SECADDRESS: case REG_SECADDRESS+1: case REG_SECADDRESS+2: case REG_SECADDRESS+3:
- WRITE8(addr, mystique->dma.secaddress, val);
- mystique->dma.sec_state = 0;
- break;
-
- case REG_TMR0: case REG_TMR0+1: case REG_TMR0+2: case REG_TMR0+3:
- WRITE8(addr, mystique->dwgreg.tmr[0], val);
- break;
- case REG_TMR1: case REG_TMR1+1: case REG_TMR1+2: case REG_TMR1+3:
- WRITE8(addr, mystique->dwgreg.tmr[1], val);
- break;
- case REG_TMR2: case REG_TMR2+1: case REG_TMR2+2: case REG_TMR2+3:
- WRITE8(addr, mystique->dwgreg.tmr[2], val);
- break;
- case REG_TMR3: case REG_TMR3+1: case REG_TMR3+2: case REG_TMR3+3:
- WRITE8(addr, mystique->dwgreg.tmr[3], val);
- break;
- case REG_TMR4: case REG_TMR4+1: case REG_TMR4+2: case REG_TMR4+3:
- WRITE8(addr, mystique->dwgreg.tmr[4], val);
- break;
- case REG_TMR5: case REG_TMR5+1: case REG_TMR5+2: case REG_TMR5+3:
- WRITE8(addr, mystique->dwgreg.tmr[5], val);
- break;
- case REG_TMR6: case REG_TMR6+1: case REG_TMR6+2: case REG_TMR6+3:
- WRITE8(addr, mystique->dwgreg.tmr[6], val);
- break;
- case REG_TMR7: case REG_TMR7+1: case REG_TMR7+2: case REG_TMR7+3:
- WRITE8(addr, mystique->dwgreg.tmr[7], val);
- break;
- case REG_TMR8: case REG_TMR8+1: case REG_TMR8+2: case REG_TMR8+3:
- WRITE8(addr, mystique->dwgreg.tmr[8], val);
- break;
-
- case REG_TEXORG: case REG_TEXORG+1: case REG_TEXORG+2: case REG_TEXORG+3:
- WRITE8(addr, mystique->dwgreg.texorg, val);
- break;
- case REG_TEXWIDTH: case REG_TEXWIDTH+1: case REG_TEXWIDTH+2: case REG_TEXWIDTH+3:
- WRITE8(addr, mystique->dwgreg.texwidth, val);
- break;
- case REG_TEXHEIGHT: case REG_TEXHEIGHT+1: case REG_TEXHEIGHT+2: case REG_TEXHEIGHT+3:
- WRITE8(addr, mystique->dwgreg.texheight, val);
- break;
- case REG_TEXCTL: case REG_TEXCTL+1: case REG_TEXCTL+2: case REG_TEXCTL+3:
- WRITE8(addr, mystique->dwgreg.texctl, val);
- mystique->dwgreg.ta_key = (mystique->dwgreg.texctl & TEXCTL_TAKEY) ? 1 : 0;
- mystique->dwgreg.ta_mask = (mystique->dwgreg.texctl & TEXCTL_TAMASK) ? 1 : 0;
- break;
- case REG_TEXTRANS: case REG_TEXTRANS+1: case REG_TEXTRANS+2: case REG_TEXTRANS+3:
- WRITE8(addr, mystique->dwgreg.textrans, val);
- break;
-
- case 0x1c28: case 0x1c29: case 0x1c2a: case 0x1c2b:
- case 0x1c2c: case 0x1c2d: case 0x1c2e: case 0x1c2f:
- case 0x1cc4: case 0x1cc5: case 0x1cc6: case 0x1cc7:
- case 0x1cd4: case 0x1cd5: case 0x1cd6: case 0x1cd7:
- case 0x1ce4: case 0x1ce5: case 0x1ce6: case 0x1ce7:
- case 0x1cf4: case 0x1cf5: case 0x1cf6: case 0x1cf7:
- break;
-
- case REG_OPMODE:
- mystique->dwgreg.dmamod = (val >> 2) & 3;
- mystique->dma.iload_state = 0;
- break;
-
- default:
- if ((addr & 0x3fff) >= 0x2c4c && (addr & 0x3fff) <= 0x2cff)
- break;
- break;
- }
-
- if (start_blit)
- mystique_start_blit(mystique);
-}
-
-
-static void
-mystique_ctrl_write_b(uint32_t addr, uint8_t val, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
- svga_t *svga = &mystique->svga;
-
- if ((addr & 0x3fff) < 0x1c00) {
- mystique_iload_write_b(addr, val, p);
- return;
- }
- if ((addr & 0x3e00) == 0x1c00 || (addr & 0x3e00) == 0x2c00) {
- if ((addr & 0x300) == 0x100)
- mystique->blitter_submit_refcount++;
- mystique_queue(mystique, addr & 0x3fff, val, FIFO_WRITE_CTRL_BYTE);
- return;
- }
-
- switch (addr & 0x3fff) {
- case REG_ICLEAR:
- if (val & ICLEAR_SOFTRAPICLR) {
- mystique->status &= ~STATUS_SOFTRAPEN;
- mystique_update_irqs(mystique);
- }
- if (val & ICLEAR_VLINEICLR) {
- mystique->status &= ~STATUS_VLINEPEN;
- mystique_update_irqs(mystique);
- }
- break;
- case REG_ICLEAR+1: case REG_ICLEAR+2: case REG_ICLEAR+3:
- break;
-
- case REG_IEN:
- mystique->ien = val & 0x65;
- break;
- case REG_IEN+1: case REG_IEN+2: case REG_IEN+3:
- break;
-
- case REG_OPMODE:
- mystique->dmamod = (val >> 2) & 3;
- mystique_queue(mystique, addr & 0x3fff, val, FIFO_WRITE_CTRL_BYTE);
- break;
- case REG_OPMODE+1:
- mystique->dmadatasiz = val & 3;
- break;
- case REG_OPMODE+2:
- mystique->dirdatasiz = val & 3;
- break;
- case REG_OPMODE+3:
- break;
-
- case REG_PRIMADDRESS: case REG_PRIMADDRESS+1: case REG_PRIMADDRESS+2: case REG_PRIMADDRESS+3:
- thread_wait_mutex(mystique->dma.lock);
- WRITE8(addr, mystique->dma.primaddress, val);
- mystique->dma.pri_state = 0;
- thread_release_mutex(mystique->dma.lock);
- break;
-
- case REG_DMAMAP: case REG_DMAMAP+0x1: case REG_DMAMAP+0x2: case REG_DMAMAP+0x3:
- case REG_DMAMAP+0x4: case REG_DMAMAP+0x5: case REG_DMAMAP+0x6: case REG_DMAMAP+0x7:
- case REG_DMAMAP+0x8: case REG_DMAMAP+0x9: case REG_DMAMAP+0xa: case REG_DMAMAP+0xb:
- case REG_DMAMAP+0xc: case REG_DMAMAP+0xd: case REG_DMAMAP+0xe: case REG_DMAMAP+0xf:
- mystique->dmamap[addr & 0xf] = val;
- break;
-
- case REG_RST: case REG_RST+1: case REG_RST+2: case REG_RST+3:
- wait_fifo_idle(mystique);
- mystique->busy = 0;
- mystique->blitter_submit_refcount = 0;
- mystique->blitter_submit_dma_refcount = 0;
- mystique->blitter_complete_refcount = 0;
- mystique->dwgreg.iload_rem_count = 0;
- mystique->status = STATUS_ENDPRDMASTS;
- break;
-
- case REG_ATTR_IDX:
- svga_out(0x3c0, val, svga);
- break;
- case REG_ATTR_DATA:
- svga_out(0x3c1, val, svga);
- break;
-
- case REG_MISC:
- svga_out(0x3c2, val, svga);
- break;
-
- case REG_SEQ_IDX:
- svga_out(0x3c4, val, svga);
- break;
- case REG_SEQ_DATA:
- svga_out(0x3c5, val, svga);
- break;
-
- case REG_GCTL_IDX:
- mystique_out(0x3ce, val, mystique);
- break;
- case REG_GCTL_DATA:
- mystique_out(0x3cf, val, mystique);
- break;
-
- case REG_CRTC_IDX:
- mystique_out(0x3d4, val, mystique);
- break;
- case REG_CRTC_DATA:
- mystique_out(0x3d5, val, mystique);
- break;
-
- case REG_CRTCEXT_IDX:
- mystique_out(0x3de, val, mystique);
- break;
- case REG_CRTCEXT_DATA:
- mystique_out(0x3df, val, mystique);
- break;
-
- case REG_CACHEFLUSH:
- break;
-
- case REG_PALWTADD:
- svga_out(0x3c8, val, svga);
- mystique->xreg_idx = val;
- break;
- case REG_PALDATA:
- svga_out(0x3c9, val, svga);
- break;
- case REG_PIXRDMSK:
- svga_out(0x3c6, val, svga);
- break;
- case REG_PALRDADD:
- svga_out(0x3c7, val, svga);
- break;
-
- case REG_X_DATAREG:
- mystique_write_xreg(mystique, mystique->xreg_idx, val);
- break;
-
- case REG_CURPOSX: case REG_CURPOSX+1:
- WRITE8(addr, mystique->cursor.pos_x, val);
- svga->hwcursor.x = mystique->cursor.pos_x - 64;
- break;
- case REG_CURPOSY: case REG_CURPOSY+1:
- WRITE8(addr & 1, mystique->cursor.pos_y, val);
- svga->hwcursor.y = mystique->cursor.pos_y - 64;
- break;
-
- case 0x1e50: case 0x1e51: case 0x1e52: case 0x1e53:
- case 0x3c0b: case 0x3e02: case 0x3e08:
- break;
-
- default:
- if ((addr & 0x3fff) >= 0x2c4c && (addr & 0x3fff) <= 0x2cff)
- break;
- if ((addr & 0x3fff) >= 0x3e00)
- break;
- break;
- }
-}
-
-
-static uint32_t
-mystique_ctrl_read_l(uint32_t addr, void *p)
-{
- uint32_t ret;
-
- if ((addr & 0x3fff) < 0x1c00)
- return mystique_iload_read_l(addr, p);
-
- ret = mystique_ctrl_read_b(addr, p);
- ret |= mystique_ctrl_read_b(addr+1, p) << 8;
- ret |= mystique_ctrl_read_b(addr+2, p) << 16;
- ret |= mystique_ctrl_read_b(addr+3, p) << 24;
-
- return ret;
-}
-
-
-static void
-mystique_accel_ctrl_write_l(uint32_t addr, uint32_t val, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
- int start_blit = 0;
-
- if ((addr & 0x300) == 0x100) {
- addr &= ~0x100;
- start_blit = 1;
- }
-
- switch (addr & 0x3ffc) {
- case REG_DWGCTL:
- mystique->dwgreg.dwgctrl = val;
- break;
-
- case REG_ZORG:
- mystique->dwgreg.zorg = val;
- mystique->dwgreg.z_base = mystique->dwgreg.ydstorg*2 + mystique->dwgreg.zorg;
- break;
-
- case REG_PLNWT:
- mystique->dwgreg.plnwt = val;
- break;
-
- case REG_SHIFT:
- mystique->dwgreg.funcnt = val & 0xff;
- mystique->dwgreg.xoff = val & 7;
- mystique->dwgreg.yoff = (val >> 4) & 7;
- mystique->dwgreg.stylelen = (val >> 16) & 0xff;
- break;
-
- case REG_PITCH:
- mystique->dwgreg.pitch = val & 0xffff;
- if (mystique->dwgreg.pitch & PITCH_YLIN)
- mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg;
- else
- mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
- break;
-
- case REG_YDST:
- mystique->dwgreg.ydst = val & 0x3fffff;
- if (mystique->dwgreg.pitch & PITCH_YLIN) {
- mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg;
- mystique->dwgreg.selline = val >> 29;
- } else {
- mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
- mystique->dwgreg.selline = val & 7;
- }
- break;
- case REG_BCOL:
- mystique->dwgreg.bcol = val;
- break;
- case REG_FCOL:
- mystique->dwgreg.fcol = val;
- break;
-
- case REG_SRC0:
- mystique->dwgreg.src[0] = val;
- if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
- blit_iload_write(mystique, mystique->dwgreg.src[0], 32);
- break;
- case REG_SRC1:
- mystique->dwgreg.src[1] = val;
- if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
- blit_iload_write(mystique, mystique->dwgreg.src[1], 32);
- break;
- case REG_SRC2:
- mystique->dwgreg.src[2] = val;
- if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
- blit_iload_write(mystique, mystique->dwgreg.src[2], 32);
- break;
- case REG_SRC3:
- mystique->dwgreg.src[3] = val;
- if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
- blit_iload_write(mystique, mystique->dwgreg.src[3], 32);
- break;
-
- case REG_DMAPAD:
- if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
- blit_iload_write(mystique, mystique->dwgreg.src[0], 32);
- break;
-
- case REG_AR0:
- mystique->dwgreg.ar[0] = val;
- break;
- case REG_AR1:
- mystique->dwgreg.ar[1] = val;
- break;
- case REG_AR2:
- mystique->dwgreg.ar[2] = val;
- break;
- case REG_AR3:
- mystique->dwgreg.ar[3] = val;
- break;
- case REG_AR4:
- mystique->dwgreg.ar[4] = val;
- break;
- case REG_AR5:
- mystique->dwgreg.ar[5] = val;
- break;
- case REG_AR6:
- mystique->dwgreg.ar[6] = val;
- break;
-
- case REG_DR0:
- mystique->dwgreg.dr[0] = val;
- break;
- case REG_DR2:
- mystique->dwgreg.dr[2] = val;
- break;
- case REG_DR3:
- mystique->dwgreg.dr[3] = val;
- break;
- case REG_DR4:
- mystique->dwgreg.dr[4] = val;
- break;
- case REG_DR6:
- mystique->dwgreg.dr[6] = val;
- break;
- case REG_DR7:
- mystique->dwgreg.dr[7] = val;
- break;
- case REG_DR8:
- mystique->dwgreg.dr[8] = val;
- break;
- case REG_DR10:
- mystique->dwgreg.dr[10] = val;
- break;
- case REG_DR11:
- mystique->dwgreg.dr[11] = val;
- break;
- case REG_DR12:
- mystique->dwgreg.dr[12] = val;
- break;
- case REG_DR14:
- mystique->dwgreg.dr[14] = val;
- break;
- case REG_DR15:
- mystique->dwgreg.dr[15] = val;
- break;
-
- case REG_SECEND:
- mystique->dma.secend = val;
- if (mystique->dma.state != DMA_STATE_SEC && (mystique->dma.secaddress & DMA_ADDR_MASK) != (mystique->dma.secend & DMA_ADDR_MASK))
- mystique->dma.state = DMA_STATE_SEC;
- break;
-
- case REG_SOFTRAP:
- mystique->dma.state = DMA_STATE_IDLE;
- mystique->endprdmasts_pending = 1;
- mystique->softrap_pending_val = val;
- mystique->softrap_pending = 1;
- break;
-
- default:
- mystique_accel_ctrl_write_b(addr, val & 0xff, p);
- mystique_accel_ctrl_write_b(addr+1, (val >> 8) & 0xff, p);
- mystique_accel_ctrl_write_b(addr+2, (val >> 16) & 0xff, p);
- mystique_accel_ctrl_write_b(addr+3, (val >> 24) & 0xff, p);
- break;
- }
-
- if (start_blit)
- mystique_start_blit(mystique);
-}
-
-
-static void
-mystique_ctrl_write_l(uint32_t addr, uint32_t val, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
- uint32_t reg_addr;
-
- if ((addr & 0x3fff) < 0x1c00) {
- mystique_iload_write_l(addr, val, p);
- return;
- }
-
- if ((addr & 0x3e00) == 0x1c00 || (addr & 0x3e00) == 0x2c00) {
- if ((addr & 0x300) == 0x100)
- mystique->blitter_submit_refcount++;
- mystique_queue(mystique, addr & 0x3fff, val, FIFO_WRITE_CTRL_LONG);
- return;
- }
-
- switch (addr & 0x3ffc) {
- case REG_PRIMEND:
- thread_wait_mutex(mystique->dma.lock);
- mystique->dma.primend = val;
- if (mystique->dma.state == DMA_STATE_IDLE && (mystique->dma.primaddress & DMA_ADDR_MASK) != (mystique->dma.primend & DMA_ADDR_MASK)) {
- mystique->endprdmasts_pending = 0;
- mystique->status &= ~STATUS_ENDPRDMASTS;
-
- mystique->dma.state = DMA_STATE_PRI;
- mystique->dma.pri_state = 0;
- wake_fifo_thread(mystique);
- }
- thread_release_mutex(mystique->dma.lock);
- break;
-
- case REG_DWG_INDIR_WT: case REG_DWG_INDIR_WT+0x04: case REG_DWG_INDIR_WT+0x08: case REG_DWG_INDIR_WT+0x0c:
- case REG_DWG_INDIR_WT+0x10: case REG_DWG_INDIR_WT+0x14: case REG_DWG_INDIR_WT+0x18: case REG_DWG_INDIR_WT+0x1c:
- case REG_DWG_INDIR_WT+0x20: case REG_DWG_INDIR_WT+0x24: case REG_DWG_INDIR_WT+0x28: case REG_DWG_INDIR_WT+0x2c:
- case REG_DWG_INDIR_WT+0x30: case REG_DWG_INDIR_WT+0x34: case REG_DWG_INDIR_WT+0x38: case REG_DWG_INDIR_WT+0x3c:
- reg_addr = (mystique->dmamap[(addr >> 2) & 0xf] & 0x7f) << 2;
- if (mystique->dmamap[(addr >> 2) & 0xf] & 0x80)
- reg_addr += 0x2c00;
- else
- reg_addr += 0x1c00;
-
- if ((reg_addr & 0x300) == 0x100)
- mystique->blitter_submit_refcount++;
-
- mystique_queue(mystique, reg_addr, val, FIFO_WRITE_CTRL_LONG);
- break;
-
- default:
- mystique_ctrl_write_b(addr, val & 0xff, p);
- mystique_ctrl_write_b(addr+1, (val >> 8) & 0xff, p);
- mystique_ctrl_write_b(addr+2, (val >> 16) & 0xff, p);
- mystique_ctrl_write_b(addr+3, (val >> 24) & 0xff, p);
- break;
- }
-}
-
-
-static uint8_t
-mystique_iload_read_b(uint32_t addr, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- wait_fifo_idle(mystique);
-
- if (!mystique->busy)
- return 0xff;
-
- return blit_idump_read(mystique);
-}
-
-
-static uint32_t
-mystique_iload_read_l(uint32_t addr, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- wait_fifo_idle(mystique);
-
- if (!mystique->busy)
- return 0xffffffff;
-
- mystique->dwgreg.words++;
- return blit_idump_read(mystique);
-}
-
-
-static void
-mystique_iload_write_b(uint32_t addr, uint8_t val, void *p)
-{
-
-}
-
-
-static void
-mystique_iload_write_l(uint32_t addr, uint32_t val, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- mystique_queue(mystique, 0, val, FIFO_WRITE_ILOAD_LONG);
-}
-
-static void
-mystique_accel_iload_write_l(uint32_t addr, uint32_t val, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- switch (mystique->dwgreg.dmamod) {
- case DMA_MODE_REG:
- if (mystique->dma.iload_state == 0) {
- mystique->dma.iload_header = val;
- mystique->dma.iload_state = 1;
- } else {
- uint32_t reg_addr = (mystique->dma.iload_header & 0x7f) << 2;
- if (mystique->dma.iload_header & 0x80)
- reg_addr += 0x2c00;
- else
- reg_addr += 0x1c00;
-
- if ((reg_addr & 0x300) == 0x100)
- mystique->blitter_submit_dma_refcount++;
- mystique_accel_ctrl_write_l(reg_addr, val, mystique);
-
- mystique->dma.iload_header >>= 8;
- mystique->dma.iload_state = (mystique->dma.iload_state == 4) ? 0 : (mystique->dma.iload_state+1);
- }
- break;
-
- case DMA_MODE_BLIT:
- if (!mystique->busy)
- fatal("mystique_iload_write_l: !busy\n");
- blit_iload_write(mystique, val, 32);
- break;
-
- /* default:
- pclog("ILOAD write DMAMOD %i\n", mystique->dwgreg.dmamod); */
- }
-}
-
-static uint8_t mystique_readb_linear(uint32_t addr, void *p)
-{
- svga_t *svga = (svga_t *)p;
-
- egareads++;
-
- sub_cycles(video_timing_read_b);
-
- addr &= svga->decode_mask;
- if (addr >= svga->vram_max)
- return 0xff;
-
- return svga->vram[addr & svga->vram_mask];
-}
-static uint16_t mystique_readw_linear(uint32_t addr, void *p)
-{
- svga_t *svga = (svga_t *)p;
-
- egareads += 2;
-
- sub_cycles(video_timing_read_w);
-
- addr &= svga->decode_mask;
- if (addr >= svga->vram_max)
- return 0xffff;
-
- return *(uint16_t *)&svga->vram[addr & svga->vram_mask];
-}
-static uint32_t mystique_readl_linear(uint32_t addr, void *p)
-{
- svga_t *svga = (svga_t *)p;
-
- egareads += 4;
-
- sub_cycles(video_timing_read_l);
-
- addr &= svga->decode_mask;
- if (addr >= svga->vram_max)
- return 0xffffffff;
-
- return *(uint32_t *)&svga->vram[addr & svga->vram_mask];
-}
-
-static void mystique_writeb_linear(uint32_t addr, uint8_t val, void *p)
-{
- svga_t *svga = (svga_t *)p;
-
- egawrites++;
-
- sub_cycles(video_timing_write_b);
-
- addr &= svga->decode_mask;
- if (addr >= svga->vram_max)
- return;
- addr &= svga->vram_mask;
- svga->changedvram[addr >> 12] = changeframecount;
- svga->vram[addr] = val;
-}
-static void mystique_writew_linear(uint32_t addr, uint16_t val, void *p)
-{
- svga_t *svga = (svga_t *)p;
-
- egawrites += 2;
-
- sub_cycles(video_timing_write_w);
-
- addr &= svga->decode_mask;
- if (addr >= svga->vram_max)
- return;
- addr &= svga->vram_mask;
- svga->changedvram[addr >> 12] = changeframecount;
- *(uint16_t *)&svga->vram[addr] = val;
-}
-static void mystique_writel_linear(uint32_t addr, uint32_t val, void *p)
-{
- svga_t *svga = (svga_t *)p;
-
- egawrites += 4;
-
- sub_cycles(video_timing_write_l);
-
- addr &= svga->decode_mask;
- if (addr >= svga->vram_max)
- return;
- addr &= svga->vram_mask;
- svga->changedvram[addr >> 12] = changeframecount;
- *(uint32_t *)&svga->vram[addr] = val;
-}
-
-
-static void
-run_dma(mystique_t *mystique)
-{
- int words_transferred = 0;
-
- thread_wait_mutex(mystique->dma.lock);
-
- if (mystique->dma.state == DMA_STATE_IDLE) {
- thread_release_mutex(mystique->dma.lock);
- return;
- }
-
- while (words_transferred < DMA_MAX_WORDS && mystique->dma.state != DMA_STATE_IDLE) {
- switch (mystique->dma.state) {
- case DMA_STATE_PRI:
- switch (mystique->dma.primaddress & DMA_MODE_MASK) {
- case DMA_MODE_REG:
- if (mystique->dma.pri_state == 0) {
- mystique->dma.pri_header = *(uint32_t *)&ram[mystique->dma.primaddress & DMA_ADDR_MASK];
- mystique->dma.primaddress += 4;
- }
-
- if ((mystique->dma.pri_header & 0xff) != 0x15) {
- uint32_t val = *(uint32_t *)&ram[mystique->dma.primaddress & DMA_ADDR_MASK];
- uint32_t reg_addr;
-
- mystique->dma.primaddress += 4;
-
- reg_addr = (mystique->dma.pri_header & 0x7f) << 2;
- if (mystique->dma.pri_header & 0x80)
- reg_addr += 0x2c00;
- else
- reg_addr += 0x1c00;
-
- if ((reg_addr & 0x300) == 0x100)
- mystique->blitter_submit_dma_refcount++;
-
- mystique_accel_ctrl_write_l(reg_addr, val, mystique);
- }
-
- mystique->dma.pri_header >>= 8;
- mystique->dma.pri_state = (mystique->dma.pri_state + 1) & 3;
-
- words_transferred++;
- if (mystique->dma.state == DMA_STATE_SEC)
- mystique->dma.pri_state = 0;
- else if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
- mystique->endprdmasts_pending = 1;
- mystique->dma.state = DMA_STATE_IDLE;
- }
- break;
-
- default:
- fatal("DMA_STATE_PRI: mode %i\n", mystique->dma.primaddress & DMA_MODE_MASK);
- }
- break;
-
- case DMA_STATE_SEC:
- switch (mystique->dma.secaddress & DMA_MODE_MASK) {
- case DMA_MODE_REG:
- if (mystique->dma.sec_state == 0) {
- mystique->dma.sec_header = *(uint32_t *)&ram[mystique->dma.secaddress & DMA_ADDR_MASK];
- mystique->dma.secaddress += 4;
- }
-
- uint32_t val = *(uint32_t *)&ram[mystique->dma.secaddress & DMA_ADDR_MASK];
- uint32_t reg_addr;
-
- mystique->dma.secaddress += 4;
-
- reg_addr = (mystique->dma.sec_header & 0x7f) << 2;
- if (mystique->dma.sec_header & 0x80)
- reg_addr += 0x2c00;
- else
- reg_addr += 0x1c00;
-
- if ((reg_addr & 0x300) == 0x100)
- mystique->blitter_submit_dma_refcount++;
-
- mystique_accel_ctrl_write_l(reg_addr, val, mystique);
-
- mystique->dma.sec_header >>= 8;
- mystique->dma.sec_state = (mystique->dma.sec_state + 1) & 3;
-
- words_transferred++;
- if ((mystique->dma.secaddress & DMA_ADDR_MASK) == (mystique->dma.secend & DMA_ADDR_MASK)) {
- if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
- mystique->endprdmasts_pending = 1;
- mystique->dma.state = DMA_STATE_IDLE;
- } else
- mystique->dma.state = DMA_STATE_PRI;
- }
- break;
-
- case DMA_MODE_BLIT: {
- uint32_t val = *(uint32_t *)&ram[mystique->dma.secaddress & DMA_ADDR_MASK];
- mystique->dma.secaddress += 4;
-
- if (!mystique->busy)
- fatal("mystique_iload_write_l: !busy\n");
-
- blit_iload_write(mystique, val, 32);
-
- words_transferred++;
- if ((mystique->dma.secaddress & DMA_ADDR_MASK) == (mystique->dma.secend & DMA_ADDR_MASK)) {
- if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
- mystique->endprdmasts_pending = 1;
- mystique->dma.state = DMA_STATE_IDLE;
- } else
- mystique->dma.state = DMA_STATE_PRI;
- }
- } break;
-
- default:
- fatal("DMA_STATE_SEC: mode %i\n", mystique->dma.secaddress & DMA_MODE_MASK);
- }
- break;
- }
- }
-
- thread_release_mutex(mystique->dma.lock);
-}
-
-
-static void
-fifo_thread(void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- while (1) {
- thread_set_event(mystique->fifo_not_full_event);
- thread_wait_event(mystique->wake_fifo_thread, -1);
- thread_reset_event(mystique->wake_fifo_thread);
-
- while (!FIFO_EMPTY || mystique->dma.state != DMA_STATE_IDLE) {
- int words_transferred = 0;
-
- while (!FIFO_EMPTY && words_transferred < 100) {
- fifo_entry_t *fifo = &mystique->fifo[mystique->fifo_read_idx & FIFO_MASK];
-
- switch (fifo->addr_type & FIFO_TYPE) {
- case FIFO_WRITE_CTRL_BYTE:
- mystique_accel_ctrl_write_b(fifo->addr_type & FIFO_ADDR, fifo->val, mystique);
- break;
- case FIFO_WRITE_CTRL_LONG:
- mystique_accel_ctrl_write_l(fifo->addr_type & FIFO_ADDR, fifo->val, mystique);
- break;
- case FIFO_WRITE_ILOAD_LONG:
- mystique_accel_iload_write_l(fifo->addr_type & FIFO_ADDR, fifo->val, mystique);
- break;
- }
-
- fifo->addr_type = FIFO_INVALID;
- mystique->fifo_read_idx++;
-
- if (FIFO_ENTRIES > FIFO_THRESHOLD)
- thread_set_event(mystique->fifo_not_full_event);
-
- words_transferred++;
- }
-
- /*Only run DMA once the FIFO is empty. Required by
- Screamer 2 / Rally which will incorrectly clip an ILOAD
- if DMA runs ahead*/
- if (!words_transferred)
- run_dma(mystique);
- }
- }
-}
-
-
-static void
-wake_fifo_thread(mystique_t *mystique)
-{
- if (!timer_is_enabled(&mystique->wake_timer)) {
- /* Don't wake FIFO thread immediately - if we do that it will probably
- process one word and go back to sleep, requiring it to be woken on
- almost every write. Instead, wait a short while so that the CPU
- emulation writes more data so we have more batched-up work. */
- timer_set_delay_u64(&mystique->wake_timer, WAKE_DELAY);
- }
-}
-
-
-static void
-wake_fifo_thread_now(mystique_t *mystique)
-{
- thread_set_event(mystique->wake_fifo_thread);
-}
-
-
-static void
-mystique_wake_timer(void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- thread_set_event(mystique->wake_fifo_thread); /*Wake up FIFO thread if moving from idle*/
-}
-
-
-static void
-wait_fifo_idle(mystique_t *mystique)
-{
- while (!FIFO_EMPTY) {
- wake_fifo_thread_now(mystique);
- thread_wait_event(mystique->fifo_not_full_event, 1);
- }
-}
-
-
-/*IRQ code (PCI & PIC) is not currently thread safe. SOFTRAP IRQ requests must
- therefore be submitted from the main emulation thread, in this case via a timer
- callback. End-of-DMA status is also deferred here to prevent races between
- SOFTRAP IRQs and code reading the status register. Croc will get into an IRQ
- loop and triple fault if the ENDPRDMASTS flag is seen before the IRQ is taken*/
-static void mystique_softrap_pending_timer(void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- timer_advance_u64(&mystique->softrap_pending_timer, TIMER_USEC * 100);
-
- if (mystique->endprdmasts_pending) {
- mystique->endprdmasts_pending = 0;
- mystique->status |= STATUS_ENDPRDMASTS;
- }
- if (mystique->softrap_pending) {
- mystique->softrap_pending = 0;
-
- mystique->dma.secaddress = mystique->softrap_pending_val;
- mystique->status |= STATUS_SOFTRAPEN;
- mystique_update_irqs(mystique);
- }
-}
-
-
-static
-void mystique_queue(mystique_t *mystique, uint32_t addr, uint32_t val, uint32_t type)
-{
- fifo_entry_t *fifo = &mystique->fifo[mystique->fifo_write_idx & FIFO_MASK];
-
- if (FIFO_FULL) {
- thread_reset_event(mystique->fifo_not_full_event);
- if (FIFO_FULL)
- thread_wait_event(mystique->fifo_not_full_event, -1); /* Wait for room in ringbuffer */
- }
-
- fifo->val = val;
- fifo->addr_type = (addr & FIFO_ADDR) | type;
-
- mystique->fifo_write_idx++;
-
- if (FIFO_ENTRIES > FIFO_THRESHOLD || FIFO_ENTRIES < 8)
- wake_fifo_thread(mystique);
-}
-
-
-static uint32_t
-bitop(uint32_t src, uint32_t dst, uint32_t dwgctrl)
-{
- switch (dwgctrl & DWGCTRL_BOP_MASK) {
- case BOP(0x0): return 0;
- case BOP(0x1): return ~(dst | src);
- case BOP(0x2): return dst & ~src;
- case BOP(0x3): return ~src;
- case BOP(0x4): return ~dst & src;
- case BOP(0x5): return ~dst;
- case BOP(0x6): return dst ^ src;
- case BOP(0x7): return ~(dst & src);
- case BOP(0x8): return dst & src;
- case BOP(0x9): return ~(dst ^ src);
- case BOP(0xa): return dst;
- case BOP(0xb): return dst | ~src;
- case BOP(0xc): return src;
- case BOP(0xd): return ~dst | src;
- case BOP(0xe): return dst | src;
- case BOP(0xf): return ~0;
- }
-
- return 0;
-}
-
-
-static uint16_t
-dither(mystique_t *mystique, int r, int g, int b, int x, int y)
-{
- switch (mystique->dwgreg.dither) {
- case DITHER_NONE_555:
- return (b >> 3) | ((g >> 3) << 5) | ((r >> 3) << 10);
-
- case DITHER_NONE_565:
- return (b >> 3) | ((g >> 2) << 5) | ((r >> 3) << 11);
-
- case DITHER_555:
- return dither5[b][y][x] | (dither5[g][y][x] << 5) | (dither5[r][y][x] << 10);
-
- case DITHER_565:
- default:
- return dither5[b][y][x] | (dither6[g][y][x] << 5) | (dither5[r][y][x] << 11);
- }
-}
-
-
-static uint32_t
-blit_idump_idump(mystique_t *mystique)
-{
- svga_t *svga = &mystique->svga;
- uint64_t val64 = 0;
- uint32_t val = 0;
- int count = 0;
-
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_RPL:
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BU32RGB:
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- while (count < 32) {
- val |= (svga->vram[mystique->dwgreg.src_addr & mystique->vram_mask] << count);
-
- if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
- mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
- mystique->dwgreg.src_addr = mystique->dwgreg.ar[3];
- } else
- mystique->dwgreg.src_addr++;
-
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- break;
- }
- break;
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
-
- count += 8;
- }
- break;
-
- case MACCESS_PWIDTH_16:
- while (count < 32) {
- val |= (((uint16_t *)svga->vram)[mystique->dwgreg.src_addr & mystique->vram_mask_w] << count);
-
- if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
- mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
- mystique->dwgreg.src_addr = mystique->dwgreg.ar[3];
- } else
- mystique->dwgreg.src_addr++;
-
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- break;
- }
- break;
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
-
- count += 16;
- }
- break;
-
- case MACCESS_PWIDTH_24:
- if (mystique->dwgreg.idump_end_of_line) {
- mystique->dwgreg.idump_end_of_line = 0;
- val = mystique->dwgreg.iload_rem_data;
- mystique->dwgreg.iload_rem_count = 0;
- mystique->dwgreg.iload_rem_data = 0;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- }
- break;
- }
-
- count += mystique->dwgreg.iload_rem_count;
- val64 = mystique->dwgreg.iload_rem_data;
-
- while ((count < 32) && !mystique->dwgreg.idump_end_of_line) {
- val64 |= (uint64_t)((*(uint32_t *)&svga->vram[(mystique->dwgreg.src_addr * 3) & mystique->vram_mask]) & 0xffffff) << count;
-
- if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
- mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
- mystique->dwgreg.src_addr = mystique->dwgreg.ar[3];
- } else
- mystique->dwgreg.src_addr++;
-
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- if (count > 8)
- mystique->dwgreg.idump_end_of_line = 1;
- else {
- count = 32;
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- }
- break;
- }
- if (!(mystique->dwgreg.dwgctrl_running & DWGCTRL_LINEAR)) {
- if (count > 8)
- mystique->dwgreg.idump_end_of_line = 1;
- else {
- count = 32;
- break;
- }
- }
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
-
- count += 24;
- }
- if (count > 32)
- mystique->dwgreg.iload_rem_count = count - 32;
- else
- mystique->dwgreg.iload_rem_count = 0;
- mystique->dwgreg.iload_rem_data = (uint32_t)(val64 >> 32);
- val = val64 & 0xffffffff;
- break;
-
- case MACCESS_PWIDTH_32:
- val = (((uint32_t *)svga->vram)[mystique->dwgreg.src_addr & mystique->vram_mask_l] << count);
-
- if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
- mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
- mystique->dwgreg.src_addr = mystique->dwgreg.ar[3];
- } else
- mystique->dwgreg.src_addr++;
-
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- break;
- }
- break;
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
- break;
-
- default:
- fatal("IDUMP DWGCTRL_BLTMOD_BU32RGB %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->maccess_running);
- }
- break;
-
- default:
- fatal("IDUMP DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
- break;
- }
- break;
-
- default:
- fatal("Unknown IDUMP atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
- }
-
- return val;
-}
-
-
-static uint32_t
-blit_idump_read(mystique_t *mystique)
-{
- uint32_t ret = 0xffffffff;
-
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) {
- case DWGCTRL_OPCODE_IDUMP:
- ret = blit_idump_idump(mystique);
- break;
-
- default:
- /* pclog("blit_idump_read: bad opcode %08x\n", mystique->dwgreg.dwgctrl_running); */
- break;
- }
-
- return ret;
-}
-
-
-static void
-blit_iload_iload(mystique_t *mystique, uint32_t data, int size)
-{
- svga_t *svga = &mystique->svga;
- uint32_t src, dst;
- uint64_t data64;
- int min_size = 8;
- uint32_t bltckey = mystique->dwgreg.fcol, bltcmsk = mystique->dwgreg.bcol;
- const int transc = mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC;
- const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT;
- uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- bltckey &= 0xff;
- bltcmsk &= 0xff;
- break;
- case MACCESS_PWIDTH_16:
- bltckey &= 0xffff;
- bltcmsk &= 0xffff;
- break;
- }
-
- mystique->dwgreg.words++;
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_RPL:
- if (mystique->maccess_running & MACCESS_TLUTLOAD) {
- while ((mystique->dwgreg.length_cur > 0) && (size >= 16)) {
- uint16_t src = data & 0xffff;
-
- mystique->lut[mystique->dwgreg.ydst & 0xff].r = (src >> 11) << 3;
- mystique->lut[mystique->dwgreg.ydst & 0xff].g = ((src >> 5) & 0x3f) << 2;
- mystique->lut[mystique->dwgreg.ydst & 0xff].b = (src & 0x1f) << 3;
- mystique->dwgreg.ydst++;
- mystique->dwgreg.length_cur--;
- data >>= 16;
- size -= 16;
- }
-
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- }
- break;
- }
- case DWGCTRL_ATYPE_RSTR:
- case DWGCTRL_ATYPE_BLK:
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BFCOL:
- size += mystique->dwgreg.iload_rem_count;
- data64 = mystique->dwgreg.iload_rem_data | ((uint64_t)data << mystique->dwgreg.iload_rem_count);
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- min_size = 8;
- break;
- case MACCESS_PWIDTH_16:
- min_size = 16;
- break;
- case MACCESS_PWIDTH_24:
- min_size = 24;
- break;
- case MACCESS_PWIDTH_32:
- min_size = 32;
- break;
- }
-
- while (size >= min_size) {
- int draw = (!transc || (data & bltcmsk) != bltckey) && trans[mystique->dwgreg.xdst & 3];
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && draw) {
- dst = svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask];
-
- dst = bitop(data & 0xff, dst, mystique->dwgreg.dwgctrl_running);
- svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask) >> 12] = changeframecount;
- }
-
- data >>= 8;
- size -= 8;
- break;
-
- case MACCESS_PWIDTH_16:
- if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && draw) {
- dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w];
-
- dst = bitop(data & 0xffff, dst, mystique->dwgreg.dwgctrl_running);
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount;
- }
-
- data >>= 16;
- size -= 16;
- break;
-
- case MACCESS_PWIDTH_24:
- if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
- uint32_t old_dst = *((uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]);
-
- dst = bitop(data64, old_dst, mystique->dwgreg.dwgctrl_running);
- *((uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]) = (dst & 0xffffff) | (old_dst & 0xff000000);
- svga->changedvram[(((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask) >> 12] = changeframecount;
- }
-
- data64 >>= 24;
- size -= 24;
- break;
-
- case MACCESS_PWIDTH_32:
- if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && draw) {
- dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
-
- dst = bitop(data, dst, mystique->dwgreg.dwgctrl_running);
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
- }
-
- size = 0;
- break;
-
- default:
- fatal("ILOAD RSTR/RPL BFCOL pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
- }
-
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
- mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- break;
- }
- data64 = 0;
- size = 0;
- break;
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
- }
- mystique->dwgreg.iload_rem_count = size;
- mystique->dwgreg.iload_rem_data = data64;
- break;
-
- case DWGCTRL_BLTMOD_BMONOWF:
- data = (data >> 24) | ((data & 0x00ff0000) >> 8) | ((data & 0x0000ff00) << 8) | (data << 24);
- while (size) {
- if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot &&
- ((data & 0x80000000) || !(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC)) &&
- trans[mystique->dwgreg.xdst & 3]) {
- uint32_t old_dst;
-
- src = (data & 0x80000000) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- dst = svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
-
- svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_16:
- dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
-
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_24:
- old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask];
-
- dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running);
-
- *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
- svga->changedvram[(((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_32:
- dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
-
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
- break;
-
- default:
- fatal("ILOAD RSTR/RPL BMONOWF pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
- }
- }
-
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- break;
- }
- if (!(mystique->dwgreg.dwgctrl_running & DWGCTRL_LINEAR))
- break;
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
- data <<= 1;
- size--;
- }
- break;
-
- case DWGCTRL_BLTMOD_BU24RGB:
- size += mystique->dwgreg.iload_rem_count;
- data64 = mystique->dwgreg.iload_rem_data | ((uint64_t)data << mystique->dwgreg.iload_rem_count);
-
- while (size >= 24) {
- if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_32:
- dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
-
- dst = bitop(data64 & 0xffffff, dst, mystique->dwgreg.dwgctrl_running);
-
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
- break;
-
- default:
- fatal("ILOAD RSTR/RPL BU24RGB pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
- }
- }
-
- data64 >>= 24;
- size -= 24;
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- break;
- }
- data64 = 0;
- size = 0;
- break;
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
- }
-
- mystique->dwgreg.iload_rem_count = size;
- mystique->dwgreg.iload_rem_data = data64;
- break;
-
- case DWGCTRL_BLTMOD_BU32RGB:
- size += mystique->dwgreg.iload_rem_count;
- while (size >= 32) {
- if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_32:
- dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
-
- dst = bitop(data, dst, mystique->dwgreg.dwgctrl_running);
-
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
- break;
-
- default:
- fatal("ILOAD RSTR/RPL BU32RGB pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
- }
- }
-
- size = 0;
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- break;
- }
- break;
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
- }
-
- mystique->dwgreg.iload_rem_count = size;
- break;
-
- default:
- fatal("ILOAD DWGCTRL_ATYPE_RPL\n");
- break;
- }
- break;
-
- default:
- fatal("Unknown ILOAD iload atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
- }
-}
-
-
-#define CLAMP(x) do { \
- if ((x) & ~0xff) \
- x = ((x) < 0) ? 0 : 0xff; \
- } while (0)
-
-
-static void
-blit_iload_iload_scale(mystique_t *mystique, uint32_t data, int size)
-{
- svga_t *svga = &mystique->svga;
- uint64_t data64 = 0;
- int y0, y1;
- int u, v;
- int dR, dG, dB;
- int r0, g0, b0;
- int r1, g1, b1;
-
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BUYUV:
- y0 = (298 * ((int)(data & 0xff) - 16)) >> 8;
- u = ((data >> 8) & 0xff) - 0x80;
- y1 = (298 * ((int)((data >> 16) & 0xff) - 16)) >> 8;
- v = ((data >> 24) & 0xff) - 0x80;
-
- dR = (309*v) >> 8;
- dG = (100*u + 208*v) >> 8;
- dB = (516*u) >> 8;
-
- r0 = y0 + dR;
- CLAMP(r0);
- g0 = y0 - dG;
- CLAMP(g0);
- b0 = y0 + dB;
- CLAMP(b0);
- r1 = y1 + dR;
- CLAMP(r1);
- g1 = y1 - dG;
- CLAMP(g1);
- b1 = y1 + dB;
- CLAMP(b1);
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_16:
- data = (b0 >> 3) | ((g0 >> 2) << 5) | ((r0 >> 3) << 11);
- data |= (((b1 >> 3) | ((g1 >> 2) << 5) | ((r1 >> 3) << 11)) << 16);
- size = 32;
- break;
- case MACCESS_PWIDTH_32:
- data64 = b0 | (g0 << 8) | (r0 << 16);
- data64 |= ((uint64_t)b0 << 32) | ((uint64_t)g0 << 40) | ((uint64_t)r0 << 48);
- size = 64;
- break;
-
- default:
- fatal("blit_iload_iload_scale BUYUV pwidth %i\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
- }
- break;
-
- default:
- fatal("blit_iload_iload_scale bltmod %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK);
- break;
- }
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_16:
- while (size >= 16) {
- if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
- uint16_t dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w];
- dst = bitop(data & 0xffff, dst, mystique->dwgreg.dwgctrl_running);
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount;
- }
-
- mystique->dwgreg.ar[6] += mystique->dwgreg.ar[2];
- if ((int32_t)mystique->dwgreg.ar[6] >= 0) {
- mystique->dwgreg.ar[6] -= (mystique->dwgreg.fxright - mystique->dwgreg.fxleft);
- data >>= 16;
- size -= 16;
- }
-
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
- mystique->dwgreg.ar[6] = mystique->dwgreg.ar[2] - (mystique->dwgreg.fxright - mystique->dwgreg.fxleft);
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- break;
- }
- break;
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
- }
- break;
-
- case MACCESS_PWIDTH_32:
- while (size >= 32) {
- if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
- uint32_t dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
- dst = bitop(data64, dst, mystique->dwgreg.dwgctrl_running);
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
- }
-
- mystique->dwgreg.ar[6] += mystique->dwgreg.ar[2];
- if ((int32_t)mystique->dwgreg.ar[6] >= 0) {
- mystique->dwgreg.ar[6] -= (mystique->dwgreg.fxright - mystique->dwgreg.fxleft);
- data64 >>= 32;
- size -= 32;
- }
-
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
- mystique->dwgreg.ar[6] = mystique->dwgreg.ar[2] - (mystique->dwgreg.fxright - mystique->dwgreg.fxleft);
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- break;
- }
- break;
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
- }
- break;
-
- default:
- fatal("ILOAD_SCALE pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
- }
-}
-
-
-static void
-blit_iload_iload_high(mystique_t *mystique, uint32_t data, int size)
-{
- svga_t *svga = &mystique->svga;
- uint32_t out_data;
- int y0, y1, u, v;
- int dR, dG, dB;
- int r = 0, g = 0, b = 0;
- int next_r = 0, next_g = 0, next_b = 0;
-
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BUYUV:
- y0 = (298 * ((int)(data & 0xff) - 16)) >> 8;
- u = ((data >> 8) & 0xff) - 0x80;
- y1 = (298 * ((int)((data >> 16) & 0xff) - 16)) >> 8;
- v = ((data >> 24) & 0xff) - 0x80;
-
- dR = (309*v) >> 8;
- dG = (100*u + 208*v) >> 8;
- dB = (516*u) >> 8;
-
- r = y0 + dR;
- CLAMP(r);
- g = y0 - dG;
- CLAMP(g);
- b = y0 + dB;
- CLAMP(b);
-
- next_r = y1 + dR;
- CLAMP(next_r);
- next_g = y1 - dG;
- CLAMP(next_g);
- next_b = y1 + dB;
- CLAMP(next_b);
-
- size = 32;
- break;
-
- default:
- fatal("blit_iload_iload_high bltmod %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK);
- break;
- }
-
- while (size >= 16) {
- if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
- uint32_t dst;
- int f1 = (mystique->dwgreg.ar[6] >> 12) & 0xf;
- int f0 = 0x10 - f1;
- int out_r = ((mystique->dwgreg.lastpix_r * f0) + (r * f1)) >> 4;
- int out_g = ((mystique->dwgreg.lastpix_g * f0) + (g * f1)) >> 4;
- int out_b = ((mystique->dwgreg.lastpix_b * f0) + (b * f1)) >> 4;
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_16:
- out_data = (out_b >> 3) | ((out_g >> 2) << 5) | ((out_r >> 3) << 11);
- dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w];
- dst = bitop(out_data, dst, mystique->dwgreg.dwgctrl_running);
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount;
- break;
- case MACCESS_PWIDTH_32:
- out_data = out_b | (out_g << 8) | (out_r << 16);
- dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
- dst = bitop(out_data, dst, mystique->dwgreg.dwgctrl_running);
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
- break;
-
- default:
- fatal("ILOAD_SCALE_HIGH RSTR/RPL BUYUV pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
- }
- }
-
- mystique->dwgreg.ar[6] += mystique->dwgreg.ar[2];
- if ((int32_t)mystique->dwgreg.ar[6] >= 0) {
- mystique->dwgreg.ar[6] -= 65536;
- size -= 16;
-
- mystique->dwgreg.lastpix_r = r;
- mystique->dwgreg.lastpix_g = g;
- mystique->dwgreg.lastpix_b = b;
- r = next_r;
- g = next_g;
- b = next_b;
- }
-
- if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
- mystique->dwgreg.ar[6] = mystique->dwgreg.ar[2] - (mystique->dwgreg.fxright - mystique->dwgreg.fxleft);
- mystique->dwgreg.lastpix_r = 0;
- mystique->dwgreg.lastpix_g = 0;
- mystique->dwgreg.lastpix_b = 0;
-
- mystique->dwgreg.length_cur--;
- if (!mystique->dwgreg.length_cur) {
- mystique->busy = 0;
- mystique->blitter_complete_refcount++;
- break;
- }
- break;
- } else
- mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
- }
-}
-
-
-static void
-blit_iload_iload_highv(mystique_t *mystique, uint32_t data, int size)
-{
- uint8_t *src0, *src1;
-
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BUYUV:
- if (!mystique->dwgreg.highv_line) {
- mystique->dwgreg.highv_data = data;
- mystique->dwgreg.highv_line = 1;
- return;
- }
- mystique->dwgreg.highv_line = 0;
-
- src0 = (uint8_t *)&mystique->dwgreg.highv_data;
- src1 = (uint8_t *)&data;
-
- src1[0] = ((src0[0] * mystique->dwgreg.beta) + (src1[0] * (16 - mystique->dwgreg.beta))) >> 4;
- src1[1] = ((src0[1] * mystique->dwgreg.beta) + (src1[1] * (16 - mystique->dwgreg.beta))) >> 4;
- src1[2] = ((src0[2] * mystique->dwgreg.beta) + (src1[2] * (16 - mystique->dwgreg.beta))) >> 4;
- src1[3] = ((src0[3] * mystique->dwgreg.beta) + (src1[3] * (16 - mystique->dwgreg.beta))) >> 4;
- blit_iload_iload_high(mystique, data, 32);
- break;
-
- default:
- fatal("blit_iload_iload_highv bltmod %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK);
- break;
- }
-}
-
-
-static void
-blit_iload_write(mystique_t *mystique, uint32_t data, int size)
-{
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) {
- case DWGCTRL_OPCODE_ILOAD:
- blit_iload_iload(mystique, data, size);
- break;
-
- case DWGCTRL_OPCODE_ILOAD_SCALE:
- blit_iload_iload_scale(mystique, data, size);
- break;
-
- case DWGCTRL_OPCODE_ILOAD_HIGH:
- blit_iload_iload_high(mystique, data, size);
- break;
-
- case DWGCTRL_OPCODE_ILOAD_HIGHV:
- blit_iload_iload_highv(mystique, data, size);
- break;
-
- default:
- fatal("blit_iload_write: bad opcode %08x\n", mystique->dwgreg.dwgctrl_running);
- }
-}
-
-
-static int
-z_check(uint16_t z, uint16_t old_z, uint32_t z_mode)//mystique->dwgreg.dwgctrl & DWGCTRL_ZMODE_MASK)
-{
- switch (z_mode) {
- case DWGCTRL_ZMODE_ZE:
- return (z == old_z);
- case DWGCTRL_ZMODE_ZNE:
- return (z != old_z);
- case DWGCTRL_ZMODE_ZLT:
- return (z < old_z);
- case DWGCTRL_ZMODE_ZLTE:
- return (z <= old_z);
- case DWGCTRL_ZMODE_ZGT:
- return (z > old_z);
- case DWGCTRL_ZMODE_ZGTE:
- return (z >= old_z);
-
- case DWGCTRL_ZMODE_NOZCMP:
- default:
- return 1;
- }
-}
-
-
-static void
-blit_line(mystique_t *mystique, int closed)
-{
- svga_t *svga = &mystique->svga;
- uint32_t src, dst, old_dst;
- int x;
- int z_write;
-
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_RSTR:
- case DWGCTRL_ATYPE_RPL:
- x = mystique->dwgreg.xdst;
- while (mystique->dwgreg.length > 0) {
- if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- src = mystique->dwgreg.fcol;
- dst = svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
- svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_16:
- src = mystique->dwgreg.fcol;
- dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_24:
- src = mystique->dwgreg.fcol;
- old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
-
- dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running);
- *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
- svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_32:
- src = mystique->dwgreg.fcol;
- dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount;
- break;
-
- default:
- fatal("LINE RSTR/RPL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
- }
- }
-
- if (mystique->dwgreg.sgn.sdydxl)
- x += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
- else
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK));
-
- if ((int32_t)mystique->dwgreg.ar[1] >= 0) {
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2];
- if (mystique->dwgreg.sgn.sdydxl)
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK));
- else
- x += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
- } else
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0];
-
- mystique->dwgreg.length--;
- }
- break;
-
- case DWGCTRL_ATYPE_I:
- case DWGCTRL_ATYPE_ZI:
- z_write = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) == DWGCTRL_ATYPE_ZI);
- x = mystique->dwgreg.xdst;
- while (mystique->dwgreg.length > 0) {
- if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
- uint16_t z = ((int32_t)mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15);
- uint16_t *z_p = (uint16_t *)&svga->vram[(mystique->dwgreg.ydst_lin*2 + mystique->dwgreg.zorg) & mystique->vram_mask];
- uint16_t old_z = z_p[x];
-
- if (z_check(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK)) {
- int r = 0, g = 0, b = 0;
-
- if (z_write)
- z_p[x] = z;
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_16:
- if (!(mystique->dwgreg.dr[4] & (1 << 23)))
- r = (mystique->dwgreg.dr[4] >> 18) & 0x1f;
- if (!(mystique->dwgreg.dr[8] & (1 << 23)))
- g = (mystique->dwgreg.dr[8] >> 17) & 0x3f;
- if (!(mystique->dwgreg.dr[12] & (1 << 23)))
- b = (mystique->dwgreg.dr[12] >> 18) & 0x1f;
- dst = (r << 11) | (g << 5) | b;
-
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
- break;
-
- default:
- fatal("LINE I/ZI PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
- }
- }
- }
-
- if (mystique->dwgreg.sgn.sdydxl)
- x += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
- else
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK));
-
- mystique->dwgreg.dr[0] += mystique->dwgreg.dr[2];
- mystique->dwgreg.dr[4] += mystique->dwgreg.dr[6];
- mystique->dwgreg.dr[8] += mystique->dwgreg.dr[10];
- mystique->dwgreg.dr[12] += mystique->dwgreg.dr[14];
-
- if ((int32_t)mystique->dwgreg.ar[1] >= 0) {
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2];
-
- if (mystique->dwgreg.sgn.sdydxl)
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK));
- else
- x += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
-
- mystique->dwgreg.dr[0] += mystique->dwgreg.dr[3];
- mystique->dwgreg.dr[4] += mystique->dwgreg.dr[7];
- mystique->dwgreg.dr[8] += mystique->dwgreg.dr[11];
- mystique->dwgreg.dr[12] += mystique->dwgreg.dr[15];
- } else
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0];
-
- mystique->dwgreg.length--;
- }
- break;
-
- default:
- /* pclog("Unknown atype %03x %08x LINE\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); */
- break;
- }
-
- mystique->blitter_complete_refcount++;
-}
-
-
-static void
-blit_autoline(mystique_t *mystique, int closed)
-{
- int start_x = (int32_t)mystique->dwgreg.ar[5];
- int start_y = (int32_t)mystique->dwgreg.ar[6];
- int end_x = (int32_t)mystique->dwgreg.ar[0];
- int end_y = (int32_t)mystique->dwgreg.ar[2];
- int dx = end_x - start_x;
- int dy = end_y - start_y;
-
- if (ABS(dx) > ABS(dy)) {
- mystique->dwgreg.sgn.sdydxl = 1;
- mystique->dwgreg.ar[0] = 2*ABS(dy);
- mystique->dwgreg.ar[1] = 2*ABS(dy) - ABS(dx) - ((start_y > end_y) ? 1 : 0);
- mystique->dwgreg.ar[2] = 2*ABS(dy) - 2*ABS(dx);
- mystique->dwgreg.length = ABS(end_x - start_x);
- } else {
- mystique->dwgreg.sgn.sdydxl = 0;
- mystique->dwgreg.ar[0] = 2*ABS(dx);
- mystique->dwgreg.ar[1] = 2*ABS(dx) - ABS(dy) - ((start_y > end_y) ? 1 : 0);
- mystique->dwgreg.ar[2] = 2*ABS(dx) - 2*ABS(dy);
- mystique->dwgreg.length = ABS(end_y - start_y);
- }
- mystique->dwgreg.sgn.sdxl = (start_x > end_x) ? 1 : 0;
- mystique->dwgreg.sgn.sdy = (start_y > end_y) ? 1 : 0;
-
- blit_line(mystique, closed);
-
- mystique->dwgreg.ar[5] = end_x;
- mystique->dwgreg.xdst = end_x;
- mystique->dwgreg.ar[6] = end_y;
- mystique->dwgreg.ydst = end_y;
- mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
-}
-
-
-static void
-blit_trap(mystique_t *mystique)
-{
- svga_t *svga = &mystique->svga;
- uint32_t z_back, r_back, g_back, b_back;
- int z_write;
- int y;
- const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT;
-
- mystique->trap_count++;
-
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_BLK:
- case DWGCTRL_ATYPE_RPL:
- for (y = 0; y < mystique->dwgreg.length; y++) {
- uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
- int16_t x_l = mystique->dwgreg.fxleft & 0xffff;
- int16_t x_r = mystique->dwgreg.fxright & 0xffff;
- int yoff = (mystique->dwgreg.yoff + mystique->dwgreg.ydst) & 7;
-
- while (x_l != x_r) {
- if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot &&
- trans[x_l & 3]) {
- int xoff = (mystique->dwgreg.xoff + x_l) & 7;
- int pattern = mystique->dwgreg.pattern[yoff][xoff];
- uint32_t dst;
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask] =
- (pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xff;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_16:
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] =
- (pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xffff;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_24:
- dst = *(uint32_t *)(&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) & 0xff000000;
- *(uint32_t *)(&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) =
- ((pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xffffff) | dst;
- svga->changedvram[(((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_32:
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] =
- pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount;
- break;
-
- default:
- fatal("TRAP BLK/RPL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
- }
- }
- x_l++;
- mystique->pixel_count++;
- }
-
- if ((int32_t)mystique->dwgreg.ar[1] < 0) {
- while ((int32_t)mystique->dwgreg.ar[1] < 0 && mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0];
- mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
- }
- } else
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2];
-
- if ((int32_t)mystique->dwgreg.ar[4] < 0) {
- while ((int32_t)mystique->dwgreg.ar[4] < 0 && mystique->dwgreg.ar[6]) {
- mystique->dwgreg.ar[4] += mystique->dwgreg.ar[6];
- mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1);
- }
- } else
- mystique->dwgreg.ar[4] += mystique->dwgreg.ar[5];
-
- mystique->dwgreg.ydst++;
- mystique->dwgreg.ydst &= 0x7fffff;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
-
- mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
- }
- break;
-
- case DWGCTRL_ATYPE_RSTR:
- for (y = 0; y < mystique->dwgreg.length; y++) {
- uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
- int16_t x_l = mystique->dwgreg.fxleft & 0xffff;
- int16_t x_r = mystique->dwgreg.fxright & 0xffff;
- int yoff = (mystique->dwgreg.yoff + mystique->dwgreg.ydst) & 7;
-
- while (x_l != x_r) {
- if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot &&
- trans[x_l & 3]) {
- int xoff = (mystique->dwgreg.xoff + x_l) & 7;
- int pattern = mystique->dwgreg.pattern[yoff][xoff];
- uint32_t src = pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
- uint32_t dst, old_dst;
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- dst = svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
- svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_16:
- dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_24:
- old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask];
-
- dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running);
- *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
- svga->changedvram[(((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_32:
- dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount;
- break;
-
- default:
- fatal("TRAP RSTR PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
- }
- }
- x_l++;
- mystique->pixel_count++;
- }
-
- if ((int32_t)mystique->dwgreg.ar[1] < 0) {
- while ((int32_t)mystique->dwgreg.ar[1] < 0 && mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0];
- mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
- }
- } else
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2];
-
- if ((int32_t)mystique->dwgreg.ar[4] < 0) {
- while ((int32_t)mystique->dwgreg.ar[4] < 0 && mystique->dwgreg.ar[6]) {
- mystique->dwgreg.ar[4] += mystique->dwgreg.ar[6];
- mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1);
- }
- } else
- mystique->dwgreg.ar[4] += mystique->dwgreg.ar[5];
-
- mystique->dwgreg.ydst++;
- mystique->dwgreg.ydst &= 0x7fffff;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
-
- mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
- }
- break;
-
- case DWGCTRL_ATYPE_I:
- case DWGCTRL_ATYPE_ZI:
- z_write = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) == DWGCTRL_ATYPE_ZI);
-
- for (y = 0; y < mystique->dwgreg.length; y++) {
- uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
- uint16_t *z_p = (uint16_t *)&svga->vram[(mystique->dwgreg.ydst_lin*2 + mystique->dwgreg.zorg) & mystique->vram_mask];
- int16_t x_l = mystique->dwgreg.fxleft & 0xffff;
- int16_t x_r = mystique->dwgreg.fxright & 0xffff;
- int16_t old_x_l = x_l;
- int dx;
-
- z_back = mystique->dwgreg.dr[0];
- r_back = mystique->dwgreg.dr[4];
- g_back = mystique->dwgreg.dr[8];
- b_back = mystique->dwgreg.dr[12];
-
- while (x_l != x_r) {
- if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot &&
- trans[x_l & 3]) {
- uint16_t z = ((int32_t)mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15);
- uint16_t old_z = z_p[x_l];
-
- if (z_check(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK)) {
- uint32_t dst = 0, old_dst;
- int r = 0, g = 0, b = 0;
-
- if (!(mystique->dwgreg.dr[4] & (1 << 23)))
- r = (mystique->dwgreg.dr[4] >> 15) & 0xff;
- if (!(mystique->dwgreg.dr[8] & (1 << 23)))
- g = (mystique->dwgreg.dr[8] >> 15) & 0xff;
- if (!(mystique->dwgreg.dr[12] & (1 << 23)))
- b = (mystique->dwgreg.dr[12] >> 15) & 0xff;
-
- if (z_write)
- z_p[x_l] = z;
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_16:
- dst = dither(mystique, r, g, b, x_l & 1, mystique->dwgreg.selline & 1);
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_24:
- old_dst = *(uint32_t *)(&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) & 0xff000000;
- *(uint32_t *)(&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) = old_dst | dst;
- svga->changedvram[(((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_32:
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = b | (g << 8) | (r << 16);
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount;
- break;
-
- default:
- fatal("TRAP BLK/RPL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
- }
- }
- }
-
- mystique->dwgreg.dr[0] += mystique->dwgreg.dr[2];
- mystique->dwgreg.dr[4] += mystique->dwgreg.dr[6];
- mystique->dwgreg.dr[8] += mystique->dwgreg.dr[10];
- mystique->dwgreg.dr[12] += mystique->dwgreg.dr[14];
-
- x_l++;
- mystique->pixel_count++;
- }
-
- mystique->dwgreg.dr[0] = z_back + mystique->dwgreg.dr[3];
- mystique->dwgreg.dr[4] = r_back + mystique->dwgreg.dr[7];
- mystique->dwgreg.dr[8] = g_back + mystique->dwgreg.dr[11];
- mystique->dwgreg.dr[12] = b_back + mystique->dwgreg.dr[15];
-
- while ((int32_t)mystique->dwgreg.ar[1] < 0 && mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0];
- mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
- }
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2];
-
- while ((int32_t)mystique->dwgreg.ar[4] < 0 && mystique->dwgreg.ar[6]) {
- mystique->dwgreg.ar[4] += mystique->dwgreg.ar[6];
- mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1);
- }
- mystique->dwgreg.ar[4] += mystique->dwgreg.ar[5];
-
- dx = (int16_t)((mystique->dwgreg.fxleft - old_x_l) & 0xffff);
- mystique->dwgreg.dr[0] += dx*mystique->dwgreg.dr[2];
- mystique->dwgreg.dr[4] += dx*mystique->dwgreg.dr[6];
- mystique->dwgreg.dr[8] += dx*mystique->dwgreg.dr[10];
- mystique->dwgreg.dr[12] += dx*mystique->dwgreg.dr[14];
-
- mystique->dwgreg.ydst++;
- mystique->dwgreg.ydst &= 0x7fffff;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
-
- mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
- }
- break;
-
- default:
- fatal("Unknown atype %03x %08x TRAP\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
- }
-
- mystique->blitter_complete_refcount++;
-}
-
-
-static int texture_read(mystique_t *mystique, int *tex_r, int *tex_g, int *tex_b, int *atransp)
-{
- svga_t *svga = &mystique->svga;
-
- const int tex_shift = 3 + ((mystique->dwgreg.texctl & TEXCTL_TPITCH_MASK) >> TEXCTL_TPITCH_SHIFT);
- const unsigned int palsel = mystique->dwgreg.texctl & TEXCTL_PALSEL_MASK;
- const uint16_t tckey = mystique->dwgreg.textrans & TEXTRANS_TCKEY_MASK;
- const uint16_t tkmask = (mystique->dwgreg.textrans & TEXTRANS_TKMASK_MASK) >> TEXTRANS_TKMASK_SHIFT;
- const unsigned int w_mask = (mystique->dwgreg.texwidth & TEXWIDTH_TWMASK_MASK) >> TEXWIDTH_TWMASK_SHIFT;
- const unsigned int h_mask = (mystique->dwgreg.texheight & TEXHEIGHT_THMASK_MASK) >> TEXHEIGHT_THMASK_SHIFT;
- uint16_t src = 0;
- int s, t;
-
- if (mystique->dwgreg.texctl & TEXCTL_NPCEN) {
- const int s_shift = 20 - (mystique->dwgreg.texwidth & TEXWIDTH_TW_MASK);
- const int t_shift = 20 - (mystique->dwgreg.texheight & TEXHEIGHT_TH_MASK);
-
- s = (int32_t)mystique->dwgreg.tmr[6] >> s_shift;
- t = (int32_t)mystique->dwgreg.tmr[7] >> t_shift;
- } else {
- const int s_shift = (20 + 16) - (mystique->dwgreg.texwidth & TEXWIDTH_TW_MASK);
- const int t_shift = (20 + 16) - (mystique->dwgreg.texheight & TEXHEIGHT_TH_MASK);
- int64_t q = mystique->dwgreg.tmr[8] ? ((0x100000000ll / (int64_t)(int32_t)mystique->dwgreg.tmr[8]) /*>> 16*/) : 0;
-
- s = (((int64_t)(int32_t)mystique->dwgreg.tmr[6] * q) /*<< 8*/) >> s_shift;/*((16+20)-12);*/
- t = (((int64_t)(int32_t)mystique->dwgreg.tmr[7] * q) /*<< 8*/) >> t_shift;/*((16+20)-9);*/
- }
-
- if (mystique->dwgreg.texctl & TEXCTL_CLAMPU) {
- if (s < 0)
- s = 0;
- else if (s > w_mask)
- s = w_mask;
- } else
- s &= w_mask;
-
- if (mystique->dwgreg.texctl & TEXCTL_CLAMPV) {
- if (t < 0)
- t = 0;
- else if (t > h_mask)
- t = h_mask;
- } else
- t &= h_mask;
-
- switch (mystique->dwgreg.texctl & TEXCTL_TEXFORMAT_MASK) {
- case TEXCTL_TEXFORMAT_TW4:
- src = svga->vram[(mystique->dwgreg.texorg + (((t << tex_shift) + s) >> 1)) & mystique->vram_mask];
- if (s & 1)
- src >>= 4;
- else
- src &= 0xf;
- *tex_r = mystique->lut[src | palsel].r;
- *tex_g = mystique->lut[src | palsel].g;
- *tex_b = mystique->lut[src | palsel].b;
- *atransp = 0;
- break;
- case TEXCTL_TEXFORMAT_TW8:
- src = svga->vram[(mystique->dwgreg.texorg + (t << tex_shift) + s) & mystique->vram_mask];
- *tex_r = mystique->lut[src].r;
- *tex_g = mystique->lut[src].g;
- *tex_b = mystique->lut[src].b;
- *atransp = 0;
- break;
- case TEXCTL_TEXFORMAT_TW15:
- src = ((uint16_t *)svga->vram)[((mystique->dwgreg.texorg >> 1) + (t << tex_shift) + s) & mystique->vram_mask_w];
- *tex_r = ((src >> 10) & 0x1f) << 3;
- *tex_g = ((src >> 5) & 0x1f) << 3;
- *tex_b = (src & 0x1f) << 3;
- if (((src >> 15) & mystique->dwgreg.ta_mask) == mystique->dwgreg.ta_key)
- *atransp = 1;
- else
- *atransp = 0;
- break;
- case TEXCTL_TEXFORMAT_TW16:
- src = ((uint16_t *)svga->vram)[((mystique->dwgreg.texorg >> 1) + (t << tex_shift) + s) & mystique->vram_mask_w];
- *tex_r = (src >> 11) << 3;
- *tex_g = ((src >> 5) & 0x3f) << 2;
- *tex_b = (src & 0x1f) << 3;
- *atransp = 0;
- break;
- default:
- fatal("Unknown texture format %i\n", mystique->dwgreg.texctl & TEXCTL_TEXFORMAT_MASK);
- break;
- }
-
- return ((src & tkmask) == tckey);
-}
-
-
-static void
-blit_texture_trap(mystique_t *mystique)
-{
- svga_t *svga = &mystique->svga;
- int y;
- int z_write;
- const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT;
- const int dest32 = ((mystique->maccess_running & MACCESS_PWIDTH_MASK) == MACCESS_PWIDTH_32);
-
- mystique->trap_count++;
-
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_I:
- case DWGCTRL_ATYPE_ZI:
- z_write = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) == DWGCTRL_ATYPE_ZI);
-
- for (y = 0; y < mystique->dwgreg.length; y++) {
- uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
- uint16_t *z_p = (uint16_t *)&svga->vram[(mystique->dwgreg.ydst_lin*2 + mystique->dwgreg.zorg) & mystique->vram_mask];
- int16_t x_l = mystique->dwgreg.fxleft & 0xffff;
- int16_t x_r = mystique->dwgreg.fxright & 0xffff;
- int16_t old_x_l = x_l;
- int dx;
-
- uint32_t z_back = mystique->dwgreg.dr[0];
- uint32_t r_back = mystique->dwgreg.dr[4];
- uint32_t g_back = mystique->dwgreg.dr[8];
- uint32_t b_back = mystique->dwgreg.dr[12];
- uint32_t s_back = mystique->dwgreg.tmr[6];
- uint32_t t_back = mystique->dwgreg.tmr[7];
- uint32_t q_back = mystique->dwgreg.tmr[8];
-
- while (x_l != x_r) {
- if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot &&
- trans[x_l & 3]) {
- uint16_t z = ((int32_t)mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15);
- uint16_t old_z = z_p[x_l];
-
- if (z_check(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK)) {
- int tex_r = 0, tex_g = 0, tex_b = 0;
- int ctransp, atransp = 0;
- int i_r = 0, i_g = 0, i_b = 0;
-
- if (!(mystique->dwgreg.dr[4] & (1 << 23)))
- i_r = (mystique->dwgreg.dr[4] >> 15) & 0xff;
- if (!(mystique->dwgreg.dr[8] & (1 << 23)))
- i_g = (mystique->dwgreg.dr[8] >> 15) & 0xff;
- if (!(mystique->dwgreg.dr[12] & (1 << 23)))
- i_b = (mystique->dwgreg.dr[12] >> 15) & 0xff;
-
- ctransp = texture_read(mystique, &tex_r, &tex_g, &tex_b, &atransp);
-
- switch (mystique->dwgreg.texctl & (TEXCTL_TMODULATE | TEXCTL_STRANS | TEXCTL_ITRANS | TEXCTL_DECALCKEY)) {
- case 0:
- if (ctransp)
- goto skip_pixel;
- if (atransp) {
- tex_r = i_r;
- tex_g = i_g;
- tex_b = i_b;
- }
- break;
-
- case TEXCTL_DECALCKEY:
- if (ctransp) {
- tex_r = i_r;
- tex_g = i_g;
- tex_b = i_b;
- }
- break;
-
- case (TEXCTL_STRANS | TEXCTL_DECALCKEY):
- if (ctransp)
- goto skip_pixel;
- break;
-
- case TEXCTL_TMODULATE:
- if (ctransp)
- goto skip_pixel;
- if (mystique->dwgreg.texctl & TEXCTL_TMODULATE) {
- tex_r = (tex_r * i_r) >> 8;
- tex_g = (tex_g * i_g) >> 8;
- tex_b = (tex_b * i_b) >> 8;
- }
- break;
-
- case (TEXCTL_TMODULATE | TEXCTL_STRANS):
- if (ctransp || atransp)
- goto skip_pixel;
- if (mystique->dwgreg.texctl & TEXCTL_TMODULATE) {
- tex_r = (tex_r * i_r) >> 8;
- tex_g = (tex_g * i_g) >> 8;
- tex_b = (tex_b * i_b) >> 8;
- }
- break;
-
- default:
- fatal("Bad TEXCTL %08x %08x\n", mystique->dwgreg.texctl, mystique->dwgreg.texctl & (TEXCTL_TMODULATE | TEXCTL_STRANS | TEXCTL_ITRANS | TEXCTL_DECALCKEY));
- }
-
- if (dest32) {
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = tex_b | (tex_g << 8) | (tex_r << 16);
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount;
- } else {
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = dither(mystique, tex_r, tex_g, tex_b, x_l & 1, mystique->dwgreg.selline & 1);
- svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount;
- }
- if (z_write)
- z_p[x_l] = z;
- }
- }
-skip_pixel:
- x_l++;
- mystique->pixel_count++;
-
- mystique->dwgreg.dr[0] += mystique->dwgreg.dr[2];
- mystique->dwgreg.dr[4] += mystique->dwgreg.dr[6];
- mystique->dwgreg.dr[8] += mystique->dwgreg.dr[10];
- mystique->dwgreg.dr[12] += mystique->dwgreg.dr[14];
- mystique->dwgreg.tmr[6] += mystique->dwgreg.tmr[0];
- mystique->dwgreg.tmr[7] += mystique->dwgreg.tmr[2];
- mystique->dwgreg.tmr[8] += mystique->dwgreg.tmr[4];
- }
-
- mystique->dwgreg.dr[0] = z_back + mystique->dwgreg.dr[3];
- mystique->dwgreg.dr[4] = r_back + mystique->dwgreg.dr[7];
- mystique->dwgreg.dr[8] = g_back + mystique->dwgreg.dr[11];
- mystique->dwgreg.dr[12] = b_back + mystique->dwgreg.dr[15];
- mystique->dwgreg.tmr[6] = s_back + mystique->dwgreg.tmr[1];
- mystique->dwgreg.tmr[7] = t_back + mystique->dwgreg.tmr[3];
- mystique->dwgreg.tmr[8] = q_back + mystique->dwgreg.tmr[5];
-
- while ((int32_t)mystique->dwgreg.ar[1] < 0 && mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0];
- mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
- }
- mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2];
-
- while ((int32_t)mystique->dwgreg.ar[4] < 0 && mystique->dwgreg.ar[6]) {
- mystique->dwgreg.ar[4] += mystique->dwgreg.ar[6];
- mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1);
- }
- mystique->dwgreg.ar[4] += mystique->dwgreg.ar[5];
-
- dx = (int16_t)((mystique->dwgreg.fxleft - old_x_l) & 0xffff);
- mystique->dwgreg.dr[0] += dx*mystique->dwgreg.dr[2];
- mystique->dwgreg.dr[4] += dx*mystique->dwgreg.dr[6];
- mystique->dwgreg.dr[8] += dx*mystique->dwgreg.dr[10];
- mystique->dwgreg.dr[12] += dx*mystique->dwgreg.dr[14];
- mystique->dwgreg.tmr[6] += dx*mystique->dwgreg.tmr[0];
- mystique->dwgreg.tmr[7] += dx*mystique->dwgreg.tmr[2];
- mystique->dwgreg.tmr[8] += dx*mystique->dwgreg.tmr[4];
-
- mystique->dwgreg.ydst++;
- mystique->dwgreg.ydst &= 0x7fffff;
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
-
- mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
- }
- break;
-
- default:
- fatal("Unknown atype %03x %08x TEXTURE_TRAP\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
- }
-
- mystique->blitter_complete_refcount++;
-}
-
-
-static void
-blit_bitblt(mystique_t *mystique)
-{
- svga_t *svga = &mystique->svga;
- uint32_t src_addr;
- int y;
- int x_dir = mystique->dwgreg.sgn.scanleft ? -1 : 1;
- int16_t x_start = mystique->dwgreg.sgn.scanleft ? mystique->dwgreg.fxright : mystique->dwgreg.fxleft;
- int16_t x_end = mystique->dwgreg.sgn.scanleft ? mystique->dwgreg.fxleft : mystique->dwgreg.fxright;
- const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT;
-
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_BLK:
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BMONOLEF:
- src_addr = mystique->dwgreg.ar[3];
-
- for (y = 0; y < mystique->dwgreg.length; y++) {
- int16_t x = x_start;
-
- while (1) {
- if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
- uint32_t byte_addr = (src_addr >> 3) & mystique->vram_mask;
- int bit_offset = src_addr & 7;
- uint32_t old_dst;
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) {
- if (svga->vram[byte_addr] & (1 << bit_offset))
- svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = mystique->dwgreg.fcol;
- } else
- svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] =
- (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_16:
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) {
- if (svga->vram[byte_addr] & (1 << bit_offset))
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = mystique->dwgreg.fcol;
- } else
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] =
- (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_24:
- old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) {
- if (svga->vram[byte_addr] & (1 << bit_offset))
- *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] =
- (old_dst & 0xff000000) | (mystique->dwgreg.fcol & 0xffffff);
- } else
- *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] =
- (old_dst & 0xff000000) | (((svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xffffff);
- svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_32:
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) {
- if (svga->vram[byte_addr] & (1 << bit_offset))
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = mystique->dwgreg.fcol;
- } else
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] =
- (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 11] = changeframecount;
- break;
-
- default:
- fatal("BITBLT DWGCTRL_ATYPE_BLK unknown MACCESS %i\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
- }
- }
-
- if (src_addr == mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
- mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
- src_addr = mystique->dwgreg.ar[3];
- } else
- src_addr += x_dir;
-
- if (x != x_end)
- x += x_dir;
- else
- break;
- }
-
- if (mystique->dwgreg.sgn.sdy)
- mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK);
- else
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
- }
- break;
-
- default:
- fatal("BITBLT BLK %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK);
- break;
- }
- break;
-
- case DWGCTRL_ATYPE_RPL:
- if (mystique->maccess_running & MACCESS_TLUTLOAD) {
- src_addr = mystique->dwgreg.ar[3];
-
- y = mystique->dwgreg.ydst;
-
- while (mystique->dwgreg.length) {
- uint16_t src = ((uint16_t *)svga->vram)[src_addr & mystique->vram_mask_w];
-
- mystique->lut[y & 0xff].r = (src >> 11) << 3;
- mystique->lut[y & 0xff].g = ((src >> 5) & 0x3f) << 2;
- mystique->lut[y & 0xff].b = (src & 0x1f) << 3;
- src_addr++;
- y++;
- mystique->dwgreg.length--;
- }
- break;
- }
- case DWGCTRL_ATYPE_RSTR:
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BMONOLEF:
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_PATTERN)
- fatal("BITBLT RPL/RSTR BMONOLEF with pattern\n");
-
- src_addr = mystique->dwgreg.ar[3];
-
- for (y = 0; y < mystique->dwgreg.length; y++) {
- uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
- int16_t x = x_start;
-
- while (1) {
- uint32_t byte_addr = (src_addr >> 3) & mystique->vram_mask;
- int bit_offset = src_addr & 7;
-
- if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot &&
- ((svga->vram[byte_addr] & (1 << bit_offset)) || !(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC)) &&
- trans[x & 3]) {
- uint32_t src = (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
- uint32_t dst, old_dst;
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- dst = svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
-
- svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_16:
- dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
-
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_24:
- old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
-
- dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running);// & DWGCTRL_BOP_MASK
-
- *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
- svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- default:
- fatal("BITBLT RPL BMONOLEF PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
- }
- }
-
- if (src_addr == mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
- mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
- src_addr = mystique->dwgreg.ar[3];
- } else
- src_addr += x_dir;
-
- if (x != x_end)
- x += x_dir;
- else
- break;
- }
-
- if (mystique->dwgreg.sgn.sdy)
- mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK);
- else
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
- }
- break;
-
- case DWGCTRL_BLTMOD_BFCOL:
- case DWGCTRL_BLTMOD_BU32RGB:
- src_addr = mystique->dwgreg.ar[3];
-
- for (y = 0; y < mystique->dwgreg.length; y++) {
- uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
- uint32_t old_src_addr = src_addr;
- int16_t x = x_start;
-
- while (1) {
- if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright &&
- mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot &&
- trans[x & 3]) {
- uint32_t src, dst, old_dst;
-
- switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
- case MACCESS_PWIDTH_8:
- src = svga->vram[src_addr & mystique->vram_mask];
- dst = svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
-
- svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_16:
- src = ((uint16_t *)svga->vram)[src_addr & mystique->vram_mask_w];
- dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
-
- ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_24:
- src = *(uint32_t *)&svga->vram[(src_addr * 3) & mystique->vram_mask];
- old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
-
- dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running);
-
- *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
- svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
- break;
-
- case MACCESS_PWIDTH_32:
- src = ((uint32_t *)svga->vram)[src_addr & mystique->vram_mask_l];
- dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l];
-
- dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
-
- ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst;
- svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount;
- break;
-
- default:
- fatal("BITBLT RPL BFCOL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
- }
- }
-
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_PATTERN)
- src_addr = ((src_addr + x_dir) & 7) | (src_addr & ~7);
- else if (src_addr == mystique->dwgreg.ar[0]) {
- mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
- mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
- src_addr = mystique->dwgreg.ar[3];
- } else
- src_addr += x_dir;
-
- if (x != x_end)
- x += x_dir;
- else
- break;
- }
-
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_PATTERN) {
- src_addr = old_src_addr;
- if (mystique->dwgreg.sgn.sdy)
- src_addr = ((src_addr - 32) & 0xe0) | (src_addr & ~0xe0);
- else
- src_addr = ((src_addr + 32) & 0xe0) | (src_addr & ~0xe0);
- }
-
- if (mystique->dwgreg.sgn.sdy)
- mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK);
- else
- mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
- }
- break;
-
- default:
- fatal("BITBLT DWGCTRL_ATYPE_RPL unknown BLTMOD %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
- }
- break;
-
- default:
- /* pclog("Unknown BITBLT atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); */
- break;
- }
-
- mystique->blitter_complete_refcount++;
-}
-
-
-static void
-blit_iload(mystique_t *mystique)
-{
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_RPL:
- case DWGCTRL_ATYPE_RSTR:
- case DWGCTRL_ATYPE_BLK:
- /* pclog("ILOAD BLTMOD DWGCTRL = %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK); */
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BFCOL:
- case DWGCTRL_BLTMOD_BMONOWF:
- case DWGCTRL_BLTMOD_BU24RGB:
- case DWGCTRL_BLTMOD_BU32RGB:
- mystique->dwgreg.length_cur = mystique->dwgreg.length;
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.iload_rem_data = 0;
- mystique->dwgreg.iload_rem_count = 0;
- mystique->busy = 1;
- /* pclog("ILOAD busy\n"); */
- mystique->dwgreg.words = 0;
- break;
-
- default:
- fatal("ILOAD DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
- break;
- }
- break;
-
- default:
- fatal("Unknown ILOAD atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
- }
-}
-
-
-static void
-blit_idump(mystique_t *mystique)
-{
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_RPL:
- mystique->dwgreg.length_cur = mystique->dwgreg.length;
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.src_addr = mystique->dwgreg.ar[3];
- mystique->dwgreg.words = 0;
- mystique->dwgreg.iload_rem_count = 0;
- mystique->dwgreg.iload_rem_data = 0;
- mystique->dwgreg.idump_end_of_line = 0;
- mystique->busy = 1;
- /* pclog("IDUMP ATYPE RPL busy\n"); */
- break;
-
- default:
- fatal("Unknown IDUMP atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
- }
-}
-
-
-static void
-blit_iload_scale(mystique_t *mystique)
-{
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_RPL:
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BUYUV:
- mystique->dwgreg.length_cur = mystique->dwgreg.length;
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.iload_rem_data = 0;
- mystique->dwgreg.iload_rem_count = 0;
- mystique->busy = 1;
- mystique->dwgreg.words = 0;
- /* pclog("ILOAD SCALE ATYPE RPL BLTMOD BUYUV busy\n"); */
- break;
-
- default:
- fatal("ILOAD_SCALE DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
- break;
- }
- break;
-
- default:
- fatal("Unknown ILOAD_SCALE atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
- }
-}
-
-
-static void
-blit_iload_high(mystique_t *mystique)
-{
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_RPL:
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BUYUV:
- mystique->dwgreg.length_cur = mystique->dwgreg.length;
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.iload_rem_data = 0;
- mystique->dwgreg.iload_rem_count = 0;
- mystique->busy = 1;
- mystique->dwgreg.words = 0;
- /* pclog("ILOAD HIGH ATYPE RPL BLTMOD BUYUV busy\n"); */
- break;
-
- default:
- fatal("ILOAD_HIGH DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
- break;
- }
- break;
-
- default:
- fatal("Unknown ILOAD_HIGH atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
- }
-}
-
-
-static
-void blit_iload_highv(mystique_t *mystique)
-{
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
- case DWGCTRL_ATYPE_RPL:
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
- case DWGCTRL_BLTMOD_BUYUV:
- mystique->dwgreg.length_cur = mystique->dwgreg.length;
- mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
- mystique->dwgreg.iload_rem_data = 0;
- mystique->dwgreg.iload_rem_count = 0;
- mystique->busy = 1;
- mystique->dwgreg.words = 0;
- mystique->dwgreg.highv_line = 0;
- mystique->dwgreg.lastpix_r = 0;
- mystique->dwgreg.lastpix_g = 0;
- mystique->dwgreg.lastpix_b = 0;
- /* pclog("ILOAD HIGHV ATYPE RPL BLTMOD BUYUV busy\n"); */
- break;
-
- default:
- fatal("ILOAD_HIGHV DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
- break;
- }
- break;
-
- default:
- fatal("Unknown ILOAD_HIGHV atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
- }
-}
-
-
-static void
-mystique_start_blit(mystique_t *mystique)
-{
- uint64_t start_time = plat_timer_read();
- uint64_t end_time;
-
- mystique->dwgreg.dwgctrl_running = mystique->dwgreg.dwgctrl;
- mystique->maccess_running = mystique->maccess;
-
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_SOLID) {
- int x, y;
-
- for (y = 0; y < 8; y++) {
- for (x = 0; x < 8; x++)
- mystique->dwgreg.pattern[y][x] = 1;
- }
- mystique->dwgreg.src[0] = 0xffffffff;
- mystique->dwgreg.src[1] = 0xffffffff;
- mystique->dwgreg.src[2] = 0xffffffff;
- mystique->dwgreg.src[3] = 0xffffffff;
- }
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_ARZERO) {
- mystique->dwgreg.ar[0] = 0;
- mystique->dwgreg.ar[1] = 0;
- mystique->dwgreg.ar[2] = 0;
- mystique->dwgreg.ar[4] = 0;
- mystique->dwgreg.ar[5] = 0;
- mystique->dwgreg.ar[6] = 0;
- }
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_SGNZERO) {
- mystique->dwgreg.sgn.sdydxl = 0;
- mystique->dwgreg.sgn.scanleft = 0;
- mystique->dwgreg.sgn.sdxl = 0;
- mystique->dwgreg.sgn.sdy = 0;
- mystique->dwgreg.sgn.sdxr = 0;
- }
- if (mystique->dwgreg.dwgctrl_running & DWGCTRL_SHTZERO) {
- mystique->dwgreg.funcnt = 0;
- mystique->dwgreg.stylelen = 0;
- mystique->dwgreg.xoff = 0;
- mystique->dwgreg.yoff = 0;
- }
-
- switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) {
- case DWGCTRL_OPCODE_LINE_OPEN:
- blit_line(mystique, 0);
- break;
-
- case DWGCTRL_OPCODE_AUTOLINE_OPEN:
- blit_autoline(mystique, 0);
- break;
-
- case DWGCTRL_OPCODE_AUTOLINE_CLOSE:
- blit_autoline(mystique, 1);
- break;
-
- case DWGCTRL_OPCODE_TRAP:
- blit_trap(mystique);
- break;
-
- case DWGCTRL_OPCODE_TEXTURE_TRAP:
- blit_texture_trap(mystique);
- break;
-
- case DWGCTRL_OPCODE_ILOAD_HIGH:
- blit_iload_high(mystique);
- break;
-
- case DWGCTRL_OPCODE_BITBLT:
- blit_bitblt(mystique);
- break;
-
- case DWGCTRL_OPCODE_ILOAD:
- blit_iload(mystique);
- break;
-
- case DWGCTRL_OPCODE_IDUMP:
- blit_idump(mystique);
- break;
-
- case DWGCTRL_OPCODE_ILOAD_SCALE:
- blit_iload_scale(mystique);
- break;
-
- case DWGCTRL_OPCODE_ILOAD_HIGHV:
- blit_iload_highv(mystique);
- break;
-
- case DWGCTRL_OPCODE_ILOAD_FILTER:
- /* TODO: Actually implement this. */
- break;
-
- default:
- fatal("mystique_start_blit: unknown blit %08x\n", mystique->dwgreg.dwgctrl_running);
- }
-
- end_time = plat_timer_read();
- mystique->blitter_time += end_time - start_time;
-}
-
-
-static void
-mystique_hwcursor_draw(svga_t *svga, int displine)
-{
- int x;
- uint64_t dat[2];
- int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
-
- if (svga->interlace && svga->hwcursor_oddeven)
- svga->hwcursor_latch.addr += 16;
-
- dat[0] = *(uint64_t *)(&svga->vram[svga->hwcursor_latch.addr]);
- dat[1] = *(uint64_t *)(&svga->vram[svga->hwcursor_latch.addr + 8]);
- svga->hwcursor_latch.addr += 16;
- for (x = 0; x < 64; x ++) {
- if (!(dat[1] & (1ull << 63)))
- buffer32->line[displine][offset + svga->x_add] = (dat[0] & (1ull << 63)) ? 0xffffff : 0;
- else if (dat[0] & (1ull << 63))
- buffer32->line[displine][offset + svga->x_add] ^= 0xffffff;
-
- offset++;
- dat[0] <<= 1;
- dat[1] <<= 1;
- }
-
- if (svga->interlace && !svga->hwcursor_oddeven)
- svga->hwcursor_latch.addr += 16;
-}
-
-
-static
-uint8_t mystique_pci_read(int func, int addr, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
- uint8_t ret = 0x00;
-
- if ((addr >= 0x30) && (addr <= 0x33) && !(mystique->pci_regs[0x43] & 0x40))
- ret = 0x00;
- else switch (addr) {
- case 0x00: ret = 0x2b; break; /*Matrox*/
- case 0x01: ret = 0x10; break;
-
- case 0x02: ret = 0x1a; break; /*MGA-1064SG*/
- case 0x03: ret = 0x05; break;
-
- case PCI_REG_COMMAND:
- ret = mystique->pci_regs[PCI_REG_COMMAND]; break; /*Respond to IO and memory accesses*/
-
- case 0x07: ret = 0 << 1; break; /*Fast DEVSEL timing*/
-
- case 0x08: ret = 0; break; /*Revision ID*/
- case 0x09: ret = 0; break; /*Programming interface*/
-
- case 0x0a: ret = 0x00; break; /*Supports VGA interface*/
- case 0x0b: ret = 0x03; break;
-
- case 0x10: ret = 0x00; break; /*Control aperture*/
- case 0x11: ret = (mystique->ctrl_base >> 8) & 0xc0; break;
- case 0x12: ret = mystique->ctrl_base >> 16; break;
- case 0x13: ret = mystique->ctrl_base >> 24; break;
-
- case 0x14: ret = 0x00; break; /*Linear frame buffer*/
- case 0x16: ret = (mystique->lfb_base >> 16) & 0x80; break;
- case 0x17: ret = mystique->lfb_base >> 24; break;
-
- case 0x18: ret = 0x00; break; /*Pseudo-DMA (ILOAD)*/
- case 0x1a: ret = (mystique->iload_base >> 16) & 0x80; break;
- case 0x1b: ret = mystique->iload_base >> 24; break;
-
- case 0x30: ret = mystique->pci_regs[0x30] & 0x01; break; /*BIOS ROM address*/
- case 0x31: ret = 0x00; break;
- case 0x32: ret = mystique->pci_regs[0x32]; break;
- case 0x33: ret = mystique->pci_regs[0x33]; break;
-
- case 0x3c: ret = mystique->int_line; break;
- case 0x3d: ret = PCI_INTA; break;
-
- case 0x40: ret = mystique->pci_regs[0x40]; break;
- case 0x41: ret = mystique->pci_regs[0x41]; break;
- case 0x42: ret = mystique->pci_regs[0x42]; break;
- case 0x43: ret = mystique->pci_regs[0x43]; break;
-
- case 0x44: ret = mystique->pci_regs[0x44]; break;
- case 0x45: ret = mystique->pci_regs[0x45]; break;
-
- case 0x48: case 0x49: case 0x4a: case 0x4b:
- addr = (mystique->pci_regs[0x44] & 0xfc) | ((mystique->pci_regs[0x45] & 0x3f) << 8) |
- (addr & 3);
- ret = mystique_ctrl_read_b(addr, mystique); break;
- }
-
- return ret;
-}
-
-static void
-mystique_pci_write(int func, int addr, uint8_t val, void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- switch (addr) {
- case PCI_REG_COMMAND:
- mystique->pci_regs[PCI_REG_COMMAND] = val & 0x23;
- mystique_recalc_mapping(mystique);
- break;
-
- case 0x11:
- mystique->ctrl_base = (mystique->ctrl_base & 0xffff0000) | ((val & 0xc0) << 8);
- mystique_recalc_mapping(mystique);
- break;
- case 0x12:
- mystique->ctrl_base = (mystique->ctrl_base & 0xff00c000) | (val << 16);
- mystique_recalc_mapping(mystique);
- break;
- case 0x13:
- mystique->ctrl_base = (mystique->ctrl_base & 0x00ffc000) | (val << 24);
- mystique_recalc_mapping(mystique);
- break;
-
- case 0x16:
- mystique->lfb_base = (mystique->lfb_base & 0xff000000) | ((val & 0x80) << 16);
- mystique_recalc_mapping(mystique);
- break;
- case 0x17:
- mystique->lfb_base = (mystique->lfb_base & 0x00800000) | (val << 24);
- mystique_recalc_mapping(mystique);
- break;
-
- case 0x1a:
- mystique->iload_base = (mystique->iload_base & 0xff000000) | ((val & 0x80) << 16);
- mystique_recalc_mapping(mystique);
- break;
- case 0x1b:
- mystique->iload_base = (mystique->iload_base & 0x00800000) | (val << 24);
- mystique_recalc_mapping(mystique);
- break;
-
- case 0x30: case 0x32: case 0x33:
- if (!(mystique->pci_regs[0x43] & 0x40))
- return;
- mystique->pci_regs[addr] = val;
- if (mystique->pci_regs[0x30] & 0x01) {
- uint32_t addr = (mystique->pci_regs[0x32] << 16) | (mystique->pci_regs[0x33] << 24);
- mem_mapping_set_addr(&mystique->bios_rom.mapping, addr, 0x8000);
- } else
- mem_mapping_disable(&mystique->bios_rom.mapping);
- return;
-
- case 0x3c:
- mystique->int_line = val;
- return;
-
- case 0x40: case 0x41: case 0x42: case 0x43:
- mystique->pci_regs[addr] = val;
- if (addr == 0x43) {
- if (val & 0x40) {
- if (mystique->pci_regs[0x30] & 0x01) {
- uint32_t addr = (mystique->pci_regs[0x32] << 16) | (mystique->pci_regs[0x33] << 24);
- mem_mapping_set_addr(&mystique->bios_rom.mapping, addr, 0x8000);
- } else
- mem_mapping_disable(&mystique->bios_rom.mapping);
- } else
- mem_mapping_set_addr(&mystique->bios_rom.mapping, 0x000c0000, 0x8000);
- }
- break;
-
- case 0x4c: case 0x4d: case 0x4e: case 0x4f:
- mystique->pci_regs[addr-0x20] = val;
- break;
-
- case 0x44: case 0x45:
- mystique->pci_regs[addr] = val;
- break;
-
- case 0x48: case 0x49: case 0x4a: case 0x4b:
- addr = (mystique->pci_regs[0x44] & 0xfc) | ((mystique->pci_regs[0x45] & 0x3f) << 8) |
- (addr & 3);
- mystique_ctrl_write_b(addr, val, mystique);
- break;
- }
-}
-
-
-
-static void *
-mystique_init(const device_t *info)
-{
- int c;
- mystique_t *mystique = malloc(sizeof(mystique_t));
- wchar_t *romfn;
-
- memset(mystique, 0, sizeof(mystique_t));
-
- if (info->local == 1)
- romfn = ROM_MYSTIQUE_220;
- else
- romfn = ROM_MYSTIQUE;
-
- rom_init(&mystique->bios_rom, romfn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
- mem_mapping_disable(&mystique->bios_rom.mapping);
-
- mystique->vram_size = device_get_config_int("memory");
- mystique->vram_mask = (mystique->vram_size << 20) - 1;
- mystique->vram_mask_w = mystique->vram_mask >> 1;
- mystique->vram_mask_l = mystique->vram_mask >> 2;
-
- video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_matrox_mystique);
-
- svga_init(&mystique->svga, mystique, mystique->vram_size << 20,
- mystique_recalctimings,
- mystique_in, mystique_out,
- mystique_hwcursor_draw,
- NULL);
-
- io_sethandler(0x03c0, 0x0020, mystique_in, NULL, NULL, mystique_out, NULL, NULL, mystique);
- mem_mapping_add(&mystique->ctrl_mapping, 0, 0,
- mystique_ctrl_read_b, NULL, mystique_ctrl_read_l,
- mystique_ctrl_write_b, NULL, mystique_ctrl_write_l,
- NULL, 0, mystique);
- mem_mapping_disable(&mystique->ctrl_mapping);
-
- mem_mapping_add(&mystique->lfb_mapping, 0, 0,
- svga_read_linear, svga_readw_linear, svga_readl_linear,
- svga_write_linear, svga_writew_linear, svga_writel_linear,
- NULL, 0, mystique);
- mem_mapping_disable(&mystique->lfb_mapping);
-
- mem_mapping_add(&mystique->iload_mapping, 0, 0,
- mystique_iload_read_b, NULL, mystique_iload_read_l,
- mystique_iload_write_b, NULL, mystique_iload_write_l,
- NULL, 0, mystique);
- mem_mapping_disable(&mystique->iload_mapping);
-
- mystique->card = pci_add_card(PCI_ADD_VIDEO, mystique_pci_read, mystique_pci_write, mystique);
- mystique->pci_regs[0x2c] = mystique->bios_rom.rom[0x7ff8];
- mystique->pci_regs[0x2d] = mystique->bios_rom.rom[0x7ff8];
- mystique->pci_regs[0x2e] = mystique->bios_rom.rom[0x7ff8];
- mystique->pci_regs[0x2f] = mystique->bios_rom.rom[0x7ff8];
-
- mystique->svga.miscout = 1;
- mystique->pci_regs[0x41] = 0x01; /* vgaboot = 1 */
- mystique->pci_regs[0x43] = 0x40; /* biosen = 1 */
-
- for (c = 0; c < 256; c++) {
- dither5[c][0][0] = c >> 3;
- dither5[c][1][1] = (c + 2) >> 3;
- dither5[c][1][0] = (c + 4) >> 3;
- dither5[c][0][1] = (c + 6) >> 3;
-
- if (dither5[c][1][1] > 31)
- dither5[c][1][1] = 31;
- if (dither5[c][1][0] > 31)
- dither5[c][1][0] = 31;
- if (dither5[c][0][1] > 31)
- dither5[c][0][1] = 31;
-
- dither6[c][0][0] = c >> 2;
- dither6[c][1][1] = (c + 1) >> 2;
- dither6[c][1][0] = (c + 2) >> 2;
- dither6[c][0][1] = (c + 3) >> 2;
-
- if (dither6[c][1][1] > 63)
- dither6[c][1][1] = 63;
- if (dither6[c][1][0] > 63)
- dither6[c][1][0] = 63;
- if (dither6[c][0][1] > 63)
- dither6[c][0][1] = 63;
- }
-
- mystique->wake_fifo_thread = thread_create_event();
- mystique->fifo_not_full_event = thread_create_event();
- mystique->fifo_thread = thread_create(fifo_thread, mystique);
- mystique->dma.lock = thread_create_mutex(L"86Box.MGAMutex");
-
- timer_add(&mystique->wake_timer, mystique_wake_timer, (void *)mystique, 0);
- timer_add(&mystique->softrap_pending_timer, mystique_softrap_pending_timer, (void *)mystique, 1);
-
- mystique->status = STATUS_ENDPRDMASTS;
-
- return mystique;
-}
-
-
-static void
-mystique_close(void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- thread_kill(mystique->fifo_thread);
- thread_destroy_event(mystique->wake_fifo_thread);
- thread_destroy_event(mystique->fifo_not_full_event);
- thread_close_mutex(mystique->dma.lock);
-
- svga_close(&mystique->svga);
-
- free(mystique);
-}
-
-
-static int
-mystique_available(void)
-{
- return rom_present(ROM_MYSTIQUE);
-}
-
-
-static int
-mystique_220_available(void)
-{
- return rom_present(ROM_MYSTIQUE_220);
-}
-
-
-static void
-mystique_speed_changed(void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- svga_recalctimings(&mystique->svga);
-}
-
-
-static void
-mystique_force_redraw(void *p)
-{
- mystique_t *mystique = (mystique_t *)p;
-
- mystique->svga.fullchange = changeframecount;
-}
-
-
-static const device_config_t mystique_config[] =
-{
- {
- .name = "memory",
- .description = "Memory size",
- .type = CONFIG_SELECTION,
- .selection =
- {
- {
- .description = "2 MB",
- .value = 2
- },
- {
- .description = "4 MB",
- .value = 4
- },
- {
- .description = "8 MB",
- .value = 8
- },
- {
- .description = ""
- }
- },
- .default_int = 8
- },
- {
- .type = -1
- }
-};
-
-
-const device_t mystique_device =
-{
- "Matrox Mystique",
- DEVICE_PCI,
- 0,
- mystique_init,
- mystique_close,
- NULL,
- mystique_available,
- mystique_speed_changed,
- mystique_force_redraw,
- mystique_config
-};
-
-
-const device_t mystique_220_device =
-{
- "Matrox Mystique 220",
- DEVICE_PCI,
- 1,
- mystique_init,
- mystique_close,
- NULL,
- mystique_220_available,
- mystique_speed_changed,
- mystique_force_redraw,
- mystique_config
-};
diff --git a/src/video/vid_mga.c b/src/video/vid_mga.c
index 332dfb09a..fd27f7a54 100644
--- a/src/video/vid_mga.c
+++ b/src/video/vid_mga.c
@@ -4765,7 +4765,7 @@ mystique_pci_write(int func, int addr, uint8_t val, void *p)
case 0x48: case 0x49: case 0x4a: case 0x4b:
addr = (mystique->pci_regs[0x44] & 0xfc) | ((mystique->pci_regs[0x45] & 0x3f) << 8) |
(addr & 3);
- pclog("mystique_ctrl_write_b(%04X, %02X)\n", addr, val);
+ /* pclog("mystique_ctrl_write_b(%04X, %02X)\n", addr, val); */
mystique_ctrl_write_b(addr, val, mystique);
break;
}
diff --git a/src/win/86Box.rc b/src/win/86Box.rc
index 851b7d287..fe204a04b 100644
--- a/src/win/86Box.rc
+++ b/src/win/86Box.rc
@@ -474,6 +474,9 @@ BEGIN
CONTROL "ISABugger device",IDC_CHECK_BUGGER,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,7,80,94,10
+ CONTROL "POST card",IDC_CHECK_POSTCARD,"Button",
+ BS_AUTOCHECKBOX | WS_TABSTOP,147,80,94,10
+
LTEXT "ISA RTC",IDT_1767,7,99,48,10
COMBOBOX IDC_COMBO_ISARTC,64,98,155,120,
CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw
index d4d7ecc0b..bac5a2839 100644
--- a/src/win/Makefile.mingw
+++ b/src/win/Makefile.mingw
@@ -597,7 +597,7 @@ MCHOBJ := machine.o machine_table.o \
m_at_286_386sx.o m_at_386dx_486.o \
m_at_socket4_5.o m_at_socket7_s7.o
-DEVOBJ := bugger.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \
+DEVOBJ := bugger.o hwm.o hwm_w83781d.o ibm_5161.o isamem.o isartc.o lpt.o postcard.o $(SERIAL) \
sio_acc3221.o \
sio_fdc37c66x.o sio_fdc37c669.o \
sio_fdc37c93x.o \
@@ -605,6 +605,7 @@ DEVOBJ := bugger.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \
sio_w83787f.o \
sio_w83877f.o sio_w83977f.o \
sio_um8669f.o \
+ smbus.o \
keyboard.o \
keyboard_xt.o keyboard_at.o \
gameport.o \
diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw
index 27588540a..8e8b82a5d 100644
--- a/src/win/Makefile_ndr.mingw
+++ b/src/win/Makefile_ndr.mingw
@@ -602,7 +602,7 @@ MCHOBJ := machine.o machine_table.o \
m_at_286_386sx.o m_at_386dx_486.o \
m_at_socket4_5.o m_at_socket7_s7.o
-DEVOBJ := bugger.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \
+DEVOBJ := bugger.o hwm.o hwm_w83781d.o ibm_5161.o isamem.o isartc.o lpt.o postcard.o $(SERIAL) \
sio_acc3221.o \
sio_fdc37c66x.o sio_fdc37c669.o \
sio_fdc37c93x.o \
@@ -610,6 +610,7 @@ DEVOBJ := bugger.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \
sio_w83787f.o \
sio_w83877f.o sio_w83977f.o \
sio_um8669f.o \
+ smbus.o \
keyboard.o \
keyboard_xt.o keyboard_at.o \
gameport.o \
diff --git a/src/win/resource.h b/src/win/resource.h
index 8e11ed62a..c4ffc2728 100644
--- a/src/win/resource.h
+++ b/src/win/resource.h
@@ -175,7 +175,7 @@
#define IDC_CHECK_IDE_QUA 1127
#define IDC_BUTTON_IDE_QUA 1128
#define IDC_CHECK_BUGGER 1129
-#define IDC_CONFIGURE_BUGGER 1130
+#define IDC_CHECK_POSTCARD 1130
#define IDC_COMBO_ISARTC 1131
#define IDC_CONFIGURE_ISARTC 1132
#define IDC_GROUP_ISAMEM 1140
diff --git a/src/win/win_settings.c b/src/win/win_settings.c
index 0d79a7124..6d5476295 100644
--- a/src/win/win_settings.c
+++ b/src/win/win_settings.c
@@ -97,6 +97,7 @@ static int temp_serial[2], temp_lpt[3];
/* Other peripherals category */
static int temp_hdc, temp_scsi_card, temp_ide_ter, temp_ide_qua;
static int temp_bugger;
+static int temp_postcard;
static int temp_isartc;
static int temp_isamem[ISAMEM_MAX];
@@ -248,6 +249,7 @@ win_settings_init(void)
temp_ide_ter = ide_ter_enabled;
temp_ide_qua = ide_qua_enabled;
temp_bugger = bugger_enabled;
+ temp_postcard = postcard_enabled;
temp_isartc = isartc_type;
/* ISA memory boards. */
@@ -356,6 +358,7 @@ win_settings_changed(void)
i = i || (temp_ide_ter != ide_ter_enabled);
i = i || (temp_ide_qua != ide_qua_enabled);
i = i || (temp_bugger != bugger_enabled);
+ i = i || (temp_postcard != postcard_enabled);
i = i || (temp_isartc != isartc_type);
/* ISA memory boards. */
@@ -460,6 +463,7 @@ win_settings_save(void)
ide_ter_enabled = temp_ide_ter;
ide_qua_enabled = temp_ide_qua;
bugger_enabled = temp_bugger;
+ postcard_enabled = temp_postcard;
isartc_type = temp_isartc;
/* ISA memory boards. */
@@ -1594,6 +1598,9 @@ win_settings_peripherals_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lPa
h=GetDlgItem(hdlg, IDC_CHECK_BUGGER);
SendMessage(h, BM_SETCHECK, temp_bugger, 0);
+ h=GetDlgItem(hdlg, IDC_CHECK_POSTCARD);
+ SendMessage(h, BM_SETCHECK, temp_postcard, 0);
+
/* Populate the ISA RTC card dropdown. */
e = 0;
h = GetDlgItem(hdlg, IDC_COMBO_ISARTC);
@@ -1797,6 +1804,9 @@ win_settings_peripherals_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lPa
h = GetDlgItem(hdlg, IDC_CHECK_BUGGER);
temp_bugger = SendMessage(h, BM_GETCHECK, 0, 0);
+ h = GetDlgItem(hdlg, IDC_CHECK_POSTCARD);
+ temp_postcard = SendMessage(h, BM_GETCHECK, 0, 0);
+
free(stransi);
free(lptsTemp);