From ab154faf88ace1bba5503d1b20d6796f6a2f0852 Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Thu, 4 Aug 2022 16:17:55 +0600 Subject: [PATCH 1/3] x86: mov r, DR6 now always writes bits 4-11 and bits 16-31 as 1 --- src/cpu/x86_ops_mov_ctrl.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86_ops_mov_ctrl.h b/src/cpu/x86_ops_mov_ctrl.h index 667ea9d31..0d973338e 100644 --- a/src/cpu/x86_ops_mov_ctrl.h +++ b/src/cpu/x86_ops_mov_ctrl.h @@ -91,7 +91,7 @@ static int opMOV_r_DRx_a16(uint32_t fetchdat) return 1; } fetch_ea_16(fetchdat); - cpu_state.regs[cpu_rm].l = dr[cpu_reg]; + cpu_state.regs[cpu_rm].l = dr[cpu_reg] | (cpu_reg == 6 ? 0xffff0ff0u : 0); CLOCK_CYCLES(6); PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0); return 0; @@ -104,7 +104,7 @@ static int opMOV_r_DRx_a32(uint32_t fetchdat) return 1; } fetch_ea_32(fetchdat); - cpu_state.regs[cpu_rm].l = dr[cpu_reg]; + cpu_state.regs[cpu_rm].l = dr[cpu_reg] | (cpu_reg == 6 ? 0xffff0ff0u : 0); CLOCK_CYCLES(6); PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1); return 0; From 64195df373f28de8bc806781e2873773e7eda047 Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Thu, 4 Aug 2022 16:43:21 +0600 Subject: [PATCH 2/3] 386: set bit 14 of DR6 to 1 on INT 01 with TF set --- src/cpu/386.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/386.c b/src/cpu/386.c index 5f30e1199..d6d4ded16 100644 --- a/src/cpu/386.c +++ b/src/cpu/386.c @@ -196,6 +196,7 @@ exec386(int cycs) enter_smm_check(0); else if (trap) { flags_rebuild(); + dr[6] |= 0x4000; if (msw&1) pmodeint(1,0); else { From c743d360282736f038510997b909708245dfe7e6 Mon Sep 17 00:00:00 2001 From: Cacodemon345 Date: Thu, 4 Aug 2022 18:04:40 +0600 Subject: [PATCH 3/3] 386: Set BS flag in DR6 other interpreter as well --- src/cpu/386_dynarec.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/386_dynarec.c b/src/cpu/386_dynarec.c index 3e4d91ed2..f90ce5f80 100644 --- a/src/cpu/386_dynarec.c +++ b/src/cpu/386_dynarec.c @@ -404,6 +404,7 @@ exec386_dynarec_int(void) oldcs = CS; #endif cpu_state.oldpc = cpu_state.pc; + dr[6] |= 0x4000; x86_int(1); }