diff --git a/src/mem/catalyst_flash.c b/src/mem/catalyst_flash.c index bfc54e4b4..b49c0671c 100644 --- a/src/mem/catalyst_flash.c +++ b/src/mem/catalyst_flash.c @@ -30,14 +30,11 @@ #include <86box/nvr.h> #include <86box/plat.h> +#define FLAG_WORD 4 +#define FLAG_BXB 2 +#define FLAG_INV_A16 1 -#define FLAG_WORD 4 -#define FLAG_BXB 2 -#define FLAG_INV_A16 1 - - -enum -{ +enum { BLOCK_MAIN1, BLOCK_MAIN2, BLOCK_DATA1, @@ -46,88 +43,80 @@ enum BLOCKS_NUM }; -enum -{ - CMD_SET_READ = 0x00, +enum { + CMD_SET_READ = 0x00, CMD_READ_SIGNATURE = 0x90, - CMD_ERASE = 0x20, - CMD_ERASE_CONFIRM = 0x20, - CMD_ERASE_VERIFY = 0xA0, - CMD_PROGRAM = 0x40, + CMD_ERASE = 0x20, + CMD_ERASE_CONFIRM = 0x20, + CMD_ERASE_VERIFY = 0xA0, + CMD_PROGRAM = 0x40, CMD_PROGRAM_VERIFY = 0xC0, - CMD_RESET = 0xFF + CMD_RESET = 0xFF }; +typedef struct flash_t { + uint8_t command, pad, + pad0, pad1, + *array; -typedef struct flash_t -{ - uint8_t command, pad, - pad0, pad1, - *array; - - mem_mapping_t mapping, mapping_h[2]; + mem_mapping_t mapping, mapping_h[2]; } flash_t; - -static char flash_path[1024]; - +static char flash_path[1024]; static uint8_t flash_read(uint32_t addr, void *p) { flash_t *dev = (flash_t *) p; - uint8_t ret = 0xff; + uint8_t ret = 0xff; addr &= biosmask; switch (dev->command) { - case CMD_ERASE_VERIFY: - case CMD_PROGRAM_VERIFY: - case CMD_RESET: - case CMD_SET_READ: - ret = dev->array[addr]; - break; + case CMD_ERASE_VERIFY: + case CMD_PROGRAM_VERIFY: + case CMD_RESET: + case CMD_SET_READ: + ret = dev->array[addr]; + break; - case CMD_READ_SIGNATURE: - if (addr == 0x00000) - ret = 0x31; /* CATALYST */ - else if (addr == 0x00001) - ret = 0xB4; /* 28F010 */ - break; + case CMD_READ_SIGNATURE: + if (addr == 0x00000) + ret = 0x31; /* CATALYST */ + else if (addr == 0x00001) + ret = 0xB4; /* 28F010 */ + break; } return ret; } - static uint16_t flash_readw(uint32_t addr, void *p) { - flash_t *dev = (flash_t *)p; + flash_t *dev = (flash_t *) p; uint16_t *q; addr &= biosmask; - q = (uint16_t *)&(dev->array[addr]); + q = (uint16_t *) &(dev->array[addr]); return *q; } - static uint32_t flash_readl(uint32_t addr, void *p) { - flash_t *dev = (flash_t *)p; + flash_t *dev = (flash_t *) p; uint32_t *q; addr &= biosmask; - q = (uint32_t *)&(dev->array[addr]); + q = (uint32_t *) &(dev->array[addr]); return *q; } - static void flash_write(uint32_t addr, uint8_t val, void *p) { @@ -136,55 +125,51 @@ flash_write(uint32_t addr, uint8_t val, void *p) addr &= biosmask; switch (dev->command) { - case CMD_ERASE: - if (val == CMD_ERASE_CONFIRM) - memset(dev->array, 0xff, biosmask + 1); - break; + case CMD_ERASE: + if (val == CMD_ERASE_CONFIRM) + memset(dev->array, 0xff, biosmask + 1); + break; - case CMD_PROGRAM: - dev->array[addr] = val; - break; + case CMD_PROGRAM: + dev->array[addr] = val; + break; - default: - dev->command = val; - break; + default: + dev->command = val; + break; } } - static void flash_writew(uint32_t addr, uint16_t val, void *p) { } - static void flash_writel(uint32_t addr, uint32_t val, void *p) { } - static void catalyst_flash_add_mappings(flash_t *dev) { memcpy(dev->array, rom, biosmask + 1); mem_mapping_add(&dev->mapping, 0xe0000, 0x20000, - flash_read, flash_readw, flash_readl, - flash_write, flash_writew, flash_writel, - dev->array, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, (void *) dev); + flash_read, flash_readw, flash_readl, + flash_write, flash_writew, flash_writel, + dev->array, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev); mem_mapping_add(&(dev->mapping_h[0]), 0xfffc0000, 0x20000, - flash_read, flash_readw, flash_readl, - flash_write, flash_writew, flash_writel, - dev->array, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, (void *) dev); + flash_read, flash_readw, flash_readl, + flash_write, flash_writew, flash_writel, + dev->array, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev); mem_mapping_add(&(dev->mapping_h[1]), 0xfffe0000, 0x20000, - flash_read, flash_readw, flash_readl, - flash_write, flash_writew, flash_writel, - dev->array, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, (void *) dev); + flash_read, flash_readw, flash_readl, + flash_write, flash_writew, flash_writel, + dev->array, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev); } - static void catalyst_flash_reset(void *priv) { @@ -193,11 +178,10 @@ catalyst_flash_reset(void *priv) dev->command = CMD_RESET; } - static void * catalyst_flash_init(const device_t *info) { - FILE *f; + FILE *f; flash_t *dev; dev = malloc(sizeof(flash_t)); @@ -217,19 +201,18 @@ catalyst_flash_init(const device_t *info) f = nvr_fopen(flash_path, "rb"); if (f) { - (void) !fread(dev->array, 0x20000, 1, f); - fclose(f); + (void) !fread(dev->array, 0x20000, 1, f); + fclose(f); } return dev; } - static void catalyst_flash_close(void *p) { - FILE *f; - flash_t *dev = (flash_t *)p; + FILE *f; + flash_t *dev = (flash_t *) p; f = nvr_fopen(flash_path, "wb"); fwrite(dev->array, 0x20000, 1, f); @@ -241,17 +224,16 @@ catalyst_flash_close(void *p) free(dev); } - const device_t catalyst_flash_device = { - .name = "Catalyst 28F010-D Flash BIOS", + .name = "Catalyst 28F010-D Flash BIOS", .internal_name = "catalyst_flash", - .flags = DEVICE_PCI, - .local = 0, - .init = catalyst_flash_init, - .close = catalyst_flash_close, - .reset = catalyst_flash_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = catalyst_flash_init, + .close = catalyst_flash_close, + .reset = catalyst_flash_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/mem/i2c_eeprom.c b/src/mem/i2c_eeprom.c index dceac93a5..9a2e2876e 100644 --- a/src/mem/i2c_eeprom.c +++ b/src/mem/i2c_eeprom.c @@ -24,36 +24,32 @@ #include <86box/86box.h> #include <86box/i2c.h> - typedef struct { - void *i2c; - uint8_t addr, *data, writable; + void *i2c; + uint8_t addr, *data, writable; - uint32_t addr_mask, addr_register; - uint8_t addr_len, addr_pos; + uint32_t addr_mask, addr_register; + uint8_t addr_len, addr_pos; } i2c_eeprom_t; - #ifdef ENABLE_I2C_EEPROM_LOG int i2c_eeprom_do_log = ENABLE_I2C_EEPROM_LOG; - static void i2c_eeprom_log(const char *fmt, ...) { va_list ap; if (i2c_eeprom_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define i2c_eeprom_log(fmt, ...) +# define i2c_eeprom_log(fmt, ...) #endif - static uint8_t i2c_eeprom_start(void *bus, uint8_t addr, uint8_t read, void *priv) { @@ -62,19 +58,18 @@ i2c_eeprom_start(void *bus, uint8_t addr, uint8_t read, void *priv) i2c_eeprom_log("I2C EEPROM %s %02X: start()\n", i2c_getbusname(dev->i2c), dev->addr); if (!read) { - dev->addr_pos = 0; - dev->addr_register = (addr << dev->addr_len) & dev->addr_mask; + dev->addr_pos = 0; + dev->addr_register = (addr << dev->addr_len) & dev->addr_mask; } return 1; } - static uint8_t i2c_eeprom_read(void *bus, uint8_t addr, void *priv) { i2c_eeprom_t *dev = (i2c_eeprom_t *) priv; - uint8_t ret = dev->data[dev->addr_register]; + uint8_t ret = dev->data[dev->addr_register]; i2c_eeprom_log("I2C EEPROM %s %02X: read(%06X) = %02X\n", i2c_getbusname(dev->i2c), dev->addr, dev->addr_register, ret); dev->addr_register++; @@ -83,33 +78,31 @@ i2c_eeprom_read(void *bus, uint8_t addr, void *priv) return ret; } - static uint8_t i2c_eeprom_write(void *bus, uint8_t addr, uint8_t data, void *priv) { i2c_eeprom_t *dev = (i2c_eeprom_t *) priv; if (dev->addr_pos < dev->addr_len) { - dev->addr_register <<= 8; - dev->addr_register |= data; - dev->addr_register &= (1 << dev->addr_len) - 1; - dev->addr_register |= addr << dev->addr_len; - dev->addr_register &= dev->addr_mask; - i2c_eeprom_log("I2C EEPROM %s %02X: write(address, %06X)\n", i2c_getbusname(dev->i2c), dev->addr, dev->addr_register); - dev->addr_pos += 8; + dev->addr_register <<= 8; + dev->addr_register |= data; + dev->addr_register &= (1 << dev->addr_len) - 1; + dev->addr_register |= addr << dev->addr_len; + dev->addr_register &= dev->addr_mask; + i2c_eeprom_log("I2C EEPROM %s %02X: write(address, %06X)\n", i2c_getbusname(dev->i2c), dev->addr, dev->addr_register); + dev->addr_pos += 8; } else { - i2c_eeprom_log("I2C EEPROM %s %02X: write(%06X, %02X) = %d\n", i2c_getbusname(dev->i2c), dev->addr, dev->addr_register, data, !!dev->writable); - if (dev->writable) - dev->data[dev->addr_register] = data; - dev->addr_register++; - dev->addr_register &= dev->addr_mask; /* roll-over */ - return dev->writable; + i2c_eeprom_log("I2C EEPROM %s %02X: write(%06X, %02X) = %d\n", i2c_getbusname(dev->i2c), dev->addr, dev->addr_register, data, !!dev->writable); + if (dev->writable) + dev->data[dev->addr_register] = data; + dev->addr_register++; + dev->addr_register &= dev->addr_mask; /* roll-over */ + return dev->writable; } return 1; } - static void i2c_eeprom_stop(void *bus, uint8_t addr, void *priv) { @@ -120,17 +113,15 @@ i2c_eeprom_stop(void *bus, uint8_t addr, void *priv) dev->addr_pos = 0; } - uint8_t log2i(uint32_t i) { uint8_t ret = 0; while ((i >>= 1)) - ret++; + ret++; return ret; } - void * i2c_eeprom_init(void *i2c, uint8_t addr, uint8_t *data, uint32_t size, uint8_t writable) { @@ -140,17 +131,17 @@ i2c_eeprom_init(void *i2c, uint8_t addr, uint8_t *data, uint32_t size, uint8_t w /* Round size up to the next power of 2. */ uint32_t pow_size = 1 << log2i(size); if (pow_size < size) - size = pow_size << 1; + size = pow_size << 1; size &= 0x7fffff; /* address space limit of 8 MB = 7 bits from I2C address + 16 bits */ i2c_eeprom_log("I2C EEPROM %s %02X: init(%d, %d)\n", i2c_getbusname(i2c), addr, size, writable); - dev->i2c = i2c; - dev->addr = addr; - dev->data = data; + dev->i2c = i2c; + dev->addr = addr; + dev->data = data; dev->writable = writable; - dev->addr_len = (size >= 4096) ? 16 : 8; /* use 16-bit addresses on 24C32 and above */ + dev->addr_len = (size >= 4096) ? 16 : 8; /* use 16-bit addresses on 24C32 and above */ dev->addr_mask = size - 1; i2c_sethandler(dev->i2c, dev->addr & ~(dev->addr_mask >> dev->addr_len), (dev->addr_mask >> dev->addr_len) + 1, i2c_eeprom_start, i2c_eeprom_read, i2c_eeprom_write, i2c_eeprom_stop, dev); @@ -158,7 +149,6 @@ i2c_eeprom_init(void *i2c, uint8_t addr, uint8_t *data, uint32_t size, uint8_t w return dev; } - void i2c_eeprom_close(void *dev_handle) { diff --git a/src/mem/intel_flash.c b/src/mem/intel_flash.c index 40a7581d7..bd24f5bcc 100644 --- a/src/mem/intel_flash.c +++ b/src/mem/intel_flash.c @@ -30,14 +30,11 @@ #include <86box/nvr.h> #include <86box/plat.h> +#define FLAG_WORD 4 +#define FLAG_BXB 2 +#define FLAG_INV_A16 1 -#define FLAG_WORD 4 -#define FLAG_BXB 2 -#define FLAG_INV_A16 1 - - -enum -{ +enum { BLOCK_MAIN1, BLOCK_MAIN2, BLOCK_MAIN3, @@ -48,239 +45,231 @@ enum BLOCKS_NUM }; -enum -{ - CMD_READ_ARRAY = 0xff, - CMD_IID = 0x90, - CMD_READ_STATUS = 0x70, - CMD_CLEAR_STATUS = 0x50, - CMD_ERASE_SETUP = 0x20, - CMD_ERASE_CONFIRM = 0xd0, - CMD_ERASE_SUSPEND = 0xb0, - CMD_PROGRAM_SETUP = 0x40, +enum { + CMD_READ_ARRAY = 0xff, + CMD_IID = 0x90, + CMD_READ_STATUS = 0x70, + CMD_CLEAR_STATUS = 0x50, + CMD_ERASE_SETUP = 0x20, + CMD_ERASE_CONFIRM = 0xd0, + CMD_ERASE_SUSPEND = 0xb0, + CMD_PROGRAM_SETUP = 0x40, CMD_PROGRAM_SETUP_ALT = 0x10 }; +typedef struct flash_t { + uint8_t command, status, + pad, flags, + *array; -typedef struct flash_t -{ - uint8_t command, status, - pad, flags, - *array; + uint16_t flash_id, pad16; - uint16_t flash_id, pad16; + uint32_t program_addr, + block_start[BLOCKS_NUM], block_end[BLOCKS_NUM], + block_len[BLOCKS_NUM]; - uint32_t program_addr, - block_start[BLOCKS_NUM], block_end[BLOCKS_NUM], - block_len[BLOCKS_NUM]; - - mem_mapping_t mapping[4], mapping_h[16]; + mem_mapping_t mapping[4], mapping_h[16]; } flash_t; - -static char flash_path[1024]; - +static char flash_path[1024]; static uint8_t flash_read(uint32_t addr, void *p) { flash_t *dev = (flash_t *) p; - uint8_t ret = 0xff; + uint8_t ret = 0xff; if (dev->flags & FLAG_INV_A16) - addr ^= 0x10000; + addr ^= 0x10000; addr &= biosmask; switch (dev->command) { - case CMD_READ_ARRAY: - default: - ret = dev->array[addr]; - break; + case CMD_READ_ARRAY: + default: + ret = dev->array[addr]; + break; - case CMD_IID: - if (addr & 1) - ret = dev->flash_id & 0xff; - else - ret = 0x89; - break; + case CMD_IID: + if (addr & 1) + ret = dev->flash_id & 0xff; + else + ret = 0x89; + break; - case CMD_READ_STATUS: - ret = dev->status; - break; + case CMD_READ_STATUS: + ret = dev->status; + break; } return ret; } - static uint16_t flash_readw(uint32_t addr, void *p) { - flash_t *dev = (flash_t *) p; + flash_t *dev = (flash_t *) p; uint16_t *q; - uint16_t ret = 0xffff; + uint16_t ret = 0xffff; if (dev->flags & FLAG_INV_A16) - addr ^= 0x10000; + addr ^= 0x10000; addr &= biosmask; if (dev->flags & FLAG_WORD) - addr &= 0xfffffffe; + addr &= 0xfffffffe; - q = (uint16_t *)&(dev->array[addr]); + q = (uint16_t *) &(dev->array[addr]); ret = *q; - if (dev->flags & FLAG_WORD) switch (dev->command) { - case CMD_READ_ARRAY: - default: - break; + if (dev->flags & FLAG_WORD) + switch (dev->command) { + case CMD_READ_ARRAY: + default: + break; - case CMD_IID: - if (addr & 2) - ret = dev->flash_id; - else - ret = 0x0089; - break; + case CMD_IID: + if (addr & 2) + ret = dev->flash_id; + else + ret = 0x0089; + break; - case CMD_READ_STATUS: - ret = dev->status; - break; - } + case CMD_READ_STATUS: + ret = dev->status; + break; + } return ret; } - static uint32_t flash_readl(uint32_t addr, void *p) { - flash_t *dev = (flash_t *)p; + flash_t *dev = (flash_t *) p; uint32_t *q; if (dev->flags & FLAG_INV_A16) - addr ^= 0x10000; + addr ^= 0x10000; addr &= biosmask; - q = (uint32_t *)&(dev->array[addr]); + q = (uint32_t *) &(dev->array[addr]); return *q; } - static void flash_write(uint32_t addr, uint8_t val, void *p) { flash_t *dev = (flash_t *) p; - int i; + int i; uint32_t bb_mask = biosmask & 0xffffe000; if (biosmask == 0x7ffff) - bb_mask &= 0xffff8000; + bb_mask &= 0xffff8000; else if (biosmask == 0x3ffff) - bb_mask &= 0xffffc000; + bb_mask &= 0xffffc000; if (dev->flags & FLAG_INV_A16) - addr ^= 0x10000; + addr ^= 0x10000; addr &= biosmask; switch (dev->command) { - case CMD_ERASE_SETUP: - if (val == CMD_ERASE_CONFIRM) { - for (i = 0; i < 6; i++) { - if ((i == dev->program_addr) && (addr >= dev->block_start[i]) && (addr <= dev->block_end[i])) - memset(&(dev->array[dev->block_start[i]]), 0xff, dev->block_len[i]); - } + case CMD_ERASE_SETUP: + if (val == CMD_ERASE_CONFIRM) { + for (i = 0; i < 6; i++) { + if ((i == dev->program_addr) && (addr >= dev->block_start[i]) && (addr <= dev->block_end[i])) + memset(&(dev->array[dev->block_start[i]]), 0xff, dev->block_len[i]); + } - dev->status = 0x80; - } - dev->command = CMD_READ_STATUS; - break; + dev->status = 0x80; + } + dev->command = CMD_READ_STATUS; + break; - case CMD_PROGRAM_SETUP: - case CMD_PROGRAM_SETUP_ALT: - if (((addr & bb_mask) != (dev->block_start[6] & bb_mask)) && (addr == dev->program_addr)) - dev->array[addr] = val; - dev->command = CMD_READ_STATUS; - dev->status = 0x80; - break; + case CMD_PROGRAM_SETUP: + case CMD_PROGRAM_SETUP_ALT: + if (((addr & bb_mask) != (dev->block_start[6] & bb_mask)) && (addr == dev->program_addr)) + dev->array[addr] = val; + dev->command = CMD_READ_STATUS; + dev->status = 0x80; + break; - default: - dev->command = val; - switch (val) { - case CMD_CLEAR_STATUS: - dev->status = 0; - break; - case CMD_ERASE_SETUP: - for (i = 0; i < 7; i++) { - if ((addr >= dev->block_start[i]) && (addr <= dev->block_end[i])) - dev->program_addr = i; - } - break; - case CMD_PROGRAM_SETUP: - case CMD_PROGRAM_SETUP_ALT: - dev->program_addr = addr; - break; - } + default: + dev->command = val; + switch (val) { + case CMD_CLEAR_STATUS: + dev->status = 0; + break; + case CMD_ERASE_SETUP: + for (i = 0; i < 7; i++) { + if ((addr >= dev->block_start[i]) && (addr <= dev->block_end[i])) + dev->program_addr = i; + } + break; + case CMD_PROGRAM_SETUP: + case CMD_PROGRAM_SETUP_ALT: + dev->program_addr = addr; + break; + } } } - static void flash_writew(uint32_t addr, uint16_t val, void *p) { flash_t *dev = (flash_t *) p; - int i; + int i; uint32_t bb_mask = biosmask & 0xffffe000; if (biosmask == 0x7ffff) - bb_mask &= 0xffff8000; + bb_mask &= 0xffff8000; else if (biosmask == 0x3ffff) - bb_mask &= 0xffffc000; + bb_mask &= 0xffffc000; if (dev->flags & FLAG_INV_A16) - addr ^= 0x10000; + addr ^= 0x10000; addr &= biosmask; - if (dev->flags & FLAG_WORD) switch (dev->command) { - case CMD_ERASE_SETUP: - if (val == CMD_ERASE_CONFIRM) { - for (i = 0; i < 6; i++) { - if ((i == dev->program_addr) && (addr >= dev->block_start[i]) && (addr <= dev->block_end[i])) - memset(&(dev->array[dev->block_start[i]]), 0xff, dev->block_len[i]); - } + if (dev->flags & FLAG_WORD) + switch (dev->command) { + case CMD_ERASE_SETUP: + if (val == CMD_ERASE_CONFIRM) { + for (i = 0; i < 6; i++) { + if ((i == dev->program_addr) && (addr >= dev->block_start[i]) && (addr <= dev->block_end[i])) + memset(&(dev->array[dev->block_start[i]]), 0xff, dev->block_len[i]); + } - dev->status = 0x80; - } - dev->command = CMD_READ_STATUS; - break; + dev->status = 0x80; + } + dev->command = CMD_READ_STATUS; + break; - case CMD_PROGRAM_SETUP: - case CMD_PROGRAM_SETUP_ALT: - if (((addr & bb_mask) != (dev->block_start[6] & bb_mask)) && (addr == dev->program_addr)) - *(uint16_t *) (&dev->array[addr]) = val; - dev->command = CMD_READ_STATUS; - dev->status = 0x80; - break; + case CMD_PROGRAM_SETUP: + case CMD_PROGRAM_SETUP_ALT: + if (((addr & bb_mask) != (dev->block_start[6] & bb_mask)) && (addr == dev->program_addr)) + *(uint16_t *) (&dev->array[addr]) = val; + dev->command = CMD_READ_STATUS; + dev->status = 0x80; + break; - default: - dev->command = val & 0xff; - switch (val) { - case CMD_CLEAR_STATUS: - dev->status = 0; - break; - case CMD_ERASE_SETUP: - for (i = 0; i < 7; i++) { - if ((addr >= dev->block_start[i]) && (addr <= dev->block_end[i])) - dev->program_addr = i; - } - break; - case CMD_PROGRAM_SETUP: - case CMD_PROGRAM_SETUP_ALT: - dev->program_addr = addr; - break; - } - } + default: + dev->command = val & 0xff; + switch (val) { + case CMD_CLEAR_STATUS: + dev->status = 0; + break; + case CMD_ERASE_SETUP: + for (i = 0; i < 7; i++) { + if ((addr >= dev->block_start[i]) && (addr <= dev->block_end[i])) + dev->program_addr = i; + } + break; + case CMD_PROGRAM_SETUP: + case CMD_PROGRAM_SETUP_ALT: + dev->program_addr = addr; + break; + } + } } - static void flash_writel(uint32_t addr, uint32_t val, void *p) { @@ -290,70 +279,67 @@ flash_writel(uint32_t addr, uint32_t val, void *p) #endif } - static void intel_flash_add_mappings(flash_t *dev) { - int max = 2, i = 0; + int max = 2, i = 0; uint32_t base, fbase; uint32_t sub = 0x20000; if (biosmask == 0x7ffff) { - sub = 0x80000; - max = 8; + sub = 0x80000; + max = 8; } else if (biosmask == 0x3ffff) { - sub = 0x40000; - max = 4; + sub = 0x40000; + max = 4; } for (i = 0; i < max; i++) { - if (biosmask == 0x7ffff) - base = 0x80000 + (i << 16); - else if (biosmask == 0x3ffff) - base = 0xc0000 + (i << 16); - else - base = 0xe0000 + (i << 16); + if (biosmask == 0x7ffff) + base = 0x80000 + (i << 16); + else if (biosmask == 0x3ffff) + base = 0xc0000 + (i << 16); + else + base = 0xe0000 + (i << 16); - fbase = base & biosmask; - if (dev->flags & FLAG_INV_A16) - fbase ^= 0x10000; + fbase = base & biosmask; + if (dev->flags & FLAG_INV_A16) + fbase ^= 0x10000; - memcpy(&dev->array[fbase], &rom[base & biosmask], 0x10000); + memcpy(&dev->array[fbase], &rom[base & biosmask], 0x10000); - if ((max == 2) || (i >= 2)) { - mem_mapping_add(&(dev->mapping[i]), base, 0x10000, - flash_read, flash_readw, flash_readl, - flash_write, flash_writew, flash_writel, - dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, (void *) dev); - } - mem_mapping_add(&(dev->mapping_h[i]), (base | 0xfff00000) - sub, 0x10000, - flash_read, flash_readw, flash_readl, - flash_write, flash_writew, flash_writel, - dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, (void *) dev); - mem_mapping_add(&(dev->mapping_h[i + max]), (base | 0xfff00000), 0x10000, - flash_read, flash_readw, flash_readl, - flash_write, flash_writew, flash_writel, - dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, (void *) dev); + if ((max == 2) || (i >= 2)) { + mem_mapping_add(&(dev->mapping[i]), base, 0x10000, + flash_read, flash_readw, flash_readl, + flash_write, flash_writew, flash_writel, + dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev); + } + mem_mapping_add(&(dev->mapping_h[i]), (base | 0xfff00000) - sub, 0x10000, + flash_read, flash_readw, flash_readl, + flash_write, flash_writew, flash_writel, + dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev); + mem_mapping_add(&(dev->mapping_h[i + max]), (base | 0xfff00000), 0x10000, + flash_read, flash_readw, flash_readl, + flash_write, flash_writew, flash_writel, + dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev); } } - static void intel_flash_reset(void *priv) { flash_t *dev = (flash_t *) priv; dev->command = CMD_READ_ARRAY; - dev->status = 0; + dev->status = 0; } - static void * intel_flash_init(const device_t *info) { - FILE *f; + FILE *f; flash_t *dev; - uint8_t type = info->local & 0xff; + uint8_t type = info->local & 0xff; dev = malloc(sizeof(flash_t)); memset(dev, 0, sizeof(flash_t)); @@ -369,186 +355,185 @@ intel_flash_init(const device_t *info) memset(dev->array, 0xff, biosmask + 1); switch (biosmask) { - case 0x7ffff: - if (dev->flags & FLAG_WORD) - dev->flash_id = (dev->flags & FLAG_BXB) ? 0x4471 : 0x4470; - else - dev->flash_id =(dev->flags & FLAG_BXB) ? 0x8A : 0x89; + case 0x7ffff: + if (dev->flags & FLAG_WORD) + dev->flash_id = (dev->flags & FLAG_BXB) ? 0x4471 : 0x4470; + else + dev->flash_id = (dev->flags & FLAG_BXB) ? 0x8A : 0x89; - /* The block lengths are the same both flash types. */ - dev->block_len[BLOCK_MAIN1] = 0x20000; - dev->block_len[BLOCK_MAIN2] = 0x20000; - dev->block_len[BLOCK_MAIN3] = 0x20000; - dev->block_len[BLOCK_MAIN4] = 0x18000; - dev->block_len[BLOCK_DATA1] = 0x02000; - dev->block_len[BLOCK_DATA2] = 0x02000; - dev->block_len[BLOCK_BOOT] = 0x04000; + /* The block lengths are the same both flash types. */ + dev->block_len[BLOCK_MAIN1] = 0x20000; + dev->block_len[BLOCK_MAIN2] = 0x20000; + dev->block_len[BLOCK_MAIN3] = 0x20000; + dev->block_len[BLOCK_MAIN4] = 0x18000; + dev->block_len[BLOCK_DATA1] = 0x02000; + dev->block_len[BLOCK_DATA2] = 0x02000; + dev->block_len[BLOCK_BOOT] = 0x04000; - if (dev->flags & FLAG_BXB) { /* 28F004BX-T/28F400BX-B */ - dev->block_start[BLOCK_BOOT] = 0x00000; /* MAIN BLOCK 1 */ - dev->block_end[BLOCK_BOOT] = 0x1ffff; - dev->block_start[BLOCK_DATA2] = 0x20000; /* MAIN BLOCK 2 */ - dev->block_end[BLOCK_DATA2] = 0x3ffff; - dev->block_start[BLOCK_DATA1] = 0x40000; /* MAIN BLOCK 3 */ - dev->block_end[BLOCK_DATA1] = 0x5ffff; - dev->block_start[BLOCK_MAIN4] = 0x60000; /* MAIN BLOCK 4 */ - dev->block_end[BLOCK_MAIN4] = 0x77fff; - dev->block_start[BLOCK_MAIN3] = 0x78000; /* DATA AREA 1 BLOCK */ - dev->block_end[BLOCK_MAIN3] = 0x79fff; - dev->block_start[BLOCK_MAIN2] = 0x7a000; /* DATA AREA 2 BLOCK */ - dev->block_end[BLOCK_MAIN2] = 0x7bfff; - dev->block_start[BLOCK_MAIN1] = 0x7c000; /* BOOT BLOCK */ - dev->block_end[BLOCK_MAIN1] = 0x7ffff; - } else { - dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */ - dev->block_end[BLOCK_MAIN1] = 0x1ffff; - dev->block_start[BLOCK_MAIN2] = 0x20000; /* MAIN BLOCK 2 */ - dev->block_end[BLOCK_MAIN2] = 0x3ffff; - dev->block_start[BLOCK_MAIN3] = 0x40000; /* MAIN BLOCK 3 */ - dev->block_end[BLOCK_MAIN3] = 0x5ffff; - dev->block_start[BLOCK_MAIN4] = 0x60000; /* MAIN BLOCK 4 */ - dev->block_end[BLOCK_MAIN4] = 0x77fff; - dev->block_start[BLOCK_DATA1] = 0x78000; /* DATA AREA 1 BLOCK */ - dev->block_end[BLOCK_DATA1] = 0x79fff; - dev->block_start[BLOCK_DATA2] = 0x7a000; /* DATA AREA 2 BLOCK */ - dev->block_end[BLOCK_DATA2] = 0x7bfff; - dev->block_start[BLOCK_BOOT] = 0x7c000; /* BOOT BLOCK */ - dev->block_end[BLOCK_BOOT] = 0x7ffff; - } - break; + if (dev->flags & FLAG_BXB) { /* 28F004BX-T/28F400BX-B */ + dev->block_start[BLOCK_BOOT] = 0x00000; /* MAIN BLOCK 1 */ + dev->block_end[BLOCK_BOOT] = 0x1ffff; + dev->block_start[BLOCK_DATA2] = 0x20000; /* MAIN BLOCK 2 */ + dev->block_end[BLOCK_DATA2] = 0x3ffff; + dev->block_start[BLOCK_DATA1] = 0x40000; /* MAIN BLOCK 3 */ + dev->block_end[BLOCK_DATA1] = 0x5ffff; + dev->block_start[BLOCK_MAIN4] = 0x60000; /* MAIN BLOCK 4 */ + dev->block_end[BLOCK_MAIN4] = 0x77fff; + dev->block_start[BLOCK_MAIN3] = 0x78000; /* DATA AREA 1 BLOCK */ + dev->block_end[BLOCK_MAIN3] = 0x79fff; + dev->block_start[BLOCK_MAIN2] = 0x7a000; /* DATA AREA 2 BLOCK */ + dev->block_end[BLOCK_MAIN2] = 0x7bfff; + dev->block_start[BLOCK_MAIN1] = 0x7c000; /* BOOT BLOCK */ + dev->block_end[BLOCK_MAIN1] = 0x7ffff; + } else { + dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */ + dev->block_end[BLOCK_MAIN1] = 0x1ffff; + dev->block_start[BLOCK_MAIN2] = 0x20000; /* MAIN BLOCK 2 */ + dev->block_end[BLOCK_MAIN2] = 0x3ffff; + dev->block_start[BLOCK_MAIN3] = 0x40000; /* MAIN BLOCK 3 */ + dev->block_end[BLOCK_MAIN3] = 0x5ffff; + dev->block_start[BLOCK_MAIN4] = 0x60000; /* MAIN BLOCK 4 */ + dev->block_end[BLOCK_MAIN4] = 0x77fff; + dev->block_start[BLOCK_DATA1] = 0x78000; /* DATA AREA 1 BLOCK */ + dev->block_end[BLOCK_DATA1] = 0x79fff; + dev->block_start[BLOCK_DATA2] = 0x7a000; /* DATA AREA 2 BLOCK */ + dev->block_end[BLOCK_DATA2] = 0x7bfff; + dev->block_start[BLOCK_BOOT] = 0x7c000; /* BOOT BLOCK */ + dev->block_end[BLOCK_BOOT] = 0x7ffff; + } + break; - case 0x3ffff: - if (dev->flags & FLAG_WORD) - dev->flash_id = (dev->flags & FLAG_BXB) ? 0x2275 : 0x2274; - else - dev->flash_id = (dev->flags & FLAG_BXB) ? 0x7D : 0x7C; + case 0x3ffff: + if (dev->flags & FLAG_WORD) + dev->flash_id = (dev->flags & FLAG_BXB) ? 0x2275 : 0x2274; + else + dev->flash_id = (dev->flags & FLAG_BXB) ? 0x7D : 0x7C; - /* The block lengths are the same both flash types. */ - dev->block_len[BLOCK_MAIN1] = 0x20000; - dev->block_len[BLOCK_MAIN2] = 0x18000; - dev->block_len[BLOCK_MAIN3] = 0x00000; - dev->block_len[BLOCK_MAIN4] = 0x00000; - dev->block_len[BLOCK_DATA1] = 0x02000; - dev->block_len[BLOCK_DATA2] = 0x02000; - dev->block_len[BLOCK_BOOT] = 0x04000; + /* The block lengths are the same both flash types. */ + dev->block_len[BLOCK_MAIN1] = 0x20000; + dev->block_len[BLOCK_MAIN2] = 0x18000; + dev->block_len[BLOCK_MAIN3] = 0x00000; + dev->block_len[BLOCK_MAIN4] = 0x00000; + dev->block_len[BLOCK_DATA1] = 0x02000; + dev->block_len[BLOCK_DATA2] = 0x02000; + dev->block_len[BLOCK_BOOT] = 0x04000; - if (dev->flags & FLAG_BXB) { /* 28F002BX-B/28F200BX-B */ - dev->block_start[BLOCK_MAIN1] = 0x20000; /* MAIN BLOCK 1 */ - dev->block_end[BLOCK_MAIN1] = 0x3ffff; - dev->block_start[BLOCK_MAIN2] = 0x08000; /* MAIN BLOCK 2 */ - dev->block_end[BLOCK_MAIN2] = 0x1ffff; - dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */ - dev->block_end[BLOCK_MAIN3] = 0xfffff; - dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */ - dev->block_end[BLOCK_MAIN4] = 0xfffff; - dev->block_start[BLOCK_DATA1] = 0x06000; /* DATA AREA 1 BLOCK */ - dev->block_end[BLOCK_DATA1] = 0x07fff; - dev->block_start[BLOCK_DATA2] = 0x04000; /* DATA AREA 2 BLOCK */ - dev->block_end[BLOCK_DATA2] = 0x05fff; - dev->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */ - dev->block_end[BLOCK_BOOT] = 0x03fff; - } else { /* 28F002BX-T/28F200BX-T */ - dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */ - dev->block_end[BLOCK_MAIN1] = 0x1ffff; - dev->block_start[BLOCK_MAIN2] = 0x20000; /* MAIN BLOCK 2 */ - dev->block_end[BLOCK_MAIN2] = 0x37fff; - dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */ - dev->block_end[BLOCK_MAIN3] = 0xfffff; - dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */ - dev->block_end[BLOCK_MAIN4] = 0xfffff; - dev->block_start[BLOCK_DATA1] = 0x38000; /* DATA AREA 1 BLOCK */ - dev->block_end[BLOCK_DATA1] = 0x39fff; - dev->block_start[BLOCK_DATA2] = 0x3a000; /* DATA AREA 2 BLOCK */ - dev->block_end[BLOCK_DATA2] = 0x3bfff; - dev->block_start[BLOCK_BOOT] = 0x3c000; /* BOOT BLOCK */ - dev->block_end[BLOCK_BOOT] = 0x3ffff; - } - break; + if (dev->flags & FLAG_BXB) { /* 28F002BX-B/28F200BX-B */ + dev->block_start[BLOCK_MAIN1] = 0x20000; /* MAIN BLOCK 1 */ + dev->block_end[BLOCK_MAIN1] = 0x3ffff; + dev->block_start[BLOCK_MAIN2] = 0x08000; /* MAIN BLOCK 2 */ + dev->block_end[BLOCK_MAIN2] = 0x1ffff; + dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */ + dev->block_end[BLOCK_MAIN3] = 0xfffff; + dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */ + dev->block_end[BLOCK_MAIN4] = 0xfffff; + dev->block_start[BLOCK_DATA1] = 0x06000; /* DATA AREA 1 BLOCK */ + dev->block_end[BLOCK_DATA1] = 0x07fff; + dev->block_start[BLOCK_DATA2] = 0x04000; /* DATA AREA 2 BLOCK */ + dev->block_end[BLOCK_DATA2] = 0x05fff; + dev->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */ + dev->block_end[BLOCK_BOOT] = 0x03fff; + } else { /* 28F002BX-T/28F200BX-T */ + dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */ + dev->block_end[BLOCK_MAIN1] = 0x1ffff; + dev->block_start[BLOCK_MAIN2] = 0x20000; /* MAIN BLOCK 2 */ + dev->block_end[BLOCK_MAIN2] = 0x37fff; + dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */ + dev->block_end[BLOCK_MAIN3] = 0xfffff; + dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */ + dev->block_end[BLOCK_MAIN4] = 0xfffff; + dev->block_start[BLOCK_DATA1] = 0x38000; /* DATA AREA 1 BLOCK */ + dev->block_end[BLOCK_DATA1] = 0x39fff; + dev->block_start[BLOCK_DATA2] = 0x3a000; /* DATA AREA 2 BLOCK */ + dev->block_end[BLOCK_DATA2] = 0x3bfff; + dev->block_start[BLOCK_BOOT] = 0x3c000; /* BOOT BLOCK */ + dev->block_end[BLOCK_BOOT] = 0x3ffff; + } + break; - default: - dev->flash_id = (type & FLAG_BXB) ? 0x95 : 0x94; + default: + dev->flash_id = (type & FLAG_BXB) ? 0x95 : 0x94; - /* The block lengths are the same both flash types. */ - dev->block_len[BLOCK_MAIN1] = 0x1c000; - dev->block_len[BLOCK_MAIN2] = 0x00000; - dev->block_len[BLOCK_MAIN3] = 0x00000; - dev->block_len[BLOCK_MAIN4] = 0x00000; - dev->block_len[BLOCK_DATA1] = 0x01000; - dev->block_len[BLOCK_DATA2] = 0x01000; - dev->block_len[BLOCK_BOOT] = 0x02000; + /* The block lengths are the same both flash types. */ + dev->block_len[BLOCK_MAIN1] = 0x1c000; + dev->block_len[BLOCK_MAIN2] = 0x00000; + dev->block_len[BLOCK_MAIN3] = 0x00000; + dev->block_len[BLOCK_MAIN4] = 0x00000; + dev->block_len[BLOCK_DATA1] = 0x01000; + dev->block_len[BLOCK_DATA2] = 0x01000; + dev->block_len[BLOCK_BOOT] = 0x02000; - if (dev->flags & FLAG_BXB) { /* 28F001BX-B/28F100BX-B */ - dev->block_start[BLOCK_MAIN1] = 0x04000; /* MAIN BLOCK 1 */ - dev->block_end[BLOCK_MAIN1] = 0x1ffff; - dev->block_start[BLOCK_MAIN2] = 0xfffff; /* MAIN BLOCK 2 */ - dev->block_end[BLOCK_MAIN2] = 0xfffff; - dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */ - dev->block_end[BLOCK_MAIN3] = 0xfffff; - dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */ - dev->block_end[BLOCK_MAIN4] = 0xfffff; - dev->block_start[BLOCK_DATA1] = 0x02000; /* DATA AREA 1 BLOCK */ - dev->block_end[BLOCK_DATA1] = 0x02fff; - dev->block_start[BLOCK_DATA2] = 0x03000; /* DATA AREA 2 BLOCK */ - dev->block_end[BLOCK_DATA2] = 0x03fff; - dev->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */ - dev->block_end[BLOCK_BOOT] = 0x01fff; - } else { /* 28F001BX-T/28F100BX-T */ - dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */ - dev->block_end[BLOCK_MAIN1] = 0x1bfff; - dev->block_start[BLOCK_MAIN2] = 0xfffff; /* MAIN BLOCK 2 */ - dev->block_end[BLOCK_MAIN2] = 0xfffff; - dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */ - dev->block_end[BLOCK_MAIN3] = 0xfffff; - dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */ - dev->block_end[BLOCK_MAIN4] = 0xfffff; - dev->block_start[BLOCK_DATA1] = 0x1c000; /* DATA AREA 1 BLOCK */ - dev->block_end[BLOCK_DATA1] = 0x1cfff; - dev->block_start[BLOCK_DATA2] = 0x1d000; /* DATA AREA 2 BLOCK */ - dev->block_end[BLOCK_DATA2] = 0x1dfff; - dev->block_start[BLOCK_BOOT] = 0x1e000; /* BOOT BLOCK */ - dev->block_end[BLOCK_BOOT] = 0x1ffff; - } - break; + if (dev->flags & FLAG_BXB) { /* 28F001BX-B/28F100BX-B */ + dev->block_start[BLOCK_MAIN1] = 0x04000; /* MAIN BLOCK 1 */ + dev->block_end[BLOCK_MAIN1] = 0x1ffff; + dev->block_start[BLOCK_MAIN2] = 0xfffff; /* MAIN BLOCK 2 */ + dev->block_end[BLOCK_MAIN2] = 0xfffff; + dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */ + dev->block_end[BLOCK_MAIN3] = 0xfffff; + dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */ + dev->block_end[BLOCK_MAIN4] = 0xfffff; + dev->block_start[BLOCK_DATA1] = 0x02000; /* DATA AREA 1 BLOCK */ + dev->block_end[BLOCK_DATA1] = 0x02fff; + dev->block_start[BLOCK_DATA2] = 0x03000; /* DATA AREA 2 BLOCK */ + dev->block_end[BLOCK_DATA2] = 0x03fff; + dev->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */ + dev->block_end[BLOCK_BOOT] = 0x01fff; + } else { /* 28F001BX-T/28F100BX-T */ + dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */ + dev->block_end[BLOCK_MAIN1] = 0x1bfff; + dev->block_start[BLOCK_MAIN2] = 0xfffff; /* MAIN BLOCK 2 */ + dev->block_end[BLOCK_MAIN2] = 0xfffff; + dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */ + dev->block_end[BLOCK_MAIN3] = 0xfffff; + dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */ + dev->block_end[BLOCK_MAIN4] = 0xfffff; + dev->block_start[BLOCK_DATA1] = 0x1c000; /* DATA AREA 1 BLOCK */ + dev->block_end[BLOCK_DATA1] = 0x1cfff; + dev->block_start[BLOCK_DATA2] = 0x1d000; /* DATA AREA 2 BLOCK */ + dev->block_end[BLOCK_DATA2] = 0x1dfff; + dev->block_start[BLOCK_BOOT] = 0x1e000; /* BOOT BLOCK */ + dev->block_end[BLOCK_BOOT] = 0x1ffff; + } + break; } intel_flash_add_mappings(dev); dev->command = CMD_READ_ARRAY; - dev->status = 0; + dev->status = 0; f = nvr_fopen(flash_path, "rb"); if (f) { - (void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, f); - if (dev->block_len[BLOCK_MAIN2]) - (void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, f); - if (dev->block_len[BLOCK_MAIN3]) - (void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN3]]), dev->block_len[BLOCK_MAIN3], 1, f); - if (dev->block_len[BLOCK_MAIN4]) - (void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN4]]), dev->block_len[BLOCK_MAIN4], 1, f); + (void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, f); + if (dev->block_len[BLOCK_MAIN2]) + (void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, f); + if (dev->block_len[BLOCK_MAIN3]) + (void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN3]]), dev->block_len[BLOCK_MAIN3], 1, f); + if (dev->block_len[BLOCK_MAIN4]) + (void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN4]]), dev->block_len[BLOCK_MAIN4], 1, f); - (void) !fread(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, f); - (void) !fread(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, f); - fclose(f); + (void) !fread(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, f); + (void) !fread(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, f); + fclose(f); } return dev; } - static void intel_flash_close(void *p) { - FILE *f; - flash_t *dev = (flash_t *)p; + FILE *f; + flash_t *dev = (flash_t *) p; f = nvr_fopen(flash_path, "wb"); fwrite(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, f); if (dev->block_len[BLOCK_MAIN2]) - fwrite(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, f); + fwrite(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, f); if (dev->block_len[BLOCK_MAIN3]) - fwrite(&(dev->array[dev->block_start[BLOCK_MAIN3]]), dev->block_len[BLOCK_MAIN3], 1, f); + fwrite(&(dev->array[dev->block_start[BLOCK_MAIN3]]), dev->block_len[BLOCK_MAIN3], 1, f); if (dev->block_len[BLOCK_MAIN4]) - fwrite(&(dev->array[dev->block_start[BLOCK_MAIN4]]), dev->block_len[BLOCK_MAIN4], 1, f); + fwrite(&(dev->array[dev->block_start[BLOCK_MAIN4]]), dev->block_len[BLOCK_MAIN4], 1, f); fwrite(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, f); fwrite(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, f); @@ -562,43 +547,43 @@ intel_flash_close(void *p) /* For AMI BIOS'es - Intel 28F001BXT with A16 pin inverted. */ const device_t intel_flash_bxt_ami_device = { - .name = "Intel 28F001BXT/28F002BXT/28F004BXT Flash BIOS", + .name = "Intel 28F001BXT/28F002BXT/28F004BXT Flash BIOS", .internal_name = "intel_flash_bxt_ami", - .flags = DEVICE_PCI, - .local = FLAG_INV_A16, - .init = intel_flash_init, - .close = intel_flash_close, - .reset = intel_flash_reset, + .flags = DEVICE_PCI, + .local = FLAG_INV_A16, + .init = intel_flash_init, + .close = intel_flash_close, + .reset = intel_flash_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t intel_flash_bxt_device = { - .name = "Intel 28F001BXT/28F002BXT/28F004BXT Flash BIOS", + .name = "Intel 28F001BXT/28F002BXT/28F004BXT Flash BIOS", .internal_name = "intel_flash_bxt", - .flags = DEVICE_PCI, - .local = 0, - .init = intel_flash_init, - .close = intel_flash_close, - .reset = intel_flash_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = intel_flash_init, + .close = intel_flash_close, + .reset = intel_flash_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t intel_flash_bxb_device = { - .name = "Intel 28F001BXB/28F002BXB/28F004BXB Flash BIOS", + .name = "Intel 28F001BXB/28F002BXB/28F004BXB Flash BIOS", .internal_name = "intel_flash_bxb", - .flags = DEVICE_PCI, - .local = FLAG_BXB, - .init = intel_flash_init, - .close = intel_flash_close, - .reset = intel_flash_reset, + .flags = DEVICE_PCI, + .local = FLAG_BXB, + .init = intel_flash_init, + .close = intel_flash_close, + .reset = intel_flash_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/mem/mem.c b/src/mem/mem.c index bc4e34691..9f292fd0e 100644 --- a/src/mem/mem.c +++ b/src/mem/mem.c @@ -38,125 +38,120 @@ #include <86box/rom.h> #include <86box/gdbstub.h> #ifdef USE_DYNAREC -# include "codegen_public.h" +# include "codegen_public.h" #else -#ifdef USE_NEW_DYNAREC -# define PAGE_MASK_SHIFT 6 -#else -# define PAGE_MASK_INDEX_MASK 3 -# define PAGE_MASK_INDEX_SHIFT 10 -# define PAGE_MASK_SHIFT 4 -#endif -# define PAGE_MASK_MASK 63 +# ifdef USE_NEW_DYNAREC +# define PAGE_MASK_SHIFT 6 +# else +# define PAGE_MASK_INDEX_MASK 3 +# define PAGE_MASK_INDEX_SHIFT 10 +# define PAGE_MASK_SHIFT 4 +# endif +# define PAGE_MASK_MASK 63 #endif #if (!defined(USE_DYNAREC) && defined(USE_NEW_DYNAREC)) -#define BLOCK_PC_INVALID 0xffffffff -#define BLOCK_INVALID 0 +# define BLOCK_PC_INVALID 0xffffffff +# define BLOCK_INVALID 0 #endif +mem_mapping_t ram_low_mapping, /* 0..640K mapping */ + ram_mid_mapping, + ram_remapped_mapping, /* 640..1024K mapping */ + ram_high_mapping, /* 1024K+ mapping */ + ram_2gb_mapping, /* 1024M+ mapping */ + ram_remapped_mapping, + ram_split_mapping, + bios_mapping, + bios_high_mapping; -mem_mapping_t ram_low_mapping, /* 0..640K mapping */ - ram_mid_mapping, - ram_remapped_mapping, /* 640..1024K mapping */ - ram_high_mapping, /* 1024K+ mapping */ - ram_2gb_mapping, /* 1024M+ mapping */ - ram_remapped_mapping, - ram_split_mapping, - bios_mapping, - bios_high_mapping; +page_t *pages, /* RAM page table */ + **page_lookup; /* pagetable lookup */ +uint32_t pages_sz; /* #pages in table */ -page_t *pages, /* RAM page table */ - **page_lookup; /* pagetable lookup */ -uint32_t pages_sz; /* #pages in table */ +uint8_t *ram, *ram2; /* the virtual RAM */ +uint8_t page_ff[4096]; +uint32_t rammask; -uint8_t *ram, *ram2; /* the virtual RAM */ -uint8_t page_ff[4096]; -uint32_t rammask; +uint8_t *rom; /* the virtual ROM */ +uint32_t biosmask, biosaddr; -uint8_t *rom; /* the virtual ROM */ -uint32_t biosmask, biosaddr; +uint32_t pccache; +uint8_t *pccache2; -uint32_t pccache; -uint8_t *pccache2; +int readlnext; +int readlookup[256]; +uintptr_t *readlookup2; +uintptr_t old_rl2; +uint8_t uncached = 0; +int writelnext; +int writelookup[256]; +uintptr_t *writelookup2; -int readlnext; -int readlookup[256]; -uintptr_t *readlookup2; -uintptr_t old_rl2; -uint8_t uncached = 0; -int writelnext; -int writelookup[256]; -uintptr_t *writelookup2; +uint32_t mem_logical_addr; -uint32_t mem_logical_addr; +int shadowbios = 0, + shadowbios_write; +int readlnum = 0, + writelnum = 0; +int cachesize = 256; -int shadowbios = 0, - shadowbios_write; -int readlnum = 0, - writelnum = 0; -int cachesize = 256; +uint32_t get_phys_virt, + get_phys_phys; -uint32_t get_phys_virt, - get_phys_phys; +int mem_a20_key = 0, + mem_a20_alt = 0, + mem_a20_state = 0; -int mem_a20_key = 0, - mem_a20_alt = 0, - mem_a20_state = 0; - -int mmuflush = 0; -int mmu_perm = 4; +int mmuflush = 0; +int mmu_perm = 4; #ifdef USE_NEW_DYNAREC -uint64_t *byte_dirty_mask; -uint64_t *byte_code_present_mask; +uint64_t *byte_dirty_mask; +uint64_t *byte_code_present_mask; -uint32_t purgable_page_list_head = 0; -int purgeable_page_count = 0; +uint32_t purgable_page_list_head = 0; +int purgeable_page_count = 0; #endif -uint8_t high_page = 0; /* if a high (> 4 gb) page was detected */ - +uint8_t high_page = 0; /* if a high (> 4 gb) page was detected */ /* FIXME: re-do this with a 'mem_ops' struct. */ -static uint8_t *page_lookupp; /* pagetable mmu_perm lookup */ -static uint8_t *readlookupp; -static uint8_t *writelookupp; -static mem_mapping_t *base_mapping, *last_mapping; -static mem_mapping_t *read_mapping[MEM_MAPPINGS_NO]; -static mem_mapping_t *write_mapping[MEM_MAPPINGS_NO]; -static mem_mapping_t *read_mapping_bus[MEM_MAPPINGS_NO]; -static mem_mapping_t *write_mapping_bus[MEM_MAPPINGS_NO]; -static uint8_t *_mem_exec[MEM_MAPPINGS_NO]; -static uint8_t ff_pccache[4] = { 0xff, 0xff, 0xff, 0xff }; -static mem_state_t _mem_state[MEM_MAPPINGS_NO]; -static uint32_t remap_start_addr; +static uint8_t *page_lookupp; /* pagetable mmu_perm lookup */ +static uint8_t *readlookupp; +static uint8_t *writelookupp; +static mem_mapping_t *base_mapping, *last_mapping; +static mem_mapping_t *read_mapping[MEM_MAPPINGS_NO]; +static mem_mapping_t *write_mapping[MEM_MAPPINGS_NO]; +static mem_mapping_t *read_mapping_bus[MEM_MAPPINGS_NO]; +static mem_mapping_t *write_mapping_bus[MEM_MAPPINGS_NO]; +static uint8_t *_mem_exec[MEM_MAPPINGS_NO]; +static uint8_t ff_pccache[4] = { 0xff, 0xff, 0xff, 0xff }; +static mem_state_t _mem_state[MEM_MAPPINGS_NO]; +static uint32_t remap_start_addr; #if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)) -static size_t ram_size = 0, ram2_size = 0; +static size_t ram_size = 0, ram2_size = 0; #else -static size_t ram_size = 0; +static size_t ram_size = 0; #endif - #ifdef ENABLE_MEM_LOG int mem_do_log = ENABLE_MEM_LOG; - static void mem_log(const char *fmt, ...) { va_list ap; if (mem_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define mem_log(fmt, ...) +# define mem_log(fmt, ...) #endif - int mem_addr_is_ram(uint32_t addr) { @@ -165,125 +160,119 @@ mem_addr_is_ram(uint32_t addr) return (mapping == &ram_low_mapping) || (mapping == &ram_high_mapping) || (mapping == &ram_mid_mapping) || (mapping == &ram_remapped_mapping); } - void resetreadlookup(void) { int c; /* Initialize the page lookup table. */ - memset(page_lookup, 0x00, (1<<20)*sizeof(page_t *)); + memset(page_lookup, 0x00, (1 << 20) * sizeof(page_t *)); /* Initialize the tables for lower (<= 1024K) RAM. */ for (c = 0; c < 256; c++) { - readlookup[c] = 0xffffffff; - writelookup[c] = 0xffffffff; + readlookup[c] = 0xffffffff; + writelookup[c] = 0xffffffff; } /* Initialize the tables for high (> 1024K) RAM. */ - memset(readlookup2, 0xff, (1<<20)*sizeof(uintptr_t)); - memset(readlookupp, 0x04, (1<<20)*sizeof(uint8_t)); + memset(readlookup2, 0xff, (1 << 20) * sizeof(uintptr_t)); + memset(readlookupp, 0x04, (1 << 20) * sizeof(uint8_t)); - memset(writelookup2, 0xff, (1<<20)*sizeof(uintptr_t)); - memset(writelookupp, 0x04, (1<<20)*sizeof(uint8_t)); + memset(writelookup2, 0xff, (1 << 20) * sizeof(uintptr_t)); + memset(writelookupp, 0x04, (1 << 20) * sizeof(uint8_t)); - readlnext = 0; + readlnext = 0; writelnext = 0; - pccache = 0xffffffff; - high_page = 0; + pccache = 0xffffffff; + high_page = 0; } - void flushmmucache(void) { int c; for (c = 0; c < 256; c++) { - if (readlookup[c] != (int) 0xffffffff) { - readlookup2[readlookup[c]] = LOOKUP_INV; - readlookupp[readlookup[c]] = 4; - readlookup[c] = 0xffffffff; - } - if (writelookup[c] != (int) 0xffffffff) { - page_lookup[writelookup[c]] = NULL; - page_lookupp[writelookup[c]] = 4; - writelookup2[writelookup[c]] = LOOKUP_INV; - writelookupp[writelookup[c]] = 4; - writelookup[c] = 0xffffffff; - } + if (readlookup[c] != (int) 0xffffffff) { + readlookup2[readlookup[c]] = LOOKUP_INV; + readlookupp[readlookup[c]] = 4; + readlookup[c] = 0xffffffff; + } + if (writelookup[c] != (int) 0xffffffff) { + page_lookup[writelookup[c]] = NULL; + page_lookupp[writelookup[c]] = 4; + writelookup2[writelookup[c]] = LOOKUP_INV; + writelookupp[writelookup[c]] = 4; + writelookup[c] = 0xffffffff; + } } mmuflush++; - pccache = (uint32_t)0xffffffff; - pccache2 = (uint8_t *)0xffffffff; + pccache = (uint32_t) 0xffffffff; + pccache2 = (uint8_t *) 0xffffffff; #ifdef USE_DYNAREC codegen_flush(); #endif } - void flushmmucache_nopc(void) { int c; for (c = 0; c < 256; c++) { - if (readlookup[c] != (int) 0xffffffff) { - readlookup2[readlookup[c]] = LOOKUP_INV; - readlookupp[readlookup[c]] = 4; - readlookup[c] = 0xffffffff; - } - if (writelookup[c] != (int) 0xffffffff) { - page_lookup[writelookup[c]] = NULL; - page_lookupp[writelookup[c]] = 4; - writelookup2[writelookup[c]] = LOOKUP_INV; - writelookupp[writelookup[c]] = 4; - writelookup[c] = 0xffffffff; - } + if (readlookup[c] != (int) 0xffffffff) { + readlookup2[readlookup[c]] = LOOKUP_INV; + readlookupp[readlookup[c]] = 4; + readlookup[c] = 0xffffffff; + } + if (writelookup[c] != (int) 0xffffffff) { + page_lookup[writelookup[c]] = NULL; + page_lookupp[writelookup[c]] = 4; + writelookup2[writelookup[c]] = LOOKUP_INV; + writelookupp[writelookup[c]] = 4; + writelookup[c] = 0xffffffff; + } } } - void mem_flush_write_page(uint32_t addr, uint32_t virt) { page_t *page_target = &pages[addr >> 12]; - int c; + int c; #if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)) uint32_t a; #endif for (c = 0; c < 256; c++) { - if (writelookup[c] != (int) 0xffffffff) { + if (writelookup[c] != (int) 0xffffffff) { #if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64) - uintptr_t target = (uintptr_t)&ram[(uintptr_t)(addr & ~0xfff) - (virt & ~0xfff)]; + uintptr_t target = (uintptr_t) &ram[(uintptr_t) (addr & ~0xfff) - (virt & ~0xfff)]; #else - a = (uintptr_t)(addr & ~0xfff) - (virt & ~0xfff); - uintptr_t target; + a = (uintptr_t) (addr & ~0xfff) - (virt & ~0xfff); + uintptr_t target; - if ((addr & ~0xfff) >= (1 << 30)) - target = (uintptr_t)&ram2[a - (1 << 30)]; - else - target = (uintptr_t)&ram[a]; + if ((addr & ~0xfff) >= (1 << 30)) + target = (uintptr_t) &ram2[a - (1 << 30)]; + else + target = (uintptr_t) &ram[a]; #endif - if (writelookup2[writelookup[c]] == target || page_lookup[writelookup[c]] == page_target) { - writelookup2[writelookup[c]] = LOOKUP_INV; - page_lookup[writelookup[c]] = NULL; - writelookup[c] = 0xffffffff; - } - } + if (writelookup2[writelookup[c]] == target || page_lookup[writelookup[c]] == page_target) { + writelookup2[writelookup[c]] = LOOKUP_INV; + page_lookup[writelookup[c]] = NULL; + writelookup[c] = 0xffffffff; + } + } } } - -#define mmutranslate_read(addr) mmutranslatereal(addr,0) -#define mmutranslate_write(addr) mmutranslatereal(addr,1) -#define rammap(x) ((uint32_t *)(_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 2) & MEM_GRANULARITY_QMASK] -#define rammap64(x) ((uint64_t *)(_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 3) & MEM_GRANULARITY_PMASK] - +#define mmutranslate_read(addr) mmutranslatereal(addr, 0) +#define mmutranslate_write(addr) mmutranslatereal(addr, 1) +#define rammap(x) ((uint32_t *) (_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 2) & MEM_GRANULARITY_QMASK] +#define rammap64(x) ((uint64_t *) (_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 3) & MEM_GRANULARITY_PMASK] static __inline uint64_t mmutranslatereal_normal(uint32_t addr, int rw) @@ -292,53 +281,55 @@ mmutranslatereal_normal(uint32_t addr, int rw) uint32_t addr2; if (cpu_state.abrt) - return 0xffffffffffffffffULL; + return 0xffffffffffffffffULL; addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc)); temp = temp2 = rammap(addr2); if (!(temp & 1)) { - cr2 = addr; - temp &= 1; - if (CPL == 3) temp |= 4; - if (rw) temp |= 2; - cpu_state.abrt = ABRT_PF; - abrt_error = temp; - return 0xffffffffffffffffULL; + cr2 = addr; + temp &= 1; + if (CPL == 3) + temp |= 4; + if (rw) + temp |= 2; + cpu_state.abrt = ABRT_PF; + abrt_error = temp; + return 0xffffffffffffffffULL; } if ((temp & 0x80) && (cr4 & CR4_PSE)) { - /*4MB page*/ - if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (((CPL == 3) && !cpl_override) || (is486 && (cr0 & WP_FLAG))))) { - cr2 = addr; - temp &= 1; - if (CPL == 3) - temp |= 4; - if (rw) - temp |= 2; - cpu_state.abrt = ABRT_PF; - abrt_error = temp; + /*4MB page*/ + if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (((CPL == 3) && !cpl_override) || (is486 && (cr0 & WP_FLAG))))) { + cr2 = addr; + temp &= 1; + if (CPL == 3) + temp |= 4; + if (rw) + temp |= 2; + cpu_state.abrt = ABRT_PF; + abrt_error = temp; - return 0xffffffffffffffffULL; - } + return 0xffffffffffffffffULL; + } - mmu_perm = temp & 4; - rammap(addr2) |= (rw ? 0x60 : 0x20); + mmu_perm = temp & 4; + rammap(addr2) |= (rw ? 0x60 : 0x20); - return (temp & ~0x3fffff) + (addr & 0x3fffff); + return (temp & ~0x3fffff) + (addr & 0x3fffff); } - temp = rammap((temp & ~0xfff) + ((addr >> 10) & 0xffc)); + temp = rammap((temp & ~0xfff) + ((addr >> 10) & 0xffc)); temp3 = temp & temp2; if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && (((CPL == 3) && !cpl_override) || (is486 && (cr0 & WP_FLAG))))) { - cr2 = addr; - temp &= 1; - if (CPL == 3) - temp |= 4; - if (rw) - temp |= 2; - cpu_state.abrt = ABRT_PF; - abrt_error = temp; - return 0xffffffffffffffffULL; + cr2 = addr; + temp &= 1; + if (CPL == 3) + temp |= 4; + if (rw) + temp |= 2; + cpu_state.abrt = ABRT_PF; + abrt_error = temp; + return 0xffffffffffffffffULL; } mmu_perm = temp & 4; @@ -348,7 +339,6 @@ mmutranslatereal_normal(uint32_t addr, int rw) return (uint64_t) ((temp & ~0xfff) + (addr & 0xfff)); } - static __inline uint64_t mmutranslatereal_pae(uint32_t addr, int rw) { @@ -356,64 +346,70 @@ mmutranslatereal_pae(uint32_t addr, int rw) uint64_t addr2, addr3, addr4; if (cpu_state.abrt) - return 0xffffffffffffffffULL; + return 0xffffffffffffffffULL; addr2 = (cr3 & ~0x1f) + ((addr >> 27) & 0x18); temp = temp2 = rammap64(addr2) & 0x000000ffffffffffULL; if (!(temp & 1)) { - cr2 = addr; - temp &= 1; - if (CPL == 3) temp |= 4; - if (rw) temp |= 2; - cpu_state.abrt = ABRT_PF; - abrt_error = temp; - return 0xffffffffffffffffULL; + cr2 = addr; + temp &= 1; + if (CPL == 3) + temp |= 4; + if (rw) + temp |= 2; + cpu_state.abrt = ABRT_PF; + abrt_error = temp; + return 0xffffffffffffffffULL; } addr3 = (temp & ~0xfffULL) + ((addr >> 18) & 0xff8); temp = temp4 = rammap64(addr3) & 0x000000ffffffffffULL; - temp3 = temp & temp2; + temp3 = temp & temp2; if (!(temp & 1)) { - cr2 = addr; - temp &= 1; - if (CPL == 3) temp |= 4; - if (rw) temp |= 2; - cpu_state.abrt = ABRT_PF; - abrt_error = temp; - return 0xffffffffffffffffULL; + cr2 = addr; + temp &= 1; + if (CPL == 3) + temp |= 4; + if (rw) + temp |= 2; + cpu_state.abrt = ABRT_PF; + abrt_error = temp; + return 0xffffffffffffffffULL; } if (temp & 0x80) { - /*2MB page*/ - if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (((CPL == 3) && !cpl_override) || (cr0 & WP_FLAG)))) { - cr2 = addr; - temp &= 1; - if (CPL == 3) - temp |= 4; - if (rw) - temp |= 2; - cpu_state.abrt = ABRT_PF; - abrt_error = temp; + /*2MB page*/ + if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (((CPL == 3) && !cpl_override) || (cr0 & WP_FLAG)))) { + cr2 = addr; + temp &= 1; + if (CPL == 3) + temp |= 4; + if (rw) + temp |= 2; + cpu_state.abrt = ABRT_PF; + abrt_error = temp; - return 0xffffffffffffffffULL; - } - mmu_perm = temp & 4; - rammap64(addr3) |= (rw ? 0x60 : 0x20); + return 0xffffffffffffffffULL; + } + mmu_perm = temp & 4; + rammap64(addr3) |= (rw ? 0x60 : 0x20); - return ((temp & ~0x1fffffULL) + (addr & 0x1fffffULL)) & 0x000000ffffffffffULL; + return ((temp & ~0x1fffffULL) + (addr & 0x1fffffULL)) & 0x000000ffffffffffULL; } addr4 = (temp & ~0xfffULL) + ((addr >> 9) & 0xff8); - temp = rammap64(addr4) & 0x000000ffffffffffULL; + temp = rammap64(addr4) & 0x000000ffffffffffULL; temp3 = temp & temp4; if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && (((CPL == 3) && !cpl_override) || (cr0 & WP_FLAG)))) { - cr2 = addr; - temp &= 1; - if (CPL == 3) temp |= 4; - if (rw) temp |= 2; - cpu_state.abrt = ABRT_PF; - abrt_error = temp; - return 0xffffffffffffffffULL; + cr2 = addr; + temp &= 1; + if (CPL == 3) + temp |= 4; + if (rw) + temp |= 2; + cpu_state.abrt = ABRT_PF; + abrt_error = temp; + return 0xffffffffffffffffULL; } mmu_perm = temp & 4; @@ -423,140 +419,133 @@ mmutranslatereal_pae(uint32_t addr, int rw) return ((temp & ~0xfffULL) + ((uint64_t) (addr & 0xfff))) & 0x000000ffffffffffULL; } - uint64_t mmutranslatereal(uint32_t addr, int rw) { /* Fast path to return invalid without any call if an exception has occurred beforehand. */ if (cpu_state.abrt) - return 0xffffffffffffffffULL; + return 0xffffffffffffffffULL; if (cr4 & CR4_PAE) - return mmutranslatereal_pae(addr, rw); + return mmutranslatereal_pae(addr, rw); else - return mmutranslatereal_normal(addr, rw); + return mmutranslatereal_normal(addr, rw); } - /* This is needed because the old recompiler calls this to check for page fault. */ uint32_t mmutranslatereal32(uint32_t addr, int rw) { /* Fast path to return invalid without any call if an exception has occurred beforehand. */ if (cpu_state.abrt) - return (uint32_t) 0xffffffffffffffffULL; + return (uint32_t) 0xffffffffffffffffULL; return (uint32_t) mmutranslatereal(addr, rw); } - static __inline uint64_t mmutranslate_noabrt_normal(uint32_t addr, int rw) { - uint32_t temp,temp2,temp3; + uint32_t temp, temp2, temp3; uint32_t addr2; if (cpu_state.abrt) - return 0xffffffffffffffffULL; + return 0xffffffffffffffffULL; addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc)); temp = temp2 = rammap(addr2); - if (! (temp & 1)) - return 0xffffffffffffffffULL; + if (!(temp & 1)) + return 0xffffffffffffffffULL; if ((temp & 0x80) && (cr4 & CR4_PSE)) { - /*4MB page*/ - if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && ((CPL == 3) || (cr0 & WP_FLAG)))) - return 0xffffffffffffffffULL; + /*4MB page*/ + if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && ((CPL == 3) || (cr0 & WP_FLAG)))) + return 0xffffffffffffffffULL; - return (temp & ~0x3fffff) + (addr & 0x3fffff); + return (temp & ~0x3fffff) + (addr & 0x3fffff); } - temp = rammap((temp & ~0xfff) + ((addr >> 10) & 0xffc)); + temp = rammap((temp & ~0xfff) + ((addr >> 10) & 0xffc)); temp3 = temp & temp2; if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && ((CPL == 3) || (cr0 & WP_FLAG)))) - return 0xffffffffffffffffULL; + return 0xffffffffffffffffULL; return (uint64_t) ((temp & ~0xfff) + (addr & 0xfff)); } - static __inline uint64_t mmutranslate_noabrt_pae(uint32_t addr, int rw) { - uint64_t temp,temp2,temp3,temp4; - uint64_t addr2,addr3,addr4; + uint64_t temp, temp2, temp3, temp4; + uint64_t addr2, addr3, addr4; if (cpu_state.abrt) - return 0xffffffffffffffffULL; + return 0xffffffffffffffffULL; addr2 = (cr3 & ~0x1f) + ((addr >> 27) & 0x18); temp = temp2 = rammap64(addr2) & 0x000000ffffffffffULL; - if (! (temp & 1)) - return 0xffffffffffffffffULL; + if (!(temp & 1)) + return 0xffffffffffffffffULL; addr3 = (temp & ~0xfffULL) + ((addr >> 18) & 0xff8); temp = temp4 = rammap64(addr3) & 0x000000ffffffffffULL; - temp3 = temp & temp2; + temp3 = temp & temp2; - if (! (temp & 1)) - return 0xffffffffffffffffULL; + if (!(temp & 1)) + return 0xffffffffffffffffULL; if (temp & 0x80) { - /*2MB page*/ - if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && ((CPL == 3) || (cr0 & WP_FLAG)))) - return 0xffffffffffffffffULL; + /*2MB page*/ + if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && ((CPL == 3) || (cr0 & WP_FLAG)))) + return 0xffffffffffffffffULL; - return ((temp & ~0x1fffffULL) + (addr & 0x1fffff)) & 0x000000ffffffffffULL; + return ((temp & ~0x1fffffULL) + (addr & 0x1fffff)) & 0x000000ffffffffffULL; } addr4 = (temp & ~0xfffULL) + ((addr >> 9) & 0xff8); - temp = rammap64(addr4) & 0x000000ffffffffffULL;; + temp = rammap64(addr4) & 0x000000ffffffffffULL; + ; temp3 = temp & temp4; - if (!(temp&1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && ((CPL == 3) || (cr0 & WP_FLAG)))) - return 0xffffffffffffffffULL; + if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && ((CPL == 3) || (cr0 & WP_FLAG)))) + return 0xffffffffffffffffULL; return ((temp & ~0xfffULL) + ((uint64_t) (addr & 0xfff))) & 0x000000ffffffffffULL; } - uint64_t mmutranslate_noabrt(uint32_t addr, int rw) { /* Fast path to return invalid without any call if an exception has occurred beforehand. */ if (cpu_state.abrt) - return 0xffffffffffffffffULL; + return 0xffffffffffffffffULL; if (cr4 & CR4_PAE) - return mmutranslate_noabrt_pae(addr, rw); + return mmutranslate_noabrt_pae(addr, rw); else - return mmutranslate_noabrt_normal(addr, rw); + return mmutranslate_noabrt_normal(addr, rw); } - void mmu_invalidate(uint32_t addr) { flushmmucache_cr3(); } - uint8_t mem_addr_range_match(uint32_t addr, uint32_t start, uint32_t len) { if (addr < start) - return 0; - else if (addr >= (start + len)) - return 0; - else - return 1; + return 0; + else if (addr >= (start + len)) + return 0; + else + return 1; } - uint32_t mem_addr_translate(uint32_t addr, uint32_t chunk_start, uint32_t len) { @@ -565,7 +554,6 @@ mem_addr_translate(uint32_t addr, uint32_t chunk_start, uint32_t len) return chunk_start + (addr & mask); } - void addreadlookup(uint32_t virt, uint32_t phys) { @@ -573,35 +561,36 @@ addreadlookup(uint32_t virt, uint32_t phys) uint32_t a; #endif - if (virt == 0xffffffff) return; + if (virt == 0xffffffff) + return; - if (readlookup2[virt>>12] != (uintptr_t) LOOKUP_INV) return; + if (readlookup2[virt >> 12] != (uintptr_t) LOOKUP_INV) + return; if (readlookup[readlnext] != (int) 0xffffffff) { - if ((readlookup[readlnext] == ((es + DI) >> 12)) || (readlookup[readlnext] == ((es + EDI) >> 12))) - uncached = 1; - readlookup2[readlookup[readlnext]] = LOOKUP_INV; + if ((readlookup[readlnext] == ((es + DI) >> 12)) || (readlookup[readlnext] == ((es + EDI) >> 12))) + uncached = 1; + readlookup2[readlookup[readlnext]] = LOOKUP_INV; } #if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64) - readlookup2[virt>>12] = (uintptr_t)&ram[(uintptr_t)(phys & ~0xFFF) - (uintptr_t)(virt & ~0xfff)]; + readlookup2[virt >> 12] = (uintptr_t) &ram[(uintptr_t) (phys & ~0xFFF) - (uintptr_t) (virt & ~0xfff)]; #else - a = ((uint32_t)(phys & ~0xfff) - (uint32_t)(virt & ~0xfff)); + a = ((uint32_t) (phys & ~0xfff) - (uint32_t) (virt & ~0xfff)); if ((phys & ~0xfff) >= (1 << 30)) - readlookup2[virt>>12] = (uintptr_t)&ram2[a - (1 << 30)]; + readlookup2[virt >> 12] = (uintptr_t) &ram2[a - (1 << 30)]; else - readlookup2[virt>>12] = (uintptr_t)&ram[a]; + readlookup2[virt >> 12] = (uintptr_t) &ram[a]; #endif - readlookupp[virt>>12] = mmu_perm; + readlookupp[virt >> 12] = mmu_perm; readlookup[readlnext++] = virt >> 12; - readlnext &= (cachesize-1); + readlnext &= (cachesize - 1); cycles -= 9; } - void addwritelookup(uint32_t virt, uint32_t phys) { @@ -609,43 +598,45 @@ addwritelookup(uint32_t virt, uint32_t phys) uint32_t a; #endif - if (virt == 0xffffffff) return; + if (virt == 0xffffffff) + return; - if (page_lookup[virt >> 12]) return; + if (page_lookup[virt >> 12]) + return; if (writelookup[writelnext] != -1) { - page_lookup[writelookup[writelnext]] = NULL; - writelookup2[writelookup[writelnext]] = LOOKUP_INV; + page_lookup[writelookup[writelnext]] = NULL; + writelookup2[writelookup[writelnext]] = LOOKUP_INV; } #ifdef USE_NEW_DYNAREC -#ifdef USE_DYNAREC +# ifdef USE_DYNAREC if (pages[phys >> 12].block || (phys & ~0xfff) == recomp_page) { -#else +# else if (pages[phys >> 12].block) { -#endif +# endif #else -#ifdef USE_DYNAREC +# ifdef USE_DYNAREC if (pages[phys >> 12].block[0] || pages[phys >> 12].block[1] || pages[phys >> 12].block[2] || pages[phys >> 12].block[3] || (phys & ~0xfff) == recomp_page) { -#else +# else if (pages[phys >> 12].block[0] || pages[phys >> 12].block[1] || pages[phys >> 12].block[2] || pages[phys >> 12].block[3]) { +# endif #endif -#endif - page_lookup[virt >> 12] = &pages[phys >> 12]; - page_lookupp[virt >> 12] = mmu_perm; + page_lookup[virt >> 12] = &pages[phys >> 12]; + page_lookupp[virt >> 12] = mmu_perm; } else { #if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64) - writelookup2[virt>>12] = (uintptr_t)&ram[(uintptr_t)(phys & ~0xFFF) - (uintptr_t)(virt & ~0xfff)]; + writelookup2[virt >> 12] = (uintptr_t) &ram[(uintptr_t) (phys & ~0xFFF) - (uintptr_t) (virt & ~0xfff)]; #else - a = ((uint32_t)(phys & ~0xfff) - (uint32_t)(virt & ~0xfff)); + a = ((uint32_t) (phys & ~0xfff) - (uint32_t) (virt & ~0xfff)); - if ((phys & ~0xfff) >= (1 << 30)) - writelookup2[virt>>12] = (uintptr_t)&ram2[a - (1 << 30)]; - else - writelookup2[virt>>12] = (uintptr_t)&ram[a]; + if ((phys & ~0xfff) >= (1 << 30)) + writelookup2[virt >> 12] = (uintptr_t) &ram2[a - (1 << 30)]; + else + writelookup2[virt >> 12] = (uintptr_t) &ram[a]; #endif } - writelookupp[virt>>12] = mmu_perm; + writelookupp[virt >> 12] = mmu_perm; writelookup[writelnext++] = virt >> 12; writelnext &= (cachesize - 1); @@ -653,7 +644,6 @@ addwritelookup(uint32_t virt, uint32_t phys) cycles -= 9; } - uint8_t * getpccache(uint32_t a) { @@ -663,68 +653,67 @@ getpccache(uint32_t a) a2 = a; if (cr0 >> 31) { - a64 = mmutranslate_read(a64); + a64 = mmutranslate_read(a64); - if (a64 == 0xffffffffffffffffULL) return ram; + if (a64 == 0xffffffffffffffffULL) + return ram; } a64 &= rammask; if (_mem_exec[a64 >> MEM_GRANULARITY_BITS]) { - if (is286) { - if (read_mapping[a64 >> MEM_GRANULARITY_BITS] && (read_mapping[a64 >> MEM_GRANULARITY_BITS]->flags & MEM_MAPPING_ROM_WS)) - cpu_prefetch_cycles = cpu_rom_prefetch_cycles; - else - cpu_prefetch_cycles = cpu_mem_prefetch_cycles; - } + if (is286) { + if (read_mapping[a64 >> MEM_GRANULARITY_BITS] && (read_mapping[a64 >> MEM_GRANULARITY_BITS]->flags & MEM_MAPPING_ROM_WS)) + cpu_prefetch_cycles = cpu_rom_prefetch_cycles; + else + cpu_prefetch_cycles = cpu_mem_prefetch_cycles; + } - return &_mem_exec[a64 >> MEM_GRANULARITY_BITS][(uintptr_t)(a64 & MEM_GRANULARITY_PAGE) - (uintptr_t)(a2 & ~0xfff)]; + return &_mem_exec[a64 >> MEM_GRANULARITY_BITS][(uintptr_t) (a64 & MEM_GRANULARITY_PAGE) - (uintptr_t) (a2 & ~0xfff)]; } mem_log("Bad getpccache %08X%08X\n", (uint32_t) (a64 >> 32), (uint32_t) (a64 & 0xffffffffULL)); - return (uint8_t *)&ff_pccache; + return (uint8_t *) &ff_pccache; } - uint8_t read_mem_b(uint32_t addr) { mem_mapping_t *map; - uint8_t ret = 0xff; - int old_cycles = cycles; + uint8_t ret = 0xff; + int old_cycles = cycles; mem_logical_addr = addr; addr &= rammask; map = read_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->read_b) - ret = map->read_b(addr, map->p); + ret = map->read_b(addr, map->p); resub_cycles(old_cycles); return ret; } - uint16_t read_mem_w(uint32_t addr) { mem_mapping_t *map; - uint16_t ret = 0xffff; - int old_cycles = cycles; + uint16_t ret = 0xffff; + int old_cycles = cycles; mem_logical_addr = addr; addr &= rammask; if (addr & 1) - ret = read_mem_b(addr) | (read_mem_b(addr + 1) << 8); + ret = read_mem_b(addr) | (read_mem_b(addr + 1) << 8); else { - map = read_mapping[addr >> MEM_GRANULARITY_BITS]; + map = read_mapping[addr >> MEM_GRANULARITY_BITS]; - if (map && map->read_w) - ret = map->read_w(addr, map->p); - else if (map && map->read_b) - ret = map->read_b(addr, map->p) | (map->read_b(addr + 1, map->p) << 8); + if (map && map->read_w) + ret = map->read_w(addr, map->p); + else if (map && map->read_b) + ret = map->read_b(addr, map->p) | (map->read_b(addr + 1, map->p) << 8); } resub_cycles(old_cycles); @@ -732,115 +721,110 @@ read_mem_w(uint32_t addr) return ret; } - void write_mem_b(uint32_t addr, uint8_t val) { mem_mapping_t *map; - int old_cycles = cycles; + int old_cycles = cycles; mem_logical_addr = addr; addr &= rammask; map = write_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->write_b) - map->write_b(addr, val, map->p); + map->write_b(addr, val, map->p); resub_cycles(old_cycles); } - void write_mem_w(uint32_t addr, uint16_t val) { mem_mapping_t *map; - int old_cycles = cycles; + int old_cycles = cycles; mem_logical_addr = addr; addr &= rammask; if (addr & 1) { - write_mem_b(addr, val); - write_mem_b(addr + 1, val >> 8); + write_mem_b(addr, val); + write_mem_b(addr + 1, val >> 8); } else { - map = write_mapping[addr >> MEM_GRANULARITY_BITS]; - if (map) { - if (map->write_w) - map->write_w(addr, val, map->p); - else if (map->write_b) { - map->write_b(addr, val, map->p); - map->write_b(addr + 1, val >> 8, map->p); - } - } + map = write_mapping[addr >> MEM_GRANULARITY_BITS]; + if (map) { + if (map->write_w) + map->write_w(addr, val, map->p); + else if (map->write_b) { + map->write_b(addr, val, map->p); + map->write_b(addr + 1, val >> 8, map->p); + } + } } resub_cycles(old_cycles); } - uint8_t readmembl(uint32_t addr) { mem_mapping_t *map; - uint64_t a; + uint64_t a; GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_READ, 1); - addr64 = (uint64_t) addr; + addr64 = (uint64_t) addr; mem_logical_addr = addr; high_page = 0; if (cr0 >> 31) { - a = mmutranslate_read(addr); - addr64 = (uint32_t) a; + a = mmutranslate_read(addr); + addr64 = (uint32_t) a; - if (a > 0xffffffffULL) - return 0xff; + if (a > 0xffffffffULL) + return 0xff; } addr = (uint32_t) (addr64 & rammask); map = read_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->read_b) - return map->read_b(addr, map->p); + return map->read_b(addr, map->p); return 0xff; } - void writemembl(uint32_t addr, uint8_t val) { mem_mapping_t *map; - uint64_t a; + uint64_t a; GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_WRITE, 1); - addr64 = (uint64_t) addr; + addr64 = (uint64_t) addr; mem_logical_addr = addr; high_page = 0; - if (page_lookup[addr>>12] && page_lookup[addr>>12]->write_b) { - page_lookup[addr>>12]->write_b(addr, val, page_lookup[addr>>12]); - return; + if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_b) { + page_lookup[addr >> 12]->write_b(addr, val, page_lookup[addr >> 12]); + return; } if (cr0 >> 31) { - a = mmutranslate_write(addr); - addr64 = (uint32_t) a; + a = mmutranslate_write(addr); + addr64 = (uint32_t) a; - if (a > 0xffffffffULL) - return; + if (a > 0xffffffffULL) + return; } addr = (uint32_t) (addr64 & rammask); map = write_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->write_b) - map->write_b(addr, val, map->p); + map->write_b(addr, val, map->p); } - /* Read a byte from memory without MMU translation - result of previous MMU translation passed as value. */ uint8_t readmembl_no_mmut(uint32_t addr, uint32_t a64) @@ -852,21 +836,20 @@ readmembl_no_mmut(uint32_t addr, uint32_t a64) mem_logical_addr = addr; if (cr0 >> 31) { - if (cpu_state.abrt || high_page) - return 0xff; + if (cpu_state.abrt || high_page) + return 0xff; - addr = a64 & rammask; + addr = a64 & rammask; } else - addr &= rammask; + addr &= rammask; map = read_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->read_b) - return map->read_b(addr, map->p); + return map->read_b(addr, map->p); return 0xff; } - /* Write a byte to memory without MMU translation - result of previous MMU translation passed as value. */ void writemembl_no_mmut(uint32_t addr, uint32_t a64, uint8_t val) @@ -878,30 +861,29 @@ writemembl_no_mmut(uint32_t addr, uint32_t a64, uint8_t val) mem_logical_addr = addr; if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_b) { - page_lookup[addr >> 12]->write_b(addr, val, page_lookup[addr >> 12]); - return; + page_lookup[addr >> 12]->write_b(addr, val, page_lookup[addr >> 12]); + return; } if (cr0 >> 31) { - if (cpu_state.abrt || high_page) - return; + if (cpu_state.abrt || high_page) + return; - addr = a64 & rammask; + addr = a64 & rammask; } else - addr &= rammask; + addr &= rammask; map = write_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->write_b) - map->write_b(addr, val, map->p); + map->write_b(addr, val, map->p); } - uint16_t readmemwl(uint32_t addr) { mem_mapping_t *map; - int i; - uint64_t a; + int i; + uint64_t a; addr64a[0] = addr; addr64a[1] = addr + 1; @@ -912,58 +894,55 @@ readmemwl(uint32_t addr) high_page = 0; if (addr & 1) { - if (!cpu_cyrix_alignment || (addr & 7) == 7) - cycles -= timing_misaligned; - if ((addr & 0xfff) > 0xffe) { - if (cr0 >> 31) { - for (i = 0; i < 2; i++) { - a = mmutranslate_read(addr + i); - addr64a[i] = (uint32_t) a; + if (!cpu_cyrix_alignment || (addr & 7) == 7) + cycles -= timing_misaligned; + if ((addr & 0xfff) > 0xffe) { + if (cr0 >> 31) { + for (i = 0; i < 2; i++) { + a = mmutranslate_read(addr + i); + addr64a[i] = (uint32_t) a; - if (a > 0xffffffffULL) - return 0xffff; - } - } + if (a > 0xffffffffULL) + return 0xffff; + } + } - return readmembl_no_mmut(addr, addr64a[0]) | - (((uint16_t) readmembl_no_mmut(addr + 1, addr64a[1])) << 8); - } else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { - mmu_perm = readlookupp[addr >> 12]; - return *(uint16_t *)(readlookup2[addr >> 12] + addr); - } + return readmembl_no_mmut(addr, addr64a[0]) | (((uint16_t) readmembl_no_mmut(addr + 1, addr64a[1])) << 8); + } else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { + mmu_perm = readlookupp[addr >> 12]; + return *(uint16_t *) (readlookup2[addr >> 12] + addr); + } } if (cr0 >> 31) { - a = mmutranslate_read(addr); - addr64a[0] = (uint32_t) a; + a = mmutranslate_read(addr); + addr64a[0] = (uint32_t) a; - if (a > 0xffffffffULL) - return 0xffff; + if (a > 0xffffffffULL) + return 0xffff; } else - addr64a[0] = (uint64_t) addr; + addr64a[0] = (uint64_t) addr; addr = addr64a[0] & rammask; map = read_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->read_w) - return map->read_w(addr, map->p); + return map->read_w(addr, map->p); if (map && map->read_b) { - return map->read_b(addr, map->p) | - ((uint16_t) (map->read_b(addr + 1, map->p)) << 8); + return map->read_b(addr, map->p) | ((uint16_t) (map->read_b(addr + 1, map->p)) << 8); } return 0xffff; } - void writememwl(uint32_t addr, uint16_t val) { mem_mapping_t *map; - int i; - uint64_t a; + int i; + uint64_t a; addr64a[0] = addr; addr64a[1] = addr + 1; @@ -974,47 +953,47 @@ writememwl(uint32_t addr, uint16_t val) high_page = 0; if (addr & 1) { - if (!cpu_cyrix_alignment || (addr & 7) == 7) - cycles -= timing_misaligned; - if ((addr & 0xfff) > 0xffe) { - if (cr0 >> 31) { - for (i = 0; i < 2; i++) { - /* Do not translate a page that has a valid lookup, as that is by definition valid - and the whole purpose of the lookup is to avoid repeat identical translations. */ - if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) { - a = mmutranslate_write(addr + i); - addr64a[i] = (uint32_t) a; + if (!cpu_cyrix_alignment || (addr & 7) == 7) + cycles -= timing_misaligned; + if ((addr & 0xfff) > 0xffe) { + if (cr0 >> 31) { + for (i = 0; i < 2; i++) { + /* Do not translate a page that has a valid lookup, as that is by definition valid + and the whole purpose of the lookup is to avoid repeat identical translations. */ + if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) { + a = mmutranslate_write(addr + i); + addr64a[i] = (uint32_t) a; - if (a > 0xffffffffULL) - return; - } - } - } + if (a > 0xffffffffULL) + return; + } + } + } - /* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass - their result as a parameter to be used if needed. */ - writemembl_no_mmut(addr, addr64a[0], val); - writemembl_no_mmut(addr + 1, addr64a[1], val >> 8); - return; - } else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { - mmu_perm = writelookupp[addr >> 12]; - *(uint16_t *)(writelookup2[addr >> 12] + addr) = val; - return; - } + /* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass + their result as a parameter to be used if needed. */ + writemembl_no_mmut(addr, addr64a[0], val); + writemembl_no_mmut(addr + 1, addr64a[1], val >> 8); + return; + } else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { + mmu_perm = writelookupp[addr >> 12]; + *(uint16_t *) (writelookup2[addr >> 12] + addr) = val; + return; + } } if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_w) { - page_lookup[addr >> 12]->write_w(addr, val, page_lookup[addr >> 12]); - mmu_perm = page_lookupp[addr >> 12]; - return; + page_lookup[addr >> 12]->write_w(addr, val, page_lookup[addr >> 12]); + mmu_perm = page_lookupp[addr >> 12]; + return; } if (cr0 >> 31) { - a = mmutranslate_write(addr); - addr64a[0] = (uint32_t) a; + a = mmutranslate_write(addr); + addr64a[0] = (uint32_t) a; - if (a > 0xffffffffULL) - return; + if (a > 0xffffffffULL) + return; } addr = addr64a[0] & rammask; @@ -1022,18 +1001,17 @@ writememwl(uint32_t addr, uint16_t val) map = write_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->write_w) { - map->write_w(addr, val, map->p); - return; + map->write_w(addr, val, map->p); + return; } if (map && map->write_b) { - map->write_b(addr, val, map->p); - map->write_b(addr + 1, val >> 8, map->p); - return; + map->write_b(addr, val, map->p); + map->write_b(addr + 1, val >> 8, map->p); + return; } } - /* Read a word from memory without MMU translation - results of previous MMU translation passed as array. */ uint16_t readmemwl_no_mmut(uint32_t addr, uint32_t *a64) @@ -1045,44 +1023,41 @@ readmemwl_no_mmut(uint32_t addr, uint32_t *a64) mem_logical_addr = addr; if (addr & 1) { - if (!cpu_cyrix_alignment || (addr & 7) == 7) - cycles -= timing_misaligned; - if ((addr & 0xfff) > 0xffe) { - if (cr0 >> 31) { - if (cpu_state.abrt || high_page) - return 0xffff; - } + if (!cpu_cyrix_alignment || (addr & 7) == 7) + cycles -= timing_misaligned; + if ((addr & 0xfff) > 0xffe) { + if (cr0 >> 31) { + if (cpu_state.abrt || high_page) + return 0xffff; + } - return readmembl_no_mmut(addr, a64[0]) | - (((uint16_t) readmembl_no_mmut(addr + 1, a64[1])) << 8); - } else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { - mmu_perm = readlookupp[addr >> 12]; - return *(uint16_t *)(readlookup2[addr >> 12] + addr); - } + return readmembl_no_mmut(addr, a64[0]) | (((uint16_t) readmembl_no_mmut(addr + 1, a64[1])) << 8); + } else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { + mmu_perm = readlookupp[addr >> 12]; + return *(uint16_t *) (readlookup2[addr >> 12] + addr); + } } if (cr0 >> 31) { - if (cpu_state.abrt || high_page) - return 0xffff; + if (cpu_state.abrt || high_page) + return 0xffff; - addr = (uint32_t) (a64[0] & rammask); + addr = (uint32_t) (a64[0] & rammask); } else - addr &= rammask; + addr &= rammask; map = read_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->read_w) - return map->read_w(addr, map->p); + return map->read_w(addr, map->p); if (map && map->read_b) { - return map->read_b(addr, map->p) | - ((uint16_t) (map->read_b(addr + 1, map->p)) << 8); + return map->read_b(addr, map->p) | ((uint16_t) (map->read_b(addr + 1, map->p)) << 8); } return 0xffff; } - /* Write a word to memory without MMU translation - results of previous MMU translation passed as array. */ void writememwl_no_mmut(uint32_t addr, uint32_t *a64, uint16_t val) @@ -1094,62 +1069,61 @@ writememwl_no_mmut(uint32_t addr, uint32_t *a64, uint16_t val) mem_logical_addr = addr; if (addr & 1) { - if (!cpu_cyrix_alignment || (addr & 7) == 7) - cycles -= timing_misaligned; - if ((addr & 0xfff) > 0xffe) { - if (cr0 >> 31) { - if (cpu_state.abrt || high_page) - return; - } + if (!cpu_cyrix_alignment || (addr & 7) == 7) + cycles -= timing_misaligned; + if ((addr & 0xfff) > 0xffe) { + if (cr0 >> 31) { + if (cpu_state.abrt || high_page) + return; + } - writemembl_no_mmut(addr, a64[0], val); - writemembl_no_mmut(addr + 1, a64[1], val >> 8); - return; - } else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { - mmu_perm = writelookupp[addr >> 12]; - *(uint16_t *)(writelookup2[addr >> 12] + addr) = val; - return; - } + writemembl_no_mmut(addr, a64[0], val); + writemembl_no_mmut(addr + 1, a64[1], val >> 8); + return; + } else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { + mmu_perm = writelookupp[addr >> 12]; + *(uint16_t *) (writelookup2[addr >> 12] + addr) = val; + return; + } } if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_w) { - mmu_perm = page_lookupp[addr >> 12]; - page_lookup[addr >> 12]->write_w(addr, val, page_lookup[addr >> 12]); - return; + mmu_perm = page_lookupp[addr >> 12]; + page_lookup[addr >> 12]->write_w(addr, val, page_lookup[addr >> 12]); + return; } if (cr0 >> 31) { - if (cpu_state.abrt || high_page) - return; + if (cpu_state.abrt || high_page) + return; - addr = (uint32_t) (a64[0] & rammask); + addr = (uint32_t) (a64[0] & rammask); } else - addr &= rammask; + addr &= rammask; map = write_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->write_w) { - map->write_w(addr, val, map->p); - return; + map->write_w(addr, val, map->p); + return; } if (map && map->write_b) { - map->write_b(addr, val, map->p); - map->write_b(addr + 1, val >> 8, map->p); - return; + map->write_b(addr, val, map->p); + map->write_b(addr + 1, val >> 8, map->p); + return; } } - uint32_t readmemll(uint32_t addr) { mem_mapping_t *map; - int i; - uint64_t a = 0x0000000000000000ULL; + int i; + uint64_t a = 0x0000000000000000ULL; for (i = 0; i < 4; i++) - addr64a[i] = (uint64_t) (addr + i); + addr64a[i] = (uint64_t) (addr + i); GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_READ, 4); mem_logical_addr = addr; @@ -1157,47 +1131,46 @@ readmemll(uint32_t addr) high_page = 0; if (addr & 3) { - if (!cpu_cyrix_alignment || (addr & 7) > 4) - cycles -= timing_misaligned; - if ((addr & 0xfff) > 0xffc) { - if (cr0 >> 31) { - for (i = 0; i < 4; i++) { - if (i == 0) { - a = mmutranslate_read(addr + i); - addr64a[i] = (uint32_t) a; - } else if (!((addr + i) & 0xfff)) { - a = mmutranslate_read(addr + 3); - addr64a[i] = (uint32_t) a; - if (!cpu_state.abrt) { - a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); - addr64a[i] = (uint32_t) a; - } - } else { - a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); - addr64a[i] = (uint32_t) a; - } + if (!cpu_cyrix_alignment || (addr & 7) > 4) + cycles -= timing_misaligned; + if ((addr & 0xfff) > 0xffc) { + if (cr0 >> 31) { + for (i = 0; i < 4; i++) { + if (i == 0) { + a = mmutranslate_read(addr + i); + addr64a[i] = (uint32_t) a; + } else if (!((addr + i) & 0xfff)) { + a = mmutranslate_read(addr + 3); + addr64a[i] = (uint32_t) a; + if (!cpu_state.abrt) { + a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); + addr64a[i] = (uint32_t) a; + } + } else { + a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); + addr64a[i] = (uint32_t) a; + } - if (a > 0xffffffffULL) - return 0xffff; - } - } + if (a > 0xffffffffULL) + return 0xffff; + } + } - /* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass - their result as a parameter to be used if needed. */ - return readmemwl_no_mmut(addr, addr64a) | - (((uint32_t) readmemwl_no_mmut(addr + 2, &(addr64a[2]))) << 16); - } else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { - mmu_perm = readlookupp[addr >> 12]; - return *(uint32_t *)(readlookup2[addr >> 12] + addr); - } + /* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass + their result as a parameter to be used if needed. */ + return readmemwl_no_mmut(addr, addr64a) | (((uint32_t) readmemwl_no_mmut(addr + 2, &(addr64a[2]))) << 16); + } else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { + mmu_perm = readlookupp[addr >> 12]; + return *(uint32_t *) (readlookup2[addr >> 12] + addr); + } } if (cr0 >> 31) { - a = mmutranslate_read(addr); - addr64a[0] = (uint32_t) a; + a = mmutranslate_read(addr); + addr64a[0] = (uint32_t) a; - if (a > 0xffffffffULL) - return 0xffffffff; + if (a > 0xffffffffULL) + return 0xffffffff; } addr = addr64a[0] & rammask; @@ -1205,31 +1178,26 @@ readmemll(uint32_t addr) map = read_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->read_l) - return map->read_l(addr, map->p); + return map->read_l(addr, map->p); if (map && map->read_w) - return map->read_w(addr, map->p) | - ((uint32_t) (map->read_w(addr + 2, map->p)) << 16); + return map->read_w(addr, map->p) | ((uint32_t) (map->read_w(addr + 2, map->p)) << 16); if (map && map->read_b) - return map->read_b(addr, map->p) | - ((uint32_t) (map->read_b(addr + 1, map->p)) << 8) | - ((uint32_t) (map->read_b(addr + 2, map->p)) << 16) | - ((uint32_t) (map->read_b(addr + 3, map->p)) << 24); + return map->read_b(addr, map->p) | ((uint32_t) (map->read_b(addr + 1, map->p)) << 8) | ((uint32_t) (map->read_b(addr + 2, map->p)) << 16) | ((uint32_t) (map->read_b(addr + 3, map->p)) << 24); return 0xffffffff; } - void writememll(uint32_t addr, uint32_t val) { mem_mapping_t *map; - int i; - uint64_t a = 0x0000000000000000ULL; + int i; + uint64_t a = 0x0000000000000000ULL; for (i = 0; i < 4; i++) - addr64a[i] = (uint64_t) (addr + i); + addr64a[i] = (uint64_t) (addr + i); GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_WRITE, 4); mem_logical_addr = addr; @@ -1237,59 +1205,59 @@ writememll(uint32_t addr, uint32_t val) high_page = 0; if (addr & 3) { - if (!cpu_cyrix_alignment || (addr & 7) > 4) - cycles -= timing_misaligned; - if ((addr & 0xfff) > 0xffc) { - if (cr0 >> 31) { - for (i = 0; i < 4; i++) { - /* Do not translate a page that has a valid lookup, as that is by definition valid - and the whole purpose of the lookup is to avoid repeat identical translations. */ - if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) { - if (i == 0) { - a = mmutranslate_write(addr + i); - addr64a[i] = (uint32_t) a; - } else if (!((addr + i) & 0xfff)) { - a = mmutranslate_write(addr + 3); - addr64a[i] = (uint32_t) a; - if (!cpu_state.abrt) { - a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); - addr64a[i] = (uint32_t) a; - } - } else { - a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); - addr64a[i] = (uint32_t) a; - } + if (!cpu_cyrix_alignment || (addr & 7) > 4) + cycles -= timing_misaligned; + if ((addr & 0xfff) > 0xffc) { + if (cr0 >> 31) { + for (i = 0; i < 4; i++) { + /* Do not translate a page that has a valid lookup, as that is by definition valid + and the whole purpose of the lookup is to avoid repeat identical translations. */ + if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) { + if (i == 0) { + a = mmutranslate_write(addr + i); + addr64a[i] = (uint32_t) a; + } else if (!((addr + i) & 0xfff)) { + a = mmutranslate_write(addr + 3); + addr64a[i] = (uint32_t) a; + if (!cpu_state.abrt) { + a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); + addr64a[i] = (uint32_t) a; + } + } else { + a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); + addr64a[i] = (uint32_t) a; + } - if (a > 0xffffffffULL) - return; - } - } - } + if (a > 0xffffffffULL) + return; + } + } + } - /* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass - their result as a parameter to be used if needed. */ - writememwl_no_mmut(addr, &(addr64a[0]), val); - writememwl_no_mmut(addr + 2, &(addr64a[2]), val >> 16); - return; - } else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { - mmu_perm = writelookupp[addr >> 12]; - *(uint32_t *)(writelookup2[addr >> 12] + addr) = val; - return; - } + /* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass + their result as a parameter to be used if needed. */ + writememwl_no_mmut(addr, &(addr64a[0]), val); + writememwl_no_mmut(addr + 2, &(addr64a[2]), val >> 16); + return; + } else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { + mmu_perm = writelookupp[addr >> 12]; + *(uint32_t *) (writelookup2[addr >> 12] + addr) = val; + return; + } } if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_l) { - mmu_perm = page_lookupp[addr >> 12]; - page_lookup[addr >> 12]->write_l(addr, val, page_lookup[addr >> 12]); - return; + mmu_perm = page_lookupp[addr >> 12]; + page_lookup[addr >> 12]->write_l(addr, val, page_lookup[addr >> 12]); + return; } if (cr0 >> 31) { - a = mmutranslate_write(addr); - addr64a[0] = (uint32_t) a; + a = mmutranslate_write(addr); + addr64a[0] = (uint32_t) a; - if (a > 0xffffffffULL) - return; + if (a > 0xffffffffULL) + return; } addr = addr64a[0] & rammask; @@ -1297,24 +1265,23 @@ writememll(uint32_t addr, uint32_t val) map = write_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->write_l) { - map->write_l(addr, val, map->p); - return; + map->write_l(addr, val, map->p); + return; } if (map && map->write_w) { - map->write_w(addr, val, map->p); - map->write_w(addr + 2, val >> 16, map->p); - return; + map->write_w(addr, val, map->p); + map->write_w(addr + 2, val >> 16, map->p); + return; } if (map && map->write_b) { - map->write_b(addr, val, map->p); - map->write_b(addr + 1, val >> 8, map->p); - map->write_b(addr + 2, val >> 16, map->p); - map->write_b(addr + 3, val >> 24, map->p); - return; + map->write_b(addr, val, map->p); + map->write_b(addr + 1, val >> 8, map->p); + map->write_b(addr + 2, val >> 16, map->p); + map->write_b(addr + 3, val >> 24, map->p); + return; } } - /* Read a long from memory without MMU translation - results of previous MMU translation passed as array. */ uint32_t readmemll_no_mmut(uint32_t addr, uint32_t *a64) @@ -1326,49 +1293,43 @@ readmemll_no_mmut(uint32_t addr, uint32_t *a64) mem_logical_addr = addr; if (addr & 3) { - if (!cpu_cyrix_alignment || (addr & 7) > 4) - cycles -= timing_misaligned; - if ((addr & 0xfff) > 0xffc) { - if (cr0 >> 31) { - if (cpu_state.abrt || high_page) - return 0xffffffff; - } + if (!cpu_cyrix_alignment || (addr & 7) > 4) + cycles -= timing_misaligned; + if ((addr & 0xfff) > 0xffc) { + if (cr0 >> 31) { + if (cpu_state.abrt || high_page) + return 0xffffffff; + } - return readmemwl_no_mmut(addr, a64) | - ((uint32_t) (readmemwl_no_mmut(addr + 2, &(a64[2]))) << 16); - } else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { - mmu_perm = readlookupp[addr >> 12]; - return *(uint32_t *)(readlookup2[addr >> 12] + addr); - } + return readmemwl_no_mmut(addr, a64) | ((uint32_t) (readmemwl_no_mmut(addr + 2, &(a64[2]))) << 16); + } else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { + mmu_perm = readlookupp[addr >> 12]; + return *(uint32_t *) (readlookup2[addr >> 12] + addr); + } } if (cr0 >> 31) { - if (cpu_state.abrt || high_page) - return 0xffffffff; + if (cpu_state.abrt || high_page) + return 0xffffffff; - addr = (uint32_t) (a64[0] & rammask); + addr = (uint32_t) (a64[0] & rammask); } else - addr &= rammask; + addr &= rammask; map = read_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->read_l) - return map->read_l(addr, map->p); + return map->read_l(addr, map->p); if (map && map->read_w) - return map->read_w(addr, map->p) | - ((uint32_t) (map->read_w(addr + 2, map->p)) << 16); + return map->read_w(addr, map->p) | ((uint32_t) (map->read_w(addr + 2, map->p)) << 16); if (map && map->read_b) - return map->read_b(addr, map->p) | - ((uint32_t) (map->read_b(addr + 1, map->p)) << 8) | - ((uint32_t) (map->read_b(addr + 2, map->p)) << 16) | - ((uint32_t) (map->read_b(addr + 3, map->p)) << 24); + return map->read_b(addr, map->p) | ((uint32_t) (map->read_b(addr + 1, map->p)) << 8) | ((uint32_t) (map->read_b(addr + 2, map->p)) << 16) | ((uint32_t) (map->read_b(addr + 3, map->p)) << 24); return 0xffffffff; } - /* Write a long to memory without MMU translation - results of previous MMU translation passed as array. */ void writememll_no_mmut(uint32_t addr, uint32_t *a64, uint32_t val) @@ -1380,68 +1341,67 @@ writememll_no_mmut(uint32_t addr, uint32_t *a64, uint32_t val) mem_logical_addr = addr; if (addr & 3) { - if (!cpu_cyrix_alignment || (addr & 7) > 4) - cycles -= timing_misaligned; - if ((addr & 0xfff) > 0xffc) { - if (cr0 >> 31) { - if (cpu_state.abrt || high_page) - return; - } + if (!cpu_cyrix_alignment || (addr & 7) > 4) + cycles -= timing_misaligned; + if ((addr & 0xfff) > 0xffc) { + if (cr0 >> 31) { + if (cpu_state.abrt || high_page) + return; + } - writememwl_no_mmut(addr, &(a64[0]), val); - writememwl_no_mmut(addr + 2, &(a64[2]), val >> 16); - return; - } else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { - mmu_perm = writelookupp[addr >> 12]; - *(uint32_t *)(writelookup2[addr >> 12] + addr) = val; - return; - } + writememwl_no_mmut(addr, &(a64[0]), val); + writememwl_no_mmut(addr + 2, &(a64[2]), val >> 16); + return; + } else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { + mmu_perm = writelookupp[addr >> 12]; + *(uint32_t *) (writelookup2[addr >> 12] + addr) = val; + return; + } } if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_l) { - mmu_perm = page_lookupp[addr >> 12]; - page_lookup[addr >> 12]->write_l(addr, val, page_lookup[addr >> 12]); - return; + mmu_perm = page_lookupp[addr >> 12]; + page_lookup[addr >> 12]->write_l(addr, val, page_lookup[addr >> 12]); + return; } if (cr0 >> 31) { - if (cpu_state.abrt || high_page) - return; + if (cpu_state.abrt || high_page) + return; - addr = (uint32_t) (a64[0] & rammask); + addr = (uint32_t) (a64[0] & rammask); } else - addr &= rammask; + addr &= rammask; map = write_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->write_l) { - map->write_l(addr, val, map->p); - return; + map->write_l(addr, val, map->p); + return; } if (map && map->write_w) { - map->write_w(addr, val, map->p); - map->write_w(addr + 2, val >> 16, map->p); - return; + map->write_w(addr, val, map->p); + map->write_w(addr + 2, val >> 16, map->p); + return; } if (map && map->write_b) { - map->write_b(addr, val, map->p); - map->write_b(addr + 1, val >> 8, map->p); - map->write_b(addr + 2, val >> 16, map->p); - map->write_b(addr + 3, val >> 24, map->p); - return; + map->write_b(addr, val, map->p); + map->write_b(addr + 1, val >> 8, map->p); + map->write_b(addr + 2, val >> 16, map->p); + map->write_b(addr + 3, val >> 24, map->p); + return; } } - uint64_t readmemql(uint32_t addr) { mem_mapping_t *map; - int i; - uint64_t a = 0x0000000000000000ULL; + int i; + uint64_t a = 0x0000000000000000ULL; for (i = 0; i < 8; i++) - addr64a[i] = (uint64_t) (addr + i); + addr64a[i] = (uint64_t) (addr + i); GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_READ, 8); mem_logical_addr = addr; @@ -1449,67 +1409,65 @@ readmemql(uint32_t addr) high_page = 0; if (addr & 7) { - cycles -= timing_misaligned; - if ((addr & 0xfff) > 0xff8) { - if (cr0 >> 31) { - for (i = 0; i < 8; i++) { - if (i == 0) { - a = mmutranslate_read(addr + i); - addr64a[i] = (uint32_t) a; - } else if (!((addr + i) & 0xfff)) { - a = mmutranslate_read(addr + 7); - addr64a[i] = (uint32_t) a; - if (!cpu_state.abrt) { - a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); - addr64a[i] = (uint32_t) a; - } - } else { - a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); - addr64a[i] = (uint32_t) a; - } + cycles -= timing_misaligned; + if ((addr & 0xfff) > 0xff8) { + if (cr0 >> 31) { + for (i = 0; i < 8; i++) { + if (i == 0) { + a = mmutranslate_read(addr + i); + addr64a[i] = (uint32_t) a; + } else if (!((addr + i) & 0xfff)) { + a = mmutranslate_read(addr + 7); + addr64a[i] = (uint32_t) a; + if (!cpu_state.abrt) { + a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); + addr64a[i] = (uint32_t) a; + } + } else { + a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); + addr64a[i] = (uint32_t) a; + } - if (a > 0xffffffffULL) - return 0xffff; - } - } + if (a > 0xffffffffULL) + return 0xffff; + } + } - /* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass - their result as a parameter to be used if needed. */ - return readmemll_no_mmut(addr, addr64a) | - (((uint64_t) readmemll_no_mmut(addr + 4, &(addr64a[4]))) << 32); - } else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { - mmu_perm = readlookupp[addr >> 12]; - return *(uint64_t *)(readlookup2[addr >> 12] + addr); - } + /* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass + their result as a parameter to be used if needed. */ + return readmemll_no_mmut(addr, addr64a) | (((uint64_t) readmemll_no_mmut(addr + 4, &(addr64a[4]))) << 32); + } else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { + mmu_perm = readlookupp[addr >> 12]; + return *(uint64_t *) (readlookup2[addr >> 12] + addr); + } } if (cr0 >> 31) { - a = mmutranslate_read(addr); + a = mmutranslate_read(addr); addr64a[0] = (uint32_t) a; - if (a > 0xffffffffULL) - return 0xffffffffffffffffULL; + if (a > 0xffffffffULL) + return 0xffffffffffffffffULL; } addr = addr64a[0] & rammask; map = read_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->read_l) - return map->read_l(addr, map->p) | ((uint64_t)map->read_l(addr + 4, map->p) << 32); + return map->read_l(addr, map->p) | ((uint64_t) map->read_l(addr + 4, map->p) << 32); return readmemll(addr) | ((uint64_t) readmemll(addr + 4) << 32); } - void writememql(uint32_t addr, uint64_t val) { mem_mapping_t *map; - int i; - uint64_t a = 0x0000000000000000ULL; + int i; + uint64_t a = 0x0000000000000000ULL; for (i = 0; i < 8; i++) - addr64a[i] = (uint64_t) (addr + i); + addr64a[i] = (uint64_t) (addr + i); GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_WRITE, 8); mem_logical_addr = addr; @@ -1517,57 +1475,57 @@ writememql(uint32_t addr, uint64_t val) high_page = 0; if (addr & 7) { - cycles -= timing_misaligned; - if ((addr & 0xfff) > 0xff8) { - if (cr0 >> 31) { - for (i = 0; i < 8; i++) { - /* Do not translate a page that has a valid lookup, as that is by definition valid - and the whole purpose of the lookup is to avoid repeat identical translations. */ - if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) { - if (i == 0) { - a = mmutranslate_write(addr + i); - addr64a[i] = (uint32_t) a; - } else if (!((addr + i) & 0xfff)) { - a = mmutranslate_write(addr + 7); - addr64a[i] = (uint32_t) a; - if (!cpu_state.abrt) { - a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); - addr64a[i] = (uint32_t) a; - } - } else { - a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); - addr64a[i] = (uint32_t) a; - } + cycles -= timing_misaligned; + if ((addr & 0xfff) > 0xff8) { + if (cr0 >> 31) { + for (i = 0; i < 8; i++) { + /* Do not translate a page that has a valid lookup, as that is by definition valid + and the whole purpose of the lookup is to avoid repeat identical translations. */ + if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) { + if (i == 0) { + a = mmutranslate_write(addr + i); + addr64a[i] = (uint32_t) a; + } else if (!((addr + i) & 0xfff)) { + a = mmutranslate_write(addr + 7); + addr64a[i] = (uint32_t) a; + if (!cpu_state.abrt) { + a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); + addr64a[i] = (uint32_t) a; + } + } else { + a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff)); + addr64a[i] = (uint32_t) a; + } - if (addr64a[i] > 0xffffffffULL) - return; - } - } - } + if (addr64a[i] > 0xffffffffULL) + return; + } + } + } - /* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass - their result as a parameter to be used if needed. */ - writememll_no_mmut(addr, addr64a, val); - writememll_no_mmut(addr + 4, &(addr64a[4]), val >> 32); - return; - } else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { - mmu_perm = writelookupp[addr >> 12]; - *(uint64_t *)(writelookup2[addr >> 12] + addr) = val; - return; - } + /* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass + their result as a parameter to be used if needed. */ + writememll_no_mmut(addr, addr64a, val); + writememll_no_mmut(addr + 4, &(addr64a[4]), val >> 32); + return; + } else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) { + mmu_perm = writelookupp[addr >> 12]; + *(uint64_t *) (writelookup2[addr >> 12] + addr) = val; + return; + } } if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_l) { - mmu_perm = page_lookupp[addr >> 12]; - page_lookup[addr >> 12]->write_l(addr, val, page_lookup[addr >> 12]); - page_lookup[addr >> 12]->write_l(addr + 4, val >> 32, page_lookup[addr >> 12]); - return; + mmu_perm = page_lookupp[addr >> 12]; + page_lookup[addr >> 12]->write_l(addr, val, page_lookup[addr >> 12]); + page_lookup[addr >> 12]->write_l(addr + 4, val >> 32, page_lookup[addr >> 12]); + return; } if (cr0 >> 31) { - addr64a[0] = mmutranslate_write(addr); - if (addr64a[0] > 0xffffffffULL) - return; + addr64a[0] = mmutranslate_write(addr); + if (addr64a[0] > 0xffffffffULL) + return; } addr = addr64a[0] & rammask; @@ -1575,164 +1533,158 @@ writememql(uint32_t addr, uint64_t val) map = write_mapping[addr >> MEM_GRANULARITY_BITS]; if (map && map->write_l) { - map->write_l(addr, val, map->p); - map->write_l(addr + 4, val >> 32, map->p); - return; + map->write_l(addr, val, map->p); + map->write_l(addr + 4, val >> 32, map->p); + return; } if (map && map->write_w) { - map->write_w(addr, val, map->p); - map->write_w(addr + 2, val >> 16, map->p); - map->write_w(addr + 4, val >> 32, map->p); - map->write_w(addr + 6, val >> 48, map->p); - return; + map->write_w(addr, val, map->p); + map->write_w(addr + 2, val >> 16, map->p); + map->write_w(addr + 4, val >> 32, map->p); + map->write_w(addr + 6, val >> 48, map->p); + return; } if (map && map->write_b) { - map->write_b(addr, val, map->p); - map->write_b(addr + 1, val >> 8, map->p); - map->write_b(addr + 2, val >> 16, map->p); - map->write_b(addr + 3, val >> 24, map->p); - map->write_b(addr + 4, val >> 32, map->p); - map->write_b(addr + 5, val >> 40, map->p); - map->write_b(addr + 6, val >> 48, map->p); - map->write_b(addr + 7, val >> 56, map->p); - return; + map->write_b(addr, val, map->p); + map->write_b(addr + 1, val >> 8, map->p); + map->write_b(addr + 2, val >> 16, map->p); + map->write_b(addr + 3, val >> 24, map->p); + map->write_b(addr + 4, val >> 32, map->p); + map->write_b(addr + 5, val >> 40, map->p); + map->write_b(addr + 6, val >> 48, map->p); + map->write_b(addr + 7, val >> 56, map->p); + return; } } - void do_mmutranslate(uint32_t addr, uint32_t *a64, int num, int write) { - int i, cond = 1; + int i, cond = 1; uint32_t last_addr = addr + (num - 1); - uint64_t a = 0x0000000000000000ULL; + uint64_t a = 0x0000000000000000ULL; for (i = 0; i < num; i++) - a64[i] = (uint64_t) addr; + a64[i] = (uint64_t) addr; for (i = 0; i < num; i++) { - if (cr0 >> 31) { - if (write && ((i == 0) || !(addr & 0xfff))) - cond = (!page_lookup[addr >> 12] || !page_lookup[addr >> 12]->write_b); + if (cr0 >> 31) { + if (write && ((i == 0) || !(addr & 0xfff))) + cond = (!page_lookup[addr >> 12] || !page_lookup[addr >> 12]->write_b); - if (cond) { - /* If we have encountered at least one page fault, mark all subsequent addresses as - having page faulted, prevents false negatives in readmem*l_no_mmut. */ - if ((i > 0) && cpu_state.abrt && !high_page) - a64[i] = a64[i - 1]; - /* If we are on the same page, there is no need to translate again, as we can just - reuse the previous result. */ - else if (i == 0) { - a = mmutranslatereal(addr, write); - a64[i] = (uint32_t) a; + if (cond) { + /* If we have encountered at least one page fault, mark all subsequent addresses as + having page faulted, prevents false negatives in readmem*l_no_mmut. */ + if ((i > 0) && cpu_state.abrt && !high_page) + a64[i] = a64[i - 1]; + /* If we are on the same page, there is no need to translate again, as we can just + reuse the previous result. */ + else if (i == 0) { + a = mmutranslatereal(addr, write); + a64[i] = (uint32_t) a; - high_page = high_page || (!cpu_state.abrt && (a > 0xffffffffULL)); - } else if (!(addr & 0xfff)) { - a = mmutranslatereal(last_addr, write); - a64[i] = (uint32_t) a; + high_page = high_page || (!cpu_state.abrt && (a > 0xffffffffULL)); + } else if (!(addr & 0xfff)) { + a = mmutranslatereal(last_addr, write); + a64[i] = (uint32_t) a; - high_page = high_page || (!cpu_state.abrt && (a64[i] > 0xffffffffULL)); + high_page = high_page || (!cpu_state.abrt && (a64[i] > 0xffffffffULL)); - if (!cpu_state.abrt) { - a = (a & 0xfffffffffffff000ULL) | ((uint64_t) (addr & 0xfff)); - a64[i] = (uint32_t) a; - } - } else { - a = (a & 0xfffffffffffff000ULL) | ((uint64_t) (addr & 0xfff)); - a64[i] = (uint32_t) a; - } - } else - mmu_perm = page_lookupp[addr >> 12]; - } + if (!cpu_state.abrt) { + a = (a & 0xfffffffffffff000ULL) | ((uint64_t) (addr & 0xfff)); + a64[i] = (uint32_t) a; + } + } else { + a = (a & 0xfffffffffffff000ULL) | ((uint64_t) (addr & 0xfff)); + a64[i] = (uint32_t) a; + } + } else + mmu_perm = page_lookupp[addr >> 12]; + } - addr++; + addr++; } } - uint8_t mem_readb_phys(uint32_t addr) { mem_mapping_t *map = read_mapping_bus[addr >> MEM_GRANULARITY_BITS]; - uint8_t ret = 0xff; + uint8_t ret = 0xff; mem_logical_addr = 0xffffffff; if (map) { - if (map->exec) - ret = map->exec[(addr - map->base) & map->mask]; - else if (map->read_b) - ret = map->read_b(addr, map->p); + if (map->exec) + ret = map->exec[(addr - map->base) & map->mask]; + else if (map->read_b) + ret = map->read_b(addr, map->p); } return ret; } - uint16_t mem_readw_phys(uint32_t addr) { mem_mapping_t *map = read_mapping_bus[addr >> MEM_GRANULARITY_BITS]; - uint16_t ret, *p; + uint16_t ret, *p; mem_logical_addr = 0xffffffff; if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_HBOUND) && (map && map->exec)) { - p = (uint16_t *) &(map->exec[(addr - map->base) & map->mask]); - ret = *p; + p = (uint16_t *) &(map->exec[(addr - map->base) & map->mask]); + ret = *p; } else if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_HBOUND) && (map && map->read_w)) - ret = map->read_w(addr, map->p); + ret = map->read_w(addr, map->p); else { - ret = mem_readb_phys(addr + 1) << 8; - ret |= mem_readb_phys(addr); + ret = mem_readb_phys(addr + 1) << 8; + ret |= mem_readb_phys(addr); } return ret; } - uint32_t mem_readl_phys(uint32_t addr) { mem_mapping_t *map = read_mapping_bus[addr >> MEM_GRANULARITY_BITS]; - uint32_t ret, *p; + uint32_t ret, *p; mem_logical_addr = 0xffffffff; if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_QBOUND) && (map && map->exec)) { - p = (uint32_t *) &(map->exec[(addr - map->base) & map->mask]); - ret = *p; + p = (uint32_t *) &(map->exec[(addr - map->base) & map->mask]); + ret = *p; } else if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_QBOUND) && (map && map->read_l)) - ret = map->read_l(addr, map->p); + ret = map->read_l(addr, map->p); else { - ret = mem_readw_phys(addr + 2) << 16; - ret |= mem_readw_phys(addr); + ret = mem_readw_phys(addr + 2) << 16; + ret |= mem_readw_phys(addr); } return ret; } - void mem_read_phys(void *dest, uint32_t addr, int transfer_size) { - uint8_t *pb; + uint8_t *pb; uint16_t *pw; uint32_t *pl; if (transfer_size == 4) { - pl = (uint32_t *) dest; - *pl = mem_readl_phys(addr); + pl = (uint32_t *) dest; + *pl = mem_readl_phys(addr); } else if (transfer_size == 2) { - pw = (uint16_t *) dest; - *pw = mem_readw_phys(addr); + pw = (uint16_t *) dest; + *pw = mem_readw_phys(addr); } else if (transfer_size == 1) { - pb = (uint8_t *) dest; - *pb = mem_readb_phys(addr); + pb = (uint8_t *) dest; + *pb = mem_readb_phys(addr); } } - void mem_writeb_phys(uint32_t addr, uint8_t val) { @@ -1741,125 +1693,118 @@ mem_writeb_phys(uint32_t addr, uint8_t val) mem_logical_addr = 0xffffffff; if (map) { - if (map->exec) - map->exec[(addr - map->base) & map->mask] = val; - else if (map->write_b) - map->write_b(addr, val, map->p); - } + if (map->exec) + map->exec[(addr - map->base) & map->mask] = val; + else if (map->write_b) + map->write_b(addr, val, map->p); + } } - void mem_writew_phys(uint32_t addr, uint16_t val) { mem_mapping_t *map = write_mapping_bus[addr >> MEM_GRANULARITY_BITS]; - uint16_t *p; + uint16_t *p; mem_logical_addr = 0xffffffff; if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_HBOUND) && (map && map->exec)) { - p = (uint16_t *) &(map->exec[(addr - map->base) & map->mask]); - *p = val; + p = (uint16_t *) &(map->exec[(addr - map->base) & map->mask]); + *p = val; } else if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_HBOUND) && (map && map->write_w)) - map->write_w(addr, val, map->p); + map->write_w(addr, val, map->p); else { - mem_writeb_phys(addr, val & 0xff); - mem_writeb_phys(addr + 1, (val >> 8) & 0xff); + mem_writeb_phys(addr, val & 0xff); + mem_writeb_phys(addr + 1, (val >> 8) & 0xff); } } - void mem_writel_phys(uint32_t addr, uint32_t val) { mem_mapping_t *map = write_mapping_bus[addr >> MEM_GRANULARITY_BITS]; - uint32_t *p; + uint32_t *p; mem_logical_addr = 0xffffffff; if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_QBOUND) && (map && map->exec)) { - p = (uint32_t *) &(map->exec[(addr - map->base) & map->mask]); - *p = val; + p = (uint32_t *) &(map->exec[(addr - map->base) & map->mask]); + *p = val; } else if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_QBOUND) && (map && map->write_l)) - map->write_l(addr, val, map->p); + map->write_l(addr, val, map->p); else { - mem_writew_phys(addr, val & 0xffff); - mem_writew_phys(addr + 2, (val >> 16) & 0xffff); + mem_writew_phys(addr, val & 0xffff); + mem_writew_phys(addr + 2, (val >> 16) & 0xffff); } } - void mem_write_phys(void *src, uint32_t addr, int transfer_size) { - uint8_t *pb; + uint8_t *pb; uint16_t *pw; uint32_t *pl; if (transfer_size == 4) { - pl = (uint32_t *) src; - mem_writel_phys(addr, *pl); + pl = (uint32_t *) src; + mem_writel_phys(addr, *pl); } else if (transfer_size == 2) { - pw = (uint16_t *) src; - mem_writew_phys(addr, *pw); + pw = (uint16_t *) src; + mem_writew_phys(addr, *pw); } else if (transfer_size == 1) { - pb = (uint8_t *) src; - mem_writeb_phys(addr, *pb); + pb = (uint8_t *) src; + mem_writeb_phys(addr, *pb); } } - uint8_t mem_read_ram(uint32_t addr, void *priv) { #ifdef ENABLE_MEM_LOG if ((addr >= 0xa0000) && (addr <= 0xbffff)) - mem_log("Read B %02X from %08X\n", ram[addr], addr); + mem_log("Read B %02X from %08X\n", ram[addr], addr); #endif if (is286) - addreadlookup(mem_logical_addr, addr); + addreadlookup(mem_logical_addr, addr); return ram[addr]; } - uint16_t mem_read_ramw(uint32_t addr, void *priv) { #ifdef ENABLE_MEM_LOG if ((addr >= 0xa0000) && (addr <= 0xbffff)) - mem_log("Read W %04X from %08X\n", *(uint16_t *)&ram[addr], addr); + mem_log("Read W %04X from %08X\n", *(uint16_t *) &ram[addr], addr); #endif if (is286) - addreadlookup(mem_logical_addr, addr); + addreadlookup(mem_logical_addr, addr); - return *(uint16_t *)&ram[addr]; + return *(uint16_t *) &ram[addr]; } - uint32_t mem_read_raml(uint32_t addr, void *priv) { #ifdef ENABLE_MEM_LOG if ((addr >= 0xa0000) && (addr <= 0xbffff)) - mem_log("Read L %08X from %08X\n", *(uint32_t *)&ram[addr], addr); + mem_log("Read L %08X from %08X\n", *(uint32_t *) &ram[addr], addr); #endif if (is286) - addreadlookup(mem_logical_addr, addr); + addreadlookup(mem_logical_addr, addr); - return *(uint32_t *)&ram[addr]; + return *(uint32_t *) &ram[addr]; } - uint8_t mem_read_ram_2gb(uint32_t addr, void *priv) { #ifdef ENABLE_MEM_LOG if ((addr >= 0xa0000) && (addr <= 0xbffff)) - mem_log("Read B %02X from %08X\n", ram[addr], addr); + mem_log("Read B %02X from %08X\n", ram[addr], addr); #endif addreadlookup(mem_logical_addr, addr); @@ -1867,161 +1812,153 @@ mem_read_ram_2gb(uint32_t addr, void *priv) return ram2[addr - (1 << 30)]; } - uint16_t mem_read_ram_2gbw(uint32_t addr, void *priv) { #ifdef ENABLE_MEM_LOG if ((addr >= 0xa0000) && (addr <= 0xbffff)) - mem_log("Read W %04X from %08X\n", *(uint16_t *)&ram[addr], addr); + mem_log("Read W %04X from %08X\n", *(uint16_t *) &ram[addr], addr); #endif addreadlookup(mem_logical_addr, addr); - return *(uint16_t *)&ram2[addr - (1 << 30)]; + return *(uint16_t *) &ram2[addr - (1 << 30)]; } - uint32_t mem_read_ram_2gbl(uint32_t addr, void *priv) { #ifdef ENABLE_MEM_LOG if ((addr >= 0xa0000) && (addr <= 0xbffff)) - mem_log("Read L %08X from %08X\n", *(uint32_t *)&ram[addr], addr); + mem_log("Read L %08X from %08X\n", *(uint32_t *) &ram[addr], addr); #endif addreadlookup(mem_logical_addr, addr); - return *(uint32_t *)&ram2[addr - (1 << 30)]; + return *(uint32_t *) &ram2[addr - (1 << 30)]; } - #ifdef USE_NEW_DYNAREC static inline int page_index(page_t *p) { - return ((uintptr_t)p - (uintptr_t)pages) / sizeof(page_t); + return ((uintptr_t) p - (uintptr_t) pages) / sizeof(page_t); } - void page_add_to_evict_list(page_t *p) { pages[purgable_page_list_head].evict_prev = page_index(p); - p->evict_next = purgable_page_list_head; - p->evict_prev = 0; - purgable_page_list_head = pages[purgable_page_list_head].evict_prev; + p->evict_next = purgable_page_list_head; + p->evict_prev = 0; + purgable_page_list_head = pages[purgable_page_list_head].evict_prev; purgeable_page_count++; } - void page_remove_from_evict_list(page_t *p) { if (!page_in_evict_list(p)) - fatal("page_remove_from_evict_list: not in evict list!\n"); + fatal("page_remove_from_evict_list: not in evict list!\n"); if (p->evict_prev) - pages[p->evict_prev].evict_next = p->evict_next; + pages[p->evict_prev].evict_next = p->evict_next; else - purgable_page_list_head = p->evict_next; + purgable_page_list_head = p->evict_next; if (p->evict_next) - pages[p->evict_next].evict_prev = p->evict_prev; + pages[p->evict_next].evict_prev = p->evict_prev; p->evict_prev = EVICT_NOT_IN_LIST; - purgeable_page_count--; + purgeable_page_count--; } - void mem_write_ramb_page(uint32_t addr, uint8_t val, page_t *p) { if (p == NULL) - return; + return; -#ifdef USE_DYNAREC +# ifdef USE_DYNAREC if ((p->mem == NULL) || (p->mem == page_ff) || (val != p->mem[addr & 0xfff]) || codegen_in_recompile) { -#else +# else if ((p->mem == NULL) || (p->mem == page_ff) || (val != p->mem[addr & 0xfff])) { -#endif - uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); - int byte_offset = (addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK; - uint64_t byte_mask = (uint64_t)1 << (addr & PAGE_BYTE_MASK_MASK); +# endif + uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); + int byte_offset = (addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK; + uint64_t byte_mask = (uint64_t) 1 << (addr & PAGE_BYTE_MASK_MASK); - p->mem[addr & 0xfff] = val; - p->dirty_mask |= mask; - if ((p->code_present_mask & mask) && !page_in_evict_list(p)) - page_add_to_evict_list(p); - p->byte_dirty_mask[byte_offset] |= byte_mask; - if ((p->byte_code_present_mask[byte_offset] & byte_mask) && !page_in_evict_list(p)) - page_add_to_evict_list(p); + p->mem[addr & 0xfff] = val; + p->dirty_mask |= mask; + if ((p->code_present_mask & mask) && !page_in_evict_list(p)) + page_add_to_evict_list(p); + p->byte_dirty_mask[byte_offset] |= byte_mask; + if ((p->byte_code_present_mask[byte_offset] & byte_mask) && !page_in_evict_list(p)) + page_add_to_evict_list(p); } } - void mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *p) { if (p == NULL) - return; + return; -#ifdef USE_DYNAREC - if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint16_t *)&p->mem[addr & 0xfff]) || codegen_in_recompile) { -#else - if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint16_t *)&p->mem[addr & 0xfff])) { -#endif - uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); - int byte_offset = (addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK; - uint64_t byte_mask = (uint64_t)1 << (addr & PAGE_BYTE_MASK_MASK); +# ifdef USE_DYNAREC + if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint16_t *) &p->mem[addr & 0xfff]) || codegen_in_recompile) { +# else + if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint16_t *) &p->mem[addr & 0xfff])) { +# endif + uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); + int byte_offset = (addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK; + uint64_t byte_mask = (uint64_t) 1 << (addr & PAGE_BYTE_MASK_MASK); - if ((addr & 0xf) == 0xf) - mask |= (mask << 1); - *(uint16_t *)&p->mem[addr & 0xfff] = val; - p->dirty_mask |= mask; - if ((p->code_present_mask & mask) && !page_in_evict_list(p)) - page_add_to_evict_list(p); - if ((addr & PAGE_BYTE_MASK_MASK) == PAGE_BYTE_MASK_MASK) { - p->byte_dirty_mask[byte_offset+1] |= 1; - if ((p->byte_code_present_mask[byte_offset+1] & 1) && !page_in_evict_list(p)) - page_add_to_evict_list(p); - } else - byte_mask |= (byte_mask << 1); + if ((addr & 0xf) == 0xf) + mask |= (mask << 1); + *(uint16_t *) &p->mem[addr & 0xfff] = val; + p->dirty_mask |= mask; + if ((p->code_present_mask & mask) && !page_in_evict_list(p)) + page_add_to_evict_list(p); + if ((addr & PAGE_BYTE_MASK_MASK) == PAGE_BYTE_MASK_MASK) { + p->byte_dirty_mask[byte_offset + 1] |= 1; + if ((p->byte_code_present_mask[byte_offset + 1] & 1) && !page_in_evict_list(p)) + page_add_to_evict_list(p); + } else + byte_mask |= (byte_mask << 1); - p->byte_dirty_mask[byte_offset] |= byte_mask; + p->byte_dirty_mask[byte_offset] |= byte_mask; - if ((p->byte_code_present_mask[byte_offset] & byte_mask) && !page_in_evict_list(p)) - page_add_to_evict_list(p); + if ((p->byte_code_present_mask[byte_offset] & byte_mask) && !page_in_evict_list(p)) + page_add_to_evict_list(p); } } - void mem_write_raml_page(uint32_t addr, uint32_t val, page_t *p) { if (p == NULL) - return; + return; -#ifdef USE_DYNAREC - if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint32_t *)&p->mem[addr & 0xfff]) || codegen_in_recompile) { -#else - if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint32_t *)&p->mem[addr & 0xfff])) { -#endif - uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); - int byte_offset = (addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK; - uint64_t byte_mask = (uint64_t)0xf << (addr & PAGE_BYTE_MASK_MASK); +# ifdef USE_DYNAREC + if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint32_t *) &p->mem[addr & 0xfff]) || codegen_in_recompile) { +# else + if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint32_t *) &p->mem[addr & 0xfff])) { +# endif + uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); + int byte_offset = (addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK; + uint64_t byte_mask = (uint64_t) 0xf << (addr & PAGE_BYTE_MASK_MASK); - if ((addr & 0xf) >= 0xd) - mask |= (mask << 1); - *(uint32_t *)&p->mem[addr & 0xfff] = val; - p->dirty_mask |= mask; - p->byte_dirty_mask[byte_offset] |= byte_mask; - if (!page_in_evict_list(p) && ((p->code_present_mask & mask) || (p->byte_code_present_mask[byte_offset] & byte_mask))) - page_add_to_evict_list(p); - if ((addr & PAGE_BYTE_MASK_MASK) > (PAGE_BYTE_MASK_MASK-3)) { - uint32_t byte_mask_2 = 0xf >> (4 - (addr & 3)); + if ((addr & 0xf) >= 0xd) + mask |= (mask << 1); + *(uint32_t *) &p->mem[addr & 0xfff] = val; + p->dirty_mask |= mask; + p->byte_dirty_mask[byte_offset] |= byte_mask; + if (!page_in_evict_list(p) && ((p->code_present_mask & mask) || (p->byte_code_present_mask[byte_offset] & byte_mask))) + page_add_to_evict_list(p); + if ((addr & PAGE_BYTE_MASK_MASK) > (PAGE_BYTE_MASK_MASK - 3)) { + uint32_t byte_mask_2 = 0xf >> (4 - (addr & 3)); - p->byte_dirty_mask[byte_offset+1] |= byte_mask_2; - if ((p->byte_code_present_mask[byte_offset+1] & byte_mask_2) && !page_in_evict_list(p)) - page_add_to_evict_list(p); - } + p->byte_dirty_mask[byte_offset + 1] |= byte_mask_2; + if ((p->byte_code_present_mask[byte_offset + 1] & byte_mask_2) && !page_in_evict_list(p)) + page_add_to_evict_list(p); + } } } #else @@ -2029,175 +1966,163 @@ void mem_write_ramb_page(uint32_t addr, uint8_t val, page_t *p) { if (p == NULL) - return; + return; -#ifdef USE_DYNAREC +# ifdef USE_DYNAREC if ((p->mem == NULL) || (p->mem == page_ff) || (val != p->mem[addr & 0xfff]) || codegen_in_recompile) { -#else +# else if ((p->mem == NULL) || (p->mem == page_ff) || (val != p->mem[addr & 0xfff])) { -#endif - uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); - p->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask; - p->mem[addr & 0xfff] = val; +# endif + uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); + p->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask; + p->mem[addr & 0xfff] = val; } } - void mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *p) { if (p == NULL) - return; + return; -#ifdef USE_DYNAREC - if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint16_t *)&p->mem[addr & 0xfff]) || codegen_in_recompile) { -#else - if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint16_t *)&p->mem[addr & 0xfff])) { -#endif - uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); - if ((addr & 0xf) == 0xf) - mask |= (mask << 1); - p->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask; - *(uint16_t *)&p->mem[addr & 0xfff] = val; +# ifdef USE_DYNAREC + if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint16_t *) &p->mem[addr & 0xfff]) || codegen_in_recompile) { +# else + if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint16_t *) &p->mem[addr & 0xfff])) { +# endif + uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); + if ((addr & 0xf) == 0xf) + mask |= (mask << 1); + p->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask; + *(uint16_t *) &p->mem[addr & 0xfff] = val; } } - void mem_write_raml_page(uint32_t addr, uint32_t val, page_t *p) { if (p == NULL) - return; + return; -#ifdef USE_DYNAREC - if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint32_t *)&p->mem[addr & 0xfff]) || codegen_in_recompile) { -#else - if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint32_t *)&p->mem[addr & 0xfff])) { -#endif - uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); - if ((addr & 0xf) >= 0xd) - mask |= (mask << 1); - p->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask; - *(uint32_t *)&p->mem[addr & 0xfff] = val; +# ifdef USE_DYNAREC + if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint32_t *) &p->mem[addr & 0xfff]) || codegen_in_recompile) { +# else + if ((p->mem == NULL) || (p->mem == page_ff) || (val != *(uint32_t *) &p->mem[addr & 0xfff])) { +# endif + uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK); + if ((addr & 0xf) >= 0xd) + mask |= (mask << 1); + p->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask; + *(uint32_t *) &p->mem[addr & 0xfff] = val; } } #endif - void mem_write_ram(uint32_t addr, uint8_t val, void *priv) { #ifdef ENABLE_MEM_LOG if ((addr >= 0xa0000) && (addr <= 0xbffff)) - mem_log("Write B %02X to %08X\n", val, addr); + mem_log("Write B %02X to %08X\n", val, addr); #endif if (is286) { - addwritelookup(mem_logical_addr, addr); - mem_write_ramb_page(addr, val, &pages[addr >> 12]); + addwritelookup(mem_logical_addr, addr); + mem_write_ramb_page(addr, val, &pages[addr >> 12]); } else - ram[addr] = val; + ram[addr] = val; } - void mem_write_ramw(uint32_t addr, uint16_t val, void *priv) { #ifdef ENABLE_MEM_LOG if ((addr >= 0xa0000) && (addr <= 0xbffff)) - mem_log("Write W %04X to %08X\n", val, addr); + mem_log("Write W %04X to %08X\n", val, addr); #endif if (is286) { - addwritelookup(mem_logical_addr, addr); - mem_write_ramw_page(addr, val, &pages[addr >> 12]); + addwritelookup(mem_logical_addr, addr); + mem_write_ramw_page(addr, val, &pages[addr >> 12]); } else - *(uint16_t *)&ram[addr] = val; + *(uint16_t *) &ram[addr] = val; } - void mem_write_raml(uint32_t addr, uint32_t val, void *priv) { #ifdef ENABLE_MEM_LOG if ((addr >= 0xa0000) && (addr <= 0xbffff)) - mem_log("Write L %08X to %08X\n", val, addr); + mem_log("Write L %08X to %08X\n", val, addr); #endif if (is286) { - addwritelookup(mem_logical_addr, addr); - mem_write_raml_page(addr, val, &pages[addr >> 12]); + addwritelookup(mem_logical_addr, addr); + mem_write_raml_page(addr, val, &pages[addr >> 12]); } else - *(uint32_t *)&ram[addr] = val; + *(uint32_t *) &ram[addr] = val; } - static uint8_t mem_read_remapped(uint32_t addr, void *priv) { addr = 0xA0000 + (addr - remap_start_addr); if (is286) - addreadlookup(mem_logical_addr, addr); + addreadlookup(mem_logical_addr, addr); return ram[addr]; } - static uint16_t mem_read_remappedw(uint32_t addr, void *priv) { addr = 0xA0000 + (addr - remap_start_addr); if (is286) - addreadlookup(mem_logical_addr, addr); - return *(uint16_t *)&ram[addr]; + addreadlookup(mem_logical_addr, addr); + return *(uint16_t *) &ram[addr]; } - static uint32_t mem_read_remappedl(uint32_t addr, void *priv) { addr = 0xA0000 + (addr - remap_start_addr); if (is286) - addreadlookup(mem_logical_addr, addr); - return *(uint32_t *)&ram[addr]; + addreadlookup(mem_logical_addr, addr); + return *(uint32_t *) &ram[addr]; } - static void mem_write_remapped(uint32_t addr, uint8_t val, void *priv) { uint32_t oldaddr = addr; - addr = 0xA0000 + (addr - remap_start_addr); + addr = 0xA0000 + (addr - remap_start_addr); if (is286) { - addwritelookup(mem_logical_addr, addr); - mem_write_ramb_page(addr, val, &pages[oldaddr >> 12]); + addwritelookup(mem_logical_addr, addr); + mem_write_ramb_page(addr, val, &pages[oldaddr >> 12]); } else - ram[addr] = val; + ram[addr] = val; } - static void mem_write_remappedw(uint32_t addr, uint16_t val, void *priv) { uint32_t oldaddr = addr; - addr = 0xA0000 + (addr - remap_start_addr); + addr = 0xA0000 + (addr - remap_start_addr); if (is286) { - addwritelookup(mem_logical_addr, addr); - mem_write_ramw_page(addr, val, &pages[oldaddr >> 12]); + addwritelookup(mem_logical_addr, addr); + mem_write_ramw_page(addr, val, &pages[oldaddr >> 12]); } else - *(uint16_t *)&ram[addr] = val; + *(uint16_t *) &ram[addr] = val; } - static void mem_write_remappedl(uint32_t addr, uint32_t val, void *priv) { uint32_t oldaddr = addr; - addr = 0xA0000 + (addr - remap_start_addr); + addr = 0xA0000 + (addr - remap_start_addr); if (is286) { - addwritelookup(mem_logical_addr, addr); - mem_write_raml_page(addr, val, &pages[oldaddr >> 12]); + addwritelookup(mem_logical_addr, addr); + mem_write_raml_page(addr, val, &pages[oldaddr >> 12]); } else - *(uint32_t *)&ram[addr] = val; + *(uint32_t *) &ram[addr] = val; } - void mem_invalidate_range(uint32_t start_addr, uint32_t end_addr) { @@ -2208,19 +2133,19 @@ mem_invalidate_range(uint32_t start_addr, uint32_t end_addr) end_addr = (end_addr + PAGE_MASK_MASK) & ~PAGE_MASK_MASK; for (; start_addr <= end_addr; start_addr += 0x1000) { - if ((start_addr >> 12) >= pages_sz) - continue; + if ((start_addr >> 12) >= pages_sz) + continue; - p = &pages[start_addr >> 12]; - if (p) { - p->dirty_mask = 0xffffffffffffffffULL; + p = &pages[start_addr >> 12]; + if (p) { + p->dirty_mask = 0xffffffffffffffffULL; - if (p->byte_dirty_mask) - memset(p->byte_dirty_mask, 0xff, 64 * sizeof(uint64_t)); + if (p->byte_dirty_mask) + memset(p->byte_dirty_mask, 0xff, 64 * sizeof(uint64_t)); - if (!page_in_evict_list(p)) - page_add_to_evict_list(p); - } + if (!page_in_evict_list(p)) + page_add_to_evict_list(p); + } } #else uint32_t cur_addr; @@ -2228,130 +2153,120 @@ mem_invalidate_range(uint32_t start_addr, uint32_t end_addr) end_addr = (end_addr + PAGE_MASK_MASK) & ~PAGE_MASK_MASK; for (; start_addr <= end_addr; start_addr += 0x1000) { - /* Do nothing if the pages array is empty or DMA reads/writes to/from PCI device memory addresses - may crash the emulator. */ - cur_addr = (start_addr >> 12); - if (cur_addr < pages_sz) - memset(pages[cur_addr].dirty_mask, 0xff, sizeof(pages[cur_addr].dirty_mask)); + /* Do nothing if the pages array is empty or DMA reads/writes to/from PCI device memory addresses + may crash the emulator. */ + cur_addr = (start_addr >> 12); + if (cur_addr < pages_sz) + memset(pages[cur_addr].dirty_mask, 0xff, sizeof(pages[cur_addr].dirty_mask)); } #endif } - static __inline int mem_mapping_access_allowed(uint32_t flags, uint16_t access) { int ret = 0; if (!(access & ACCESS_DISABLED)) { - if (access & ACCESS_CACHE) - ret = (flags & MEM_MAPPING_CACHE); - else if (access & ACCESS_SMRAM) - ret = (flags & MEM_MAPPING_SMRAM); - else if (!(access & ACCESS_INTERNAL)) { - if (flags & MEM_MAPPING_IS_ROM) { - if (access & ACCESS_ROMCS) - ret = (flags & MEM_MAPPING_ROMCS); - else - ret = !(flags & MEM_MAPPING_ROMCS); - } else - ret = 1; + if (access & ACCESS_CACHE) + ret = (flags & MEM_MAPPING_CACHE); + else if (access & ACCESS_SMRAM) + ret = (flags & MEM_MAPPING_SMRAM); + else if (!(access & ACCESS_INTERNAL)) { + if (flags & MEM_MAPPING_IS_ROM) { + if (access & ACCESS_ROMCS) + ret = (flags & MEM_MAPPING_ROMCS); + else + ret = !(flags & MEM_MAPPING_ROMCS); + } else + ret = 1; - ret = ret && !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_SMRAM); - } else - ret = !(flags & MEM_MAPPING_EXTERNAL) && !(flags & MEM_MAPPING_SMRAM); + ret = ret && !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_SMRAM); + } else + ret = !(flags & MEM_MAPPING_EXTERNAL) && !(flags & MEM_MAPPING_SMRAM); } else { - /* Still allow SMRAM if access is DISABLED but also has CACHE and/or SMRAM flags set. */ - if (access & ACCESS_CACHE) - ret = (flags & MEM_MAPPING_CACHE); - else if (access & ACCESS_SMRAM) - ret = (flags & MEM_MAPPING_SMRAM); + /* Still allow SMRAM if access is DISABLED but also has CACHE and/or SMRAM flags set. */ + if (access & ACCESS_CACHE) + ret = (flags & MEM_MAPPING_CACHE); + else if (access & ACCESS_SMRAM) + ret = (flags & MEM_MAPPING_SMRAM); } return ret; } - void mem_mapping_recalc(uint64_t base, uint64_t size) { mem_mapping_t *map; - int n; - uint64_t c; + int n; + uint64_t c; if (!size || (base_mapping == NULL)) - return; + return; map = base_mapping; /* Clear out old mappings. */ for (c = base; c < base + size; c += MEM_GRANULARITY_SIZE) { - _mem_exec[c >> MEM_GRANULARITY_BITS] = NULL; - write_mapping[c >> MEM_GRANULARITY_BITS] = NULL; - read_mapping[c >> MEM_GRANULARITY_BITS] = NULL; - write_mapping_bus[c >> MEM_GRANULARITY_BITS] = NULL; - read_mapping_bus[c >> MEM_GRANULARITY_BITS] = NULL; + _mem_exec[c >> MEM_GRANULARITY_BITS] = NULL; + write_mapping[c >> MEM_GRANULARITY_BITS] = NULL; + read_mapping[c >> MEM_GRANULARITY_BITS] = NULL; + write_mapping_bus[c >> MEM_GRANULARITY_BITS] = NULL; + read_mapping_bus[c >> MEM_GRANULARITY_BITS] = NULL; } /* Walk mapping list. */ while (map != NULL) { - /* In range? */ - if (map->enable && (uint64_t)map->base < ((uint64_t)base + (uint64_t)size) && - ((uint64_t)map->base + (uint64_t)map->size) > (uint64_t)base) { - uint64_t start = (map->base < base) ? map->base : base; - uint64_t end = (((uint64_t)map->base + (uint64_t)map->size) < (base + size)) ? - ((uint64_t)map->base + (uint64_t)map->size) : (base + size); - if (start < map->base) - start = map->base; + /* In range? */ + if (map->enable && (uint64_t) map->base < ((uint64_t) base + (uint64_t) size) && ((uint64_t) map->base + (uint64_t) map->size) > (uint64_t) base) { + uint64_t start = (map->base < base) ? map->base : base; + uint64_t end = (((uint64_t) map->base + (uint64_t) map->size) < (base + size)) ? ((uint64_t) map->base + (uint64_t) map->size) : (base + size); + if (start < map->base) + start = map->base; - for (c = start; c < end; c += MEM_GRANULARITY_SIZE) { - /* CPU */ - n = !!in_smm; - if (map->exec && - mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].x)) - _mem_exec[c >> MEM_GRANULARITY_BITS] = map->exec + (c - map->base); - if ((map->write_b || map->write_w || map->write_l) && - mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].w)) - write_mapping[c >> MEM_GRANULARITY_BITS] = map; - if ((map->read_b || map->read_w || map->read_l) && - mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].r)) - read_mapping[c >> MEM_GRANULARITY_BITS] = map; + for (c = start; c < end; c += MEM_GRANULARITY_SIZE) { + /* CPU */ + n = !!in_smm; + if (map->exec && mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].x)) + _mem_exec[c >> MEM_GRANULARITY_BITS] = map->exec + (c - map->base); + if ((map->write_b || map->write_w || map->write_l) && mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].w)) + write_mapping[c >> MEM_GRANULARITY_BITS] = map; + if ((map->read_b || map->read_w || map->read_l) && mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].r)) + read_mapping[c >> MEM_GRANULARITY_BITS] = map; - /* Bus */ - n |= STATE_BUS; - if ((map->write_b || map->write_w || map->write_l) && - mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].w)) - write_mapping_bus[c >> MEM_GRANULARITY_BITS] = map; - if ((map->read_b || map->read_w || map->read_l) && - mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].r)) - read_mapping_bus[c >> MEM_GRANULARITY_BITS] = map; - } - } - map = map->next; + /* Bus */ + n |= STATE_BUS; + if ((map->write_b || map->write_w || map->write_l) && mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].w)) + write_mapping_bus[c >> MEM_GRANULARITY_BITS] = map; + if ((map->read_b || map->read_w || map->read_l) && mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].r)) + read_mapping_bus[c >> MEM_GRANULARITY_BITS] = map; + } + } + map = map->next; } flushmmucache_cr3(); } - void mem_mapping_set(mem_mapping_t *map, - uint32_t base, - uint32_t size, - uint8_t (*read_b)(uint32_t addr, void *p), - uint16_t (*read_w)(uint32_t addr, void *p), - uint32_t (*read_l)(uint32_t addr, void *p), - void (*write_b)(uint32_t addr, uint8_t val, void *p), - void (*write_w)(uint32_t addr, uint16_t val, void *p), - void (*write_l)(uint32_t addr, uint32_t val, void *p), - uint8_t *exec, - uint32_t fl, - void *p) + uint32_t base, + uint32_t size, + uint8_t (*read_b)(uint32_t addr, void *p), + uint16_t (*read_w)(uint32_t addr, void *p), + uint32_t (*read_l)(uint32_t addr, void *p), + void (*write_b)(uint32_t addr, uint8_t val, void *p), + void (*write_w)(uint32_t addr, uint16_t val, void *p), + void (*write_l)(uint32_t addr, uint32_t val, void *p), + uint8_t *exec, + uint32_t fl, + void *p) { if (size != 0x00000000) - map->enable = 1; + map->enable = 1; else - map->enable = 0; + map->enable = 0; map->base = base; map->size = size; map->mask = (map->size ? 0xffffffff : 0x00000000); @@ -2369,72 +2284,69 @@ mem_mapping_set(mem_mapping_t *map, /* If the mapping is disabled, there is no need to recalc anything. */ if (size != 0x00000000) - mem_mapping_recalc(map->base, map->size); + mem_mapping_recalc(map->base, map->size); } - void mem_mapping_add(mem_mapping_t *map, - uint32_t base, - uint32_t size, - uint8_t (*read_b)(uint32_t addr, void *p), - uint16_t (*read_w)(uint32_t addr, void *p), - uint32_t (*read_l)(uint32_t addr, void *p), - void (*write_b)(uint32_t addr, uint8_t val, void *p), - void (*write_w)(uint32_t addr, uint16_t val, void *p), - void (*write_l)(uint32_t addr, uint32_t val, void *p), - uint8_t *exec, - uint32_t fl, - void *p) + uint32_t base, + uint32_t size, + uint8_t (*read_b)(uint32_t addr, void *p), + uint16_t (*read_w)(uint32_t addr, void *p), + uint32_t (*read_l)(uint32_t addr, void *p), + void (*write_b)(uint32_t addr, uint8_t val, void *p), + void (*write_w)(uint32_t addr, uint16_t val, void *p), + void (*write_l)(uint32_t addr, uint32_t val, void *p), + uint8_t *exec, + uint32_t fl, + void *p) { /* Do a sanity check */ if ((base_mapping == NULL) && (last_mapping != NULL)) { - fatal("mem_mapping_add(): NULL base mapping with non-NULL last mapping\n"); - return; + fatal("mem_mapping_add(): NULL base mapping with non-NULL last mapping\n"); + return; } else if ((base_mapping != NULL) && (last_mapping == NULL)) { - fatal("mem_mapping_add(): Non-NULL base mapping with NULL last mapping\n"); - return; + fatal("mem_mapping_add(): Non-NULL base mapping with NULL last mapping\n"); + return; } else if ((base_mapping != NULL) && (base_mapping->prev != NULL)) { - fatal("mem_mapping_add(): Base mapping with a preceding mapping\n"); - return; + fatal("mem_mapping_add(): Base mapping with a preceding mapping\n"); + return; } else if ((last_mapping != NULL) && (last_mapping->next != NULL)) { - fatal("mem_mapping_add(): Last mapping with a following mapping\n"); - return; + fatal("mem_mapping_add(): Last mapping with a following mapping\n"); + return; } /* Add mapping to the beginning of the list if necessary.*/ if (base_mapping == NULL) - base_mapping = map; + base_mapping = map; /* Add mapping to the end of the list.*/ if (last_mapping == NULL) - map->prev = NULL; - else { - map->prev = last_mapping; - last_mapping->next = map; + map->prev = NULL; + else { + map->prev = last_mapping; + last_mapping->next = map; } last_mapping = map; mem_mapping_set(map, base, size, read_b, read_w, read_l, - write_b, write_w, write_l, exec, fl, p); + write_b, write_w, write_l, exec, fl, p); } - void mem_mapping_do_recalc(mem_mapping_t *map) { mem_mapping_recalc(map->base, map->size); } - void mem_mapping_set_handler(mem_mapping_t *map, - uint8_t (*read_b)(uint32_t addr, void *p), - uint16_t (*read_w)(uint32_t addr, void *p), - uint32_t (*read_l)(uint32_t addr, void *p), - void (*write_b)(uint32_t addr, uint8_t val, void *p), - void (*write_w)(uint32_t addr, uint16_t val, void *p), - void (*write_l)(uint32_t addr, uint32_t val, void *p)) + uint8_t (*read_b)(uint32_t addr, void *p), + uint16_t (*read_w)(uint32_t addr, void *p), + uint32_t (*read_l)(uint32_t addr, void *p), + void (*write_b)(uint32_t addr, uint8_t val, void *p), + void (*write_w)(uint32_t addr, uint16_t val, void *p), + void (*write_l)(uint32_t addr, uint32_t val, void *p)) { map->read_b = read_b; map->read_w = read_w; @@ -2446,7 +2358,6 @@ mem_mapping_set_handler(mem_mapping_t *map, mem_mapping_recalc(map->base, map->size); } - void mem_mapping_set_addr(mem_mapping_t *map, uint32_t base, uint32_t size) { @@ -2456,13 +2367,12 @@ mem_mapping_set_addr(mem_mapping_t *map, uint32_t base, uint32_t size) /* Set new mapping. */ map->enable = 1; - map->base = base; - map->size = size; + map->base = base; + map->size = size; mem_mapping_recalc(map->base, map->size); } - void mem_mapping_set_exec(mem_mapping_t *map, uint8_t *exec) { @@ -2471,7 +2381,6 @@ mem_mapping_set_exec(mem_mapping_t *map, uint8_t *exec) mem_mapping_recalc(map->base, map->size); } - void mem_mapping_set_mask(mem_mapping_t *map, uint32_t mask) { @@ -2480,14 +2389,12 @@ mem_mapping_set_mask(mem_mapping_t *map, uint32_t mask) mem_mapping_recalc(map->base, map->size); } - void mem_mapping_set_p(mem_mapping_t *map, void *p) { map->p = p; } - void mem_mapping_disable(mem_mapping_t *map) { @@ -2496,7 +2403,6 @@ mem_mapping_disable(mem_mapping_t *map) mem_mapping_recalc(map->base, map->size); } - void mem_mapping_enable(mem_mapping_t *map) { @@ -2505,75 +2411,71 @@ mem_mapping_enable(mem_mapping_t *map) mem_mapping_recalc(map->base, map->size); } - void mem_set_access(uint8_t bitmap, int mode, uint32_t base, uint32_t size, uint16_t access) { - uint32_t c; - uint16_t mask, smstate = 0x0000; - const uint16_t smstates[4] = { 0x0000, (MEM_READ_SMRAM | MEM_WRITE_SMRAM), - MEM_READ_SMRAM_EX, (MEM_READ_DISABLED_EX | MEM_WRITE_DISABLED_EX) }; + uint32_t c; + uint16_t mask, smstate = 0x0000; + const uint16_t smstates[4] = { 0x0000, (MEM_READ_SMRAM | MEM_WRITE_SMRAM), + MEM_READ_SMRAM_EX, (MEM_READ_DISABLED_EX | MEM_WRITE_DISABLED_EX) }; int i; if (mode) - mask = 0x2d6b; + mask = 0x2d6b; else - mask = 0x1084; + mask = 0x1084; if (mode) { - if (mode == 1) - access = !!access; + if (mode == 1) + access = !!access; - if (mode == 3) { - if (access & ACCESS_SMRAM_X) - smstate |= MEM_EXEC_SMRAM; - if (access & ACCESS_SMRAM_R) - smstate |= MEM_READ_SMRAM_2; - if (access & ACCESS_SMRAM_W) - smstate |= MEM_WRITE_SMRAM; - } else - smstate = smstates[access & 0x07]; + if (mode == 3) { + if (access & ACCESS_SMRAM_X) + smstate |= MEM_EXEC_SMRAM; + if (access & ACCESS_SMRAM_R) + smstate |= MEM_READ_SMRAM_2; + if (access & ACCESS_SMRAM_W) + smstate |= MEM_WRITE_SMRAM; + } else + smstate = smstates[access & 0x07]; } else - smstate = access & 0x6f7b; + smstate = access & 0x6f7b; for (c = 0; c < size; c += MEM_GRANULARITY_SIZE) { - for (i = 0; i < 4; i++) { - if (bitmap & (1 << i)) { - _mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] = - (_mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] & mask) | smstate; - } - } + for (i = 0; i < 4; i++) { + if (bitmap & (1 << i)) { + _mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] & mask) | smstate; + } + } #ifdef ENABLE_MEM_LOG - if (((c + base) >= 0xa0000) && ((c + base) <= 0xbffff)) { - mem_log("Set mem state for block at %08X to %04X with bitmap %02X\n", - c + base, smstate, bitmap); - } + if (((c + base) >= 0xa0000) && ((c + base) <= 0xbffff)) { + mem_log("Set mem state for block at %08X to %04X with bitmap %02X\n", + c + base, smstate, bitmap); + } #endif } mem_mapping_recalc(base, size); } - void mem_a20_init(void) { if (is286) { - rammask = cpu_16bitbus ? 0xefffff : 0xffefffff; - if (is6117) - rammask |= 0x03000000; - flushmmucache(); - mem_a20_state = mem_a20_key | mem_a20_alt; + rammask = cpu_16bitbus ? 0xefffff : 0xffefffff; + if (is6117) + rammask |= 0x03000000; + flushmmucache(); + mem_a20_state = mem_a20_key | mem_a20_alt; } else { - rammask = 0xfffff; - flushmmucache(); - mem_a20_key = mem_a20_alt = mem_a20_state = 0; + rammask = 0xfffff; + flushmmucache(); + mem_a20_key = mem_a20_alt = mem_a20_state = 0; } } - /* Close all the memory mappings. */ void mem_close(void) @@ -2581,25 +2483,23 @@ mem_close(void) mem_mapping_t *map = base_mapping, *next; while (map != NULL) { - next = map->next; - map->prev = map->next = NULL; - map = next; + next = map->next; + map->prev = map->next = NULL; + map = next; } base_mapping = last_mapping = 0; } - static void mem_add_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size) { mem_mapping_add(mapping, base, size, - mem_read_ram,mem_read_ramw,mem_read_raml, - mem_write_ram,mem_write_ramw,mem_write_raml, - ram + base, MEM_MAPPING_INTERNAL, NULL); + mem_read_ram, mem_read_ramw, mem_read_raml, + mem_write_ram, mem_write_ramw, mem_write_raml, + ram + base, MEM_MAPPING_INTERNAL, NULL); } - static void mem_init_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size) { @@ -2607,7 +2507,6 @@ mem_init_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size) mem_add_ram_mapping(mapping, base, size); } - /* Reset the memory state. */ void mem_reset(void) @@ -2618,71 +2517,71 @@ mem_reset(void) #ifdef USE_NEW_DYNAREC if (byte_dirty_mask) { - free(byte_dirty_mask); - byte_dirty_mask = NULL; + free(byte_dirty_mask); + byte_dirty_mask = NULL; } if (byte_code_present_mask) { - free(byte_code_present_mask); - byte_code_present_mask = NULL; + free(byte_code_present_mask); + byte_code_present_mask = NULL; } #endif /* Free the old pages array, if necessary. */ if (pages) { - free(pages); - pages = NULL; + free(pages); + pages = NULL; } if (ram != NULL) { - plat_munmap(ram, ram_size); - ram = NULL; - ram_size = 0; + plat_munmap(ram, ram_size); + ram = NULL; + ram_size = 0; } #if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)) if (ram2 != NULL) { - plat_munmap(ram2, ram2_size); - ram2 = NULL; - ram2_size = 0; + plat_munmap(ram2, ram2_size); + ram2 = NULL; + ram2_size = 0; } if (mem_size > 2097152) - mem_size = 2097152; + mem_size = 2097152; #endif m = 1024UL * mem_size; #if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)) if (mem_size > 1048576) { - ram_size = 1 << 30; - ram = (uint8_t *) plat_mmap(ram_size, 0); /* allocate and clear the RAM block of the first 1 GB */ - if (ram == NULL) { - fatal("Failed to allocate primary RAM block. Make sure you have enough RAM available.\n"); - return; - } - memset(ram, 0x00, ram_size); - ram2_size = m - (1 << 30); - ram2 = (uint8_t *) plat_mmap(ram2_size, 0); /* allocate and clear the RAM block above 1 GB */ - if (ram2 == NULL) { - if (config_changed == 2) - fatal(EMU_NAME " must be restarted for the memory amount change to be applied.\n"); - else - fatal("Failed to allocate secondary RAM block. Make sure you have enough RAM available.\n"); - return; - } - memset(ram2, 0x00, ram2_size); + ram_size = 1 << 30; + ram = (uint8_t *) plat_mmap(ram_size, 0); /* allocate and clear the RAM block of the first 1 GB */ + if (ram == NULL) { + fatal("Failed to allocate primary RAM block. Make sure you have enough RAM available.\n"); + return; + } + memset(ram, 0x00, ram_size); + ram2_size = m - (1 << 30); + ram2 = (uint8_t *) plat_mmap(ram2_size, 0); /* allocate and clear the RAM block above 1 GB */ + if (ram2 == NULL) { + if (config_changed == 2) + fatal(EMU_NAME " must be restarted for the memory amount change to be applied.\n"); + else + fatal("Failed to allocate secondary RAM block. Make sure you have enough RAM available.\n"); + return; + } + memset(ram2, 0x00, ram2_size); } else #endif { - ram_size = m; - ram = (uint8_t *) plat_mmap(ram_size, 0); /* allocate and clear the RAM block */ - if (ram == NULL) { - fatal("Failed to allocate RAM block. Make sure you have enough RAM available.\n"); - return; - } - memset(ram, 0x00, ram_size); - if (mem_size > 1048576) - ram2 = &(ram[1 << 30]); + ram_size = m; + ram = (uint8_t *) plat_mmap(ram_size, 0); /* allocate and clear the RAM block */ + if (ram == NULL) { + fatal("Failed to allocate RAM block. Make sure you have enough RAM available.\n"); + return; + } + memset(ram, 0x00, ram_size); + if (mem_size > 1048576) + ram2 = &(ram[1 << 30]); } /* @@ -2691,31 +2590,31 @@ mem_reset(void) * memory amount could have changed. */ if (is286) { - if (cpu_16bitbus) { - /* 80286/386SX; maximum address space is 16MB. */ - m = 4096; - /* ALi M6117; maximum address space is 64MB. */ - if (is6117) - m <<= 2; - } else { - /* 80386DX+; maximum address space is 4GB. */ - m = 1048576; - } + if (cpu_16bitbus) { + /* 80286/386SX; maximum address space is 16MB. */ + m = 4096; + /* ALi M6117; maximum address space is 64MB. */ + if (is6117) + m <<= 2; + } else { + /* 80386DX+; maximum address space is 4GB. */ + m = 1048576; + } } else { - /* 8088/86; maximum address space is 1MB. */ - m = 256; + /* 8088/86; maximum address space is 1MB. */ + m = 256; } /* * Allocate and initialize the (new) page table. */ pages_sz = m; - pages = (page_t *)malloc(m*sizeof(page_t)); + pages = (page_t *) malloc(m * sizeof(page_t)); memset(page_lookup, 0x00, (1 << 20) * sizeof(page_t *)); memset(page_lookupp, 0x04, (1 << 20) * sizeof(uint8_t)); - memset(pages, 0x00, pages_sz*sizeof(page_t)); + memset(pages, 0x00, pages_sz * sizeof(page_t)); #ifdef USE_NEW_DYNAREC byte_dirty_mask = malloc((mem_size * 1024) / 8); @@ -2726,38 +2625,38 @@ mem_reset(void) #endif for (c = 0; c < pages_sz; c++) { - if ((c << 12) >= (mem_size << 10)) - pages[c].mem = page_ff; - else { + if ((c << 12) >= (mem_size << 10)) + pages[c].mem = page_ff; + else { #if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)) - if (mem_size > 1048576) { - if ((c << 12) < (1 << 30)) - pages[c].mem = &ram[c << 12]; - else - pages[c].mem = &ram2[(c << 12) - (1 << 30)]; - } else - pages[c].mem = &ram[c << 12]; + if (mem_size > 1048576) { + if ((c << 12) < (1 << 30)) + pages[c].mem = &ram[c << 12]; + else + pages[c].mem = &ram2[(c << 12) - (1 << 30)]; + } else + pages[c].mem = &ram[c << 12]; #else - pages[c].mem = &ram[c << 12]; + pages[c].mem = &ram[c << 12]; #endif - } - if (c < m) { - pages[c].write_b = mem_write_ramb_page; - pages[c].write_w = mem_write_ramw_page; - pages[c].write_l = mem_write_raml_page; - } + } + if (c < m) { + pages[c].write_b = mem_write_ramb_page; + pages[c].write_w = mem_write_ramw_page; + pages[c].write_l = mem_write_raml_page; + } #ifdef USE_NEW_DYNAREC - pages[c].evict_prev = EVICT_NOT_IN_LIST; - pages[c].byte_dirty_mask = &byte_dirty_mask[c * 64]; - pages[c].byte_code_present_mask = &byte_code_present_mask[c * 64]; + pages[c].evict_prev = EVICT_NOT_IN_LIST; + pages[c].byte_dirty_mask = &byte_dirty_mask[c * 64]; + pages[c].byte_code_present_mask = &byte_code_present_mask[c * 64]; #endif } - memset(_mem_exec, 0x00, sizeof(_mem_exec)); - memset(write_mapping, 0x00, sizeof(write_mapping)); - memset(read_mapping, 0x00, sizeof(read_mapping)); + memset(_mem_exec, 0x00, sizeof(_mem_exec)); + memset(write_mapping, 0x00, sizeof(write_mapping)); + memset(read_mapping, 0x00, sizeof(read_mapping)); memset(write_mapping_bus, 0x00, sizeof(write_mapping_bus)); - memset(read_mapping_bus, 0x00, sizeof(read_mapping_bus)); + memset(read_mapping_bus, 0x00, sizeof(read_mapping_bus)); base_mapping = last_mapping = NULL; @@ -2768,159 +2667,156 @@ mem_reset(void) mem_init_ram_mapping(&ram_low_mapping, 0x000000, (mem_size > 640) ? 0xa0000 : mem_size * 1024); if (mem_size > 1024) { - if (cpu_16bitbus && !is6117 && mem_size > 16256) - mem_init_ram_mapping(&ram_high_mapping, 0x100000, (16256 - 1024) * 1024); - else if (cpu_16bitbus && is6117 && mem_size > 65408) - mem_init_ram_mapping(&ram_high_mapping, 0x100000, (65408 - 1024) * 1024); - else { - if (mem_size > 1048576) { - mem_init_ram_mapping(&ram_high_mapping, 0x100000, (1048576 - 1024) * 1024); + if (cpu_16bitbus && !is6117 && mem_size > 16256) + mem_init_ram_mapping(&ram_high_mapping, 0x100000, (16256 - 1024) * 1024); + else if (cpu_16bitbus && is6117 && mem_size > 65408) + mem_init_ram_mapping(&ram_high_mapping, 0x100000, (65408 - 1024) * 1024); + else { + if (mem_size > 1048576) { + mem_init_ram_mapping(&ram_high_mapping, 0x100000, (1048576 - 1024) * 1024); - mem_set_mem_state_both((1 << 30), (mem_size - 1048576) * 1024, - MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - mem_mapping_add(&ram_2gb_mapping, (1 << 30), - ((mem_size - 1048576) * 1024), - mem_read_ram_2gb,mem_read_ram_2gbw,mem_read_ram_2gbl, - mem_write_ram,mem_write_ramw,mem_write_raml, - ram2, MEM_MAPPING_INTERNAL, NULL); - } else - mem_init_ram_mapping(&ram_high_mapping, 0x100000, (mem_size - 1024) * 1024); - } + mem_set_mem_state_both((1 << 30), (mem_size - 1048576) * 1024, + MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_mapping_add(&ram_2gb_mapping, (1 << 30), + ((mem_size - 1048576) * 1024), + mem_read_ram_2gb, mem_read_ram_2gbw, mem_read_ram_2gbl, + mem_write_ram, mem_write_ramw, mem_write_raml, + ram2, MEM_MAPPING_INTERNAL, NULL); + } else + mem_init_ram_mapping(&ram_high_mapping, 0x100000, (mem_size - 1024) * 1024); + } } if (mem_size > 768) - mem_add_ram_mapping(&ram_mid_mapping, 0xa0000, 0x60000); + mem_add_ram_mapping(&ram_mid_mapping, 0xa0000, 0x60000); mem_mapping_add(&ram_remapped_mapping, mem_size * 1024, 256 * 1024, - mem_read_remapped,mem_read_remappedw,mem_read_remappedl, - mem_write_remapped,mem_write_remappedw,mem_write_remappedl, - ram + 0xa0000, MEM_MAPPING_INTERNAL, NULL); + mem_read_remapped, mem_read_remappedw, mem_read_remappedl, + mem_write_remapped, mem_write_remappedw, mem_write_remappedl, + ram + 0xa0000, MEM_MAPPING_INTERNAL, NULL); mem_mapping_disable(&ram_remapped_mapping); mem_a20_init(); #ifdef USE_NEW_DYNAREC purgable_page_list_head = 0; - purgeable_page_count = 0; + purgeable_page_count = 0; #endif } - void mem_init(void) { /* Perform a one-time init. */ ram = rom = NULL; - ram2 = NULL; - pages = NULL; + ram2 = NULL; + pages = NULL; /* Allocate the lookup tables. */ - page_lookup = (page_t **)malloc((1<<20)*sizeof(page_t *)); - page_lookupp = (uint8_t *)malloc((1<<20)*sizeof(uint8_t)); - readlookup2 = malloc((1<<20)*sizeof(uintptr_t)); - readlookupp = malloc((1<<20)*sizeof(uint8_t)); - writelookup2 = malloc((1<<20)*sizeof(uintptr_t)); - writelookupp = malloc((1<<20)*sizeof(uint8_t)); + page_lookup = (page_t **) malloc((1 << 20) * sizeof(page_t *)); + page_lookupp = (uint8_t *) malloc((1 << 20) * sizeof(uint8_t)); + readlookup2 = malloc((1 << 20) * sizeof(uintptr_t)); + readlookupp = malloc((1 << 20) * sizeof(uint8_t)); + writelookup2 = malloc((1 << 20) * sizeof(uintptr_t)); + writelookupp = malloc((1 << 20) * sizeof(uint8_t)); } - void mem_remap_top(int kb) { - uint32_t c; - uint32_t start = (mem_size >= 1024) ? mem_size : 1024; - int offset, size = mem_size - 640; - int set = 1; + uint32_t c; + uint32_t start = (mem_size >= 1024) ? mem_size : 1024; + int offset, size = mem_size - 640; + int set = 1; static int old_kb = 0; mem_log("MEM: remapping top %iKB (mem=%i)\n", kb, mem_size); - if (mem_size <= 640) return; + if (mem_size <= 640) + return; if (kb == 0) { - kb = old_kb; - set = 0; + kb = old_kb; + set = 0; } else - old_kb = kb; + old_kb = kb; if (size > kb) - size = kb; + size = kb; remap_start_addr = start << 10; for (c = ((start * 1024) >> 12); c < (((start + size) * 1024) >> 12); c++) { - offset = c - ((start * 1024) >> 12); - pages[c].mem = set ? &ram[0xa0000 + (offset << 12)] : page_ff; - pages[c].write_b = set ? mem_write_ramb_page : NULL; - pages[c].write_w = set ? mem_write_ramw_page : NULL; - pages[c].write_l = set ? mem_write_raml_page : NULL; + offset = c - ((start * 1024) >> 12); + pages[c].mem = set ? &ram[0xa0000 + (offset << 12)] : page_ff; + pages[c].write_b = set ? mem_write_ramb_page : NULL; + pages[c].write_w = set ? mem_write_ramw_page : NULL; + pages[c].write_l = set ? mem_write_raml_page : NULL; #ifdef USE_NEW_DYNAREC - pages[c].evict_prev = EVICT_NOT_IN_LIST; - pages[c].byte_dirty_mask = &byte_dirty_mask[offset * 64]; - pages[c].byte_code_present_mask = &byte_code_present_mask[offset * 64]; + pages[c].evict_prev = EVICT_NOT_IN_LIST; + pages[c].byte_dirty_mask = &byte_dirty_mask[offset * 64]; + pages[c].byte_code_present_mask = &byte_code_present_mask[offset * 64]; #endif } - mem_set_mem_state_both(start * 1024, size * 1024, set ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : - (MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL)); + mem_set_mem_state_both(start * 1024, size * 1024, set ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL)); if (set) { - mem_mapping_set_addr(&ram_remapped_mapping, start * 1024, size * 1024); - mem_mapping_set_exec(&ram_remapped_mapping, ram + 0xa0000); + mem_mapping_set_addr(&ram_remapped_mapping, start * 1024, size * 1024); + mem_mapping_set_exec(&ram_remapped_mapping, ram + 0xa0000); } else - mem_mapping_disable(&ram_remapped_mapping); + mem_mapping_disable(&ram_remapped_mapping); flushmmucache(); } - void mem_reset_page_blocks(void) { uint32_t c; - if (pages == NULL) return; + if (pages == NULL) + return; for (c = 0; c < pages_sz; c++) { - pages[c].write_b = mem_write_ramb_page; - pages[c].write_w = mem_write_ramw_page; - pages[c].write_l = mem_write_raml_page; + pages[c].write_b = mem_write_ramb_page; + pages[c].write_w = mem_write_ramw_page; + pages[c].write_l = mem_write_raml_page; #ifdef USE_NEW_DYNAREC - pages[c].block = BLOCK_INVALID; - pages[c].block_2 = BLOCK_INVALID; - pages[c].head = BLOCK_INVALID; + pages[c].block = BLOCK_INVALID; + pages[c].block_2 = BLOCK_INVALID; + pages[c].head = BLOCK_INVALID; #else - pages[c].block[0] = pages[c].block[1] = pages[c].block[2] = pages[c].block[3] = NULL; - pages[c].block_2[0] = pages[c].block_2[1] = pages[c].block_2[2] = pages[c].block_2[3] = NULL; - pages[c].head = NULL; + pages[c].block[0] = pages[c].block[1] = pages[c].block[2] = pages[c].block[3] = NULL; + pages[c].block_2[0] = pages[c].block_2[1] = pages[c].block_2[2] = pages[c].block_2[3] = NULL; + pages[c].head = NULL; #endif } } - void mem_a20_recalc(void) { int state; - if (! is286) { - rammask = 0xfffff; - flushmmucache(); - mem_a20_key = mem_a20_alt = mem_a20_state = 0; + if (!is286) { + rammask = 0xfffff; + flushmmucache(); + mem_a20_key = mem_a20_alt = mem_a20_state = 0; - return; + return; } state = mem_a20_key | mem_a20_alt; if (state && !mem_a20_state) { - rammask = (cpu_16bitbus) ? 0xffffff : 0xffffffff; - if (is6117) - rammask |= 0x03000000; - flushmmucache(); + rammask = (cpu_16bitbus) ? 0xffffff : 0xffffffff; + if (is6117) + rammask |= 0x03000000; + flushmmucache(); } else if (!state && mem_a20_state) { - rammask = (cpu_16bitbus) ? 0xefffff : 0xffefffff; - if (is6117) - rammask |= 0x03000000; - flushmmucache(); + rammask = (cpu_16bitbus) ? 0xefffff : 0xffefffff; + if (is6117) + rammask |= 0x03000000; + flushmmucache(); } mem_a20_state = state; diff --git a/src/mem/rom.c b/src/mem/rom.c index 955e5b85d..a1dbc55a1 100644 --- a/src/mem/rom.c +++ b/src/mem/rom.c @@ -38,35 +38,32 @@ #include <86box/machine.h> #include <86box/m_xt_xi8088.h> - #ifdef ENABLE_ROM_LOG int rom_do_log = ENABLE_ROM_LOG; - static void rom_log(const char *fmt, ...) { va_list ap; if (rom_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define rom_log(fmt, ...) +# define rom_log(fmt, ...) #endif void -rom_add_path(const char* path) +rom_add_path(const char *path) { char cwd[1024] = { 0 }; - rom_path_t* rom_path = &rom_paths; + rom_path_t *rom_path = &rom_paths; - if (rom_paths.path[0] != '\0') - { + if (rom_paths.path[0] != '\0') { // Iterate to the end of the list. while (rom_path->next != NULL) { rom_path = rom_path->next; @@ -77,7 +74,7 @@ rom_add_path(const char* path) } // Save the path, turning it into absolute if needed. - if (!path_abs((char*) path)) { + if (!path_abs((char *) path)) { plat_getcwd(cwd, sizeof(cwd)); path_slash(cwd); snprintf(rom_path->path, sizeof(rom_path->path), "%s%s", cwd, path); @@ -89,13 +86,12 @@ rom_add_path(const char* path) path_slash(rom_path->path); } - FILE * rom_fopen(char *fn, char *mode) { - char temp[1024]; + char temp[1024]; rom_path_t *rom_path; - FILE *fp = NULL; + FILE *fp = NULL; if (strstr(fn, "roms/") == fn) { /* Relative path */ @@ -114,11 +110,10 @@ rom_fopen(char *fn, char *mode) } } - int rom_getfile(char *fn, char *s, int size) { - char temp[1024]; + char temp[1024]; rom_path_t *rom_path; if (strstr(fn, "roms/") == fn) { @@ -144,7 +139,6 @@ rom_getfile(char *fn, char *s, int size) } } - int rom_present(char *fn) { @@ -152,104 +146,99 @@ rom_present(char *fn) f = rom_fopen(fn, "rb"); if (f != NULL) { - (void)fclose(f); - return(1); + (void) fclose(f); + return (1); } - return(0); + return (0); } - uint8_t rom_read(uint32_t addr, void *priv) { - rom_t *rom = (rom_t *)priv; + rom_t *rom = (rom_t *) priv; #ifdef ROM_TRACE - if (rom->mapping.base==ROM_TRACE) - rom_log("ROM: read byte from BIOS at %06lX\n", addr); + if (rom->mapping.base == ROM_TRACE) + rom_log("ROM: read byte from BIOS at %06lX\n", addr); #endif if (addr < rom->mapping.base) - return 0xff; + return 0xff; if (addr >= (rom->mapping.base + rom->sz)) - return 0xff; - return(rom->rom[(addr - rom->mapping.base) & rom->mask]); + return 0xff; + return (rom->rom[(addr - rom->mapping.base) & rom->mask]); } - uint16_t rom_readw(uint32_t addr, void *priv) { - rom_t *rom = (rom_t *)priv; + rom_t *rom = (rom_t *) priv; #ifdef ROM_TRACE - if (rom->mapping.base==ROM_TRACE) - rom_log("ROM: read word from BIOS at %06lX\n", addr); + if (rom->mapping.base == ROM_TRACE) + rom_log("ROM: read word from BIOS at %06lX\n", addr); #endif if (addr < (rom->mapping.base - 1)) - return 0xffff; + return 0xffff; if (addr >= (rom->mapping.base + rom->sz)) - return 0xffff; - return(*(uint16_t *)&rom->rom[(addr - rom->mapping.base) & rom->mask]); + return 0xffff; + return (*(uint16_t *) &rom->rom[(addr - rom->mapping.base) & rom->mask]); } - uint32_t rom_readl(uint32_t addr, void *priv) { - rom_t *rom = (rom_t *)priv; + rom_t *rom = (rom_t *) priv; #ifdef ROM_TRACE - if (rom->mapping.base==ROM_TRACE) - rom_log("ROM: read long from BIOS at %06lX\n", addr); + if (rom->mapping.base == ROM_TRACE) + rom_log("ROM: read long from BIOS at %06lX\n", addr); #endif if (addr < (rom->mapping.base - 3)) - return 0xffffffff; + return 0xffffffff; if (addr >= (rom->mapping.base + rom->sz)) - return 0xffffffff; - return(*(uint32_t *)&rom->rom[(addr - rom->mapping.base) & rom->mask]); + return 0xffffffff; + return (*(uint32_t *) &rom->rom[(addr - rom->mapping.base) & rom->mask]); } - int rom_load_linear_oddeven(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr) { FILE *f = rom_fopen(fn, "rb"); - int i; + int i; if (f == NULL) { - rom_log("ROM: image '%s' not found\n", fn); - return(0); + rom_log("ROM: image '%s' not found\n", fn); + return (0); } /* Make sure we only look at the base-256K offset. */ if (addr >= 0x40000) - addr = 0; + addr = 0; else - addr &= 0x03ffff; + addr &= 0x03ffff; if (ptr != NULL) { - if (fseek(f, off, SEEK_SET) == -1) - fatal("rom_load_linear(): Error seeking to the beginning of the file\n"); - for (i = 0; i < (sz >> 1); i++) { - if (fread(ptr + (addr + (i << 1)), 1, 1, f) != 1) - fatal("rom_load_linear(): Error reading even data\n"); - } - for (i = 0; i < (sz >> 1); i++) { - if (fread(ptr + (addr + (i << 1) + 1), 1, 1, f) != 1) - fatal("rom_load_linear(): Error reading od data\n"); - } + if (fseek(f, off, SEEK_SET) == -1) + fatal("rom_load_linear(): Error seeking to the beginning of the file\n"); + for (i = 0; i < (sz >> 1); i++) { + if (fread(ptr + (addr + (i << 1)), 1, 1, f) != 1) + fatal("rom_load_linear(): Error reading even data\n"); + } + for (i = 0; i < (sz >> 1); i++) { + if (fread(ptr + (addr + (i << 1) + 1), 1, 1, f) != 1) + fatal("rom_load_linear(): Error reading od data\n"); + } } - (void)fclose(f); + (void) fclose(f); - return(1); + return (1); } - /* Load a ROM BIOS from its chips, interleaved mode. */ int rom_load_linear(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr) @@ -257,29 +246,28 @@ rom_load_linear(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr) FILE *f = rom_fopen(fn, "rb"); if (f == NULL) { - rom_log("ROM: image '%s' not found\n", fn); - return(0); + rom_log("ROM: image '%s' not found\n", fn); + return (0); } /* Make sure we only look at the base-256K offset. */ if (addr >= 0x40000) - addr = 0; + addr = 0; else - addr &= 0x03ffff; + addr &= 0x03ffff; if (ptr != NULL) { - if (fseek(f, off, SEEK_SET) == -1) - fatal("rom_load_linear(): Error seeking to the beginning of the file\n"); - if (fread(ptr+addr, 1, sz, f) > sz) - fatal("rom_load_linear(): Error reading data\n"); + if (fseek(f, off, SEEK_SET) == -1) + fatal("rom_load_linear(): Error seeking to the beginning of the file\n"); + if (fread(ptr + addr, 1, sz, f) > sz) + fatal("rom_load_linear(): Error reading data\n"); } - (void)fclose(f); + (void) fclose(f); - return(1); + return (1); } - /* Load a ROM BIOS from its chips, linear mode with high bit flipped. */ int rom_load_linear_inverted(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr) @@ -287,84 +275,80 @@ rom_load_linear_inverted(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr) FILE *f = rom_fopen(fn, "rb"); if (f == NULL) { - rom_log("ROM: image '%s' not found\n", fn); - return(0); + rom_log("ROM: image '%s' not found\n", fn); + return (0); } /* Make sure we only look at the base-256K offset. */ - if (addr >= 0x40000) - { - addr = 0; - } - else - { - addr &= 0x03ffff; + if (addr >= 0x40000) { + addr = 0; + } else { + addr &= 0x03ffff; } - (void)fseek(f, 0, SEEK_END); + (void) fseek(f, 0, SEEK_END); if (ftell(f) < sz) { - (void)fclose(f); - return(0); + (void) fclose(f); + return (0); } if (ptr != NULL) { - if (fseek(f, off, SEEK_SET) == -1) - fatal("rom_load_linear_inverted(): Error seeking to the beginning of the file\n"); - if (fread(ptr+addr+0x10000, 1, sz >> 1, f) > (sz >> 1)) - fatal("rom_load_linear_inverted(): Error reading the upper half of the data\n"); - if (fread(ptr+addr, sz >> 1, 1, f) > (sz >> 1)) - fatal("rom_load_linear_inverted(): Error reading the lower half of the data\n"); + if (fseek(f, off, SEEK_SET) == -1) + fatal("rom_load_linear_inverted(): Error seeking to the beginning of the file\n"); + if (fread(ptr + addr + 0x10000, 1, sz >> 1, f) > (sz >> 1)) + fatal("rom_load_linear_inverted(): Error reading the upper half of the data\n"); + if (fread(ptr + addr, sz >> 1, 1, f) > (sz >> 1)) + fatal("rom_load_linear_inverted(): Error reading the lower half of the data\n"); } - (void)fclose(f); + (void) fclose(f); - return(1); + return (1); } - /* Load a ROM BIOS from its chips, interleaved mode. */ int rom_load_interleaved(char *fnl, char *fnh, uint32_t addr, int sz, int off, uint8_t *ptr) { FILE *fl = rom_fopen(fnl, "rb"); FILE *fh = rom_fopen(fnh, "rb"); - int c; + int c; if (fl == NULL || fh == NULL) { - if (fl == NULL) rom_log("ROM: image '%s' not found\n", fnl); - else (void)fclose(fl); - if (fh == NULL) rom_log("ROM: image '%s' not found\n", fnh); - else (void)fclose(fh); + if (fl == NULL) + rom_log("ROM: image '%s' not found\n", fnl); + else + (void) fclose(fl); + if (fh == NULL) + rom_log("ROM: image '%s' not found\n", fnh); + else + (void) fclose(fh); - return(0); + return (0); } /* Make sure we only look at the base-256K offset. */ - if (addr >= 0x40000) - { - addr = 0; - } - else - { - addr &= 0x03ffff; + if (addr >= 0x40000) { + addr = 0; + } else { + addr &= 0x03ffff; } if (ptr != NULL) { - (void)fseek(fl, off, SEEK_SET); - (void)fseek(fh, off, SEEK_SET); - for (c=0; c 0x4000; 0x4000 -> 0x4000; 0x6000 -> 0x8000 */ if (up && (n % MEM_GRANULARITY_SIZE)) - temp_n += MEM_GRANULARITY_SIZE; + temp_n += MEM_GRANULARITY_SIZE; return temp_n; } - - static uint8_t * rom_reset(uint32_t addr, int sz) { biosaddr = bios_normalize(addr, 0); biosmask = bios_normalize(sz, 1) - 1; if ((biosaddr + biosmask) > 0x000fffff) - biosaddr = 0x000fffff - biosmask; + biosaddr = 0x000fffff - biosmask; rom_log("Load BIOS: %i bytes at %08X-%08X\n", biosmask + 1, biosaddr, biosaddr + biosmask); /* If not done yet, allocate a 128KB buffer for the BIOS ROM. */ if (rom != NULL) { - rom_log("ROM allocated, freeing...\n"); - free(rom); - rom = NULL; + rom_log("ROM allocated, freeing...\n"); + free(rom); + rom = NULL; } rom_log("Allocating ROM...\n"); - rom = (uint8_t *)malloc(biosmask + 1); + rom = (uint8_t *) malloc(biosmask + 1); rom_log("Filling ROM with FF's...\n"); memset(rom, 0xff, biosmask + 1); return rom; } - uint8_t bios_read(uint32_t addr, void *priv) { @@ -413,12 +394,11 @@ bios_read(uint32_t addr, void *priv) addr &= 0x000fffff; if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) - ret = rom[addr - biosaddr]; + ret = rom[addr - biosaddr]; return ret; } - uint16_t bios_readw(uint32_t addr, void *priv) { @@ -427,12 +407,11 @@ bios_readw(uint32_t addr, void *priv) addr &= 0x000fffff; if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) - ret = *(uint16_t *)&rom[addr - biosaddr]; + ret = *(uint16_t *) &rom[addr - biosaddr]; return ret; } - uint32_t bios_readl(uint32_t addr, void *priv) { @@ -441,113 +420,110 @@ bios_readl(uint32_t addr, void *priv) addr &= 0x000fffff; if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) - ret = *(uint32_t *)&rom[addr - biosaddr]; + ret = *(uint32_t *) &rom[addr - biosaddr]; return ret; } - static void bios_add(void) { int temp_cpu_type, temp_cpu_16bitbus = 1; int temp_is286 = 0, temp_is6117 = 0; - if (/*AT && */cpu_s) { - temp_cpu_type = cpu_s->cpu_type; - temp_cpu_16bitbus = (temp_cpu_type == CPU_286 || temp_cpu_type == CPU_386SX || temp_cpu_type == CPU_486SLC || temp_cpu_type == CPU_IBM386SLC || temp_cpu_type == CPU_IBM486SLC ); - temp_is286 = (temp_cpu_type >= CPU_286); - temp_is6117 = !strcmp(cpu_f->manufacturer, "ALi"); + if (/*AT && */ cpu_s) { + temp_cpu_type = cpu_s->cpu_type; + temp_cpu_16bitbus = (temp_cpu_type == CPU_286 || temp_cpu_type == CPU_386SX || temp_cpu_type == CPU_486SLC || temp_cpu_type == CPU_IBM386SLC || temp_cpu_type == CPU_IBM486SLC); + temp_is286 = (temp_cpu_type >= CPU_286); + temp_is6117 = !strcmp(cpu_f->manufacturer, "ALi"); } if (biosmask > 0x1ffff) { - /* 256k+ BIOS'es only have low mappings at E0000-FFFFF. */ - mem_mapping_add(&bios_mapping, 0xe0000, 0x20000, - bios_read,bios_readw,bios_readl, - NULL,NULL,NULL, - &rom[0x20000], MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0); + /* 256k+ BIOS'es only have low mappings at E0000-FFFFF. */ + mem_mapping_add(&bios_mapping, 0xe0000, 0x20000, + bios_read, bios_readw, bios_readl, + NULL, NULL, NULL, + &rom[0x20000], MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, 0); - mem_set_mem_state_both(0x0e0000, 0x20000, - MEM_READ_ROMCS | MEM_WRITE_ROMCS); + mem_set_mem_state_both(0x0e0000, 0x20000, + MEM_READ_ROMCS | MEM_WRITE_ROMCS); } else { - mem_mapping_add(&bios_mapping, biosaddr, biosmask + 1, - bios_read,bios_readw,bios_readl, - NULL,NULL,NULL, - rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0); + mem_mapping_add(&bios_mapping, biosaddr, biosmask + 1, + bios_read, bios_readw, bios_readl, + NULL, NULL, NULL, + rom, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, 0); - mem_set_mem_state_both(biosaddr, biosmask + 1, - MEM_READ_ROMCS | MEM_WRITE_ROMCS); + mem_set_mem_state_both(biosaddr, biosmask + 1, + MEM_READ_ROMCS | MEM_WRITE_ROMCS); } if (temp_is6117) { - mem_mapping_add(&bios_high_mapping, biosaddr | 0x03f00000, biosmask + 1, - bios_read,bios_readw,bios_readl, - NULL,NULL,NULL, - rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0); + mem_mapping_add(&bios_high_mapping, biosaddr | 0x03f00000, biosmask + 1, + bios_read, bios_readw, bios_readl, + NULL, NULL, NULL, + rom, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, 0); - mem_set_mem_state_both(biosaddr | 0x03f00000, biosmask + 1, - MEM_READ_ROMCS | MEM_WRITE_ROMCS); + mem_set_mem_state_both(biosaddr | 0x03f00000, biosmask + 1, + MEM_READ_ROMCS | MEM_WRITE_ROMCS); } else if (temp_is286) { - mem_mapping_add(&bios_high_mapping, biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1, - bios_read,bios_readw,bios_readl, - NULL,NULL,NULL, - rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0); + mem_mapping_add(&bios_high_mapping, biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1, + bios_read, bios_readw, bios_readl, + NULL, NULL, NULL, + rom, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, 0); - mem_set_mem_state_both(biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1, - MEM_READ_ROMCS | MEM_WRITE_ROMCS); + mem_set_mem_state_both(biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1, + MEM_READ_ROMCS | MEM_WRITE_ROMCS); } } - /* These four are for loading the BIOS. */ int bios_load(char *fn1, char *fn2, uint32_t addr, int sz, int off, int flags) { - uint8_t ret = 0; + uint8_t ret = 0; uint8_t *ptr = NULL; - int i, old_sz = sz; + int i, old_sz = sz; /* - f0000, 65536 = prepare 64k rom starting at f0000, load 64k bios at 0000 - fe000, 65536 = prepare 64k rom starting at f0000, load 8k bios at e000 - fe000, 49152 = prepare 48k rom starting at f4000, load 8k bios at a000 - fe000, 8192 = prepare 16k rom starting at fc000, load 8k bios at 2000 + f0000, 65536 = prepare 64k rom starting at f0000, load 64k bios at 0000 + fe000, 65536 = prepare 64k rom starting at f0000, load 8k bios at e000 + fe000, 49152 = prepare 48k rom starting at f4000, load 8k bios at a000 + fe000, 8192 = prepare 16k rom starting at fc000, load 8k bios at 2000 */ if (!bios_only) - ptr = (flags & FLAG_AUX) ? rom : rom_reset(addr, sz); + ptr = (flags & FLAG_AUX) ? rom : rom_reset(addr, sz); if (!(flags & FLAG_AUX) && ((addr + sz) > 0x00100000)) - sz = 0x00100000 - addr; + sz = 0x00100000 - addr; #ifdef ENABLE_ROM_LOG if (!bios_only) - rom_log("%sing %i bytes of %sBIOS starting with ptr[%08X] (ptr = %08X)\n", (bios_only) ? "Check" : "Load", sz, (flags & FLAG_AUX) ? "auxiliary " : "", addr - biosaddr, ptr); + rom_log("%sing %i bytes of %sBIOS starting with ptr[%08X] (ptr = %08X)\n", (bios_only) ? "Check" : "Load", sz, (flags & FLAG_AUX) ? "auxiliary " : "", addr - biosaddr, ptr); #endif if (flags & FLAG_INT) - ret = rom_load_interleaved(fn1, fn2, addr - biosaddr, sz, off, ptr); + ret = rom_load_interleaved(fn1, fn2, addr - biosaddr, sz, off, ptr); else { - if (flags & FLAG_INV) - ret = rom_load_linear_inverted(fn1, addr - biosaddr, sz, off, ptr); - else - ret = rom_load_linear(fn1, addr - biosaddr, sz, off, ptr); + if (flags & FLAG_INV) + ret = rom_load_linear_inverted(fn1, addr - biosaddr, sz, off, ptr); + else + ret = rom_load_linear(fn1, addr - biosaddr, sz, off, ptr); } if (!bios_only && (flags & FLAG_REP) && (old_sz >= 65536) && (sz < old_sz)) { - old_sz /= sz; - for (i = 0; i < (old_sz - 1); i++) { - rom_log("Copying ptr[%08X] to ptr[%08X]\n", addr - biosaddr, i * sz); - memcpy(&(ptr[i * sz]), &(ptr[addr - biosaddr]), sz); - } + old_sz /= sz; + for (i = 0; i < (old_sz - 1); i++) { + rom_log("Copying ptr[%08X] to ptr[%08X]\n", addr - biosaddr, i * sz); + memcpy(&(ptr[i * sz]), &(ptr[addr - biosaddr]), sz); + } } if (!bios_only && ret && !(flags & FLAG_AUX)) - bios_add(); + bios_add(); return ret; } - int bios_load_linear_combined(char *fn1, char *fn2, int sz, int off) { @@ -559,7 +535,6 @@ bios_load_linear_combined(char *fn1, char *fn2, int sz, int off) return ret; } - int bios_load_linear_combined2(char *fn1, char *fn2, char *fn3, char *fn4, char *fn5, int sz, int off) { @@ -570,12 +545,11 @@ bios_load_linear_combined2(char *fn1, char *fn2, char *fn3, char *fn4, char *fn5 ret &= bios_load_aux_linear(fn2, 0x000c0000, 65536, off); ret &= bios_load_aux_linear(fn4, 0x000e0000, sz - 196608, off); if (fn5 != NULL) - ret &= bios_load_aux_linear(fn5, 0x000ec000, 16384, 0); + ret &= bios_load_aux_linear(fn5, 0x000ec000, 16384, 0); return ret; } - int bios_load_linear_combined2_ex(char *fn1, char *fn2, char *fn3, char *fn4, char *fn5, int sz, int off) { @@ -586,12 +560,11 @@ bios_load_linear_combined2_ex(char *fn1, char *fn2, char *fn3, char *fn4, char * ret &= bios_load_aux_linear(fn2, 0x000d0000, 65536, off); ret &= bios_load_aux_linear(fn4, 0x000f0000, sz - 196608, off); if (fn5 != NULL) - ret &= bios_load_aux_linear(fn5, 0x000fc000, 16384, 0); + ret &= bios_load_aux_linear(fn5, 0x000fc000, 16384, 0); return ret; } - int rom_init(rom_t *rom, char *fn, uint32_t addr, int sz, int mask, int off, uint32_t flags) { @@ -602,26 +575,25 @@ rom_init(rom_t *rom, char *fn, uint32_t addr, int sz, int mask, int off, uint32_ memset(rom->rom, 0xff, sz); /* Load the image file into the buffer. */ - if (! rom_load_linear(fn, addr, sz, off, rom->rom)) { - /* Nope.. clean up. */ - free(rom->rom); - rom->rom = NULL; - return(-1); + if (!rom_load_linear(fn, addr, sz, off, rom->rom)) { + /* Nope.. clean up. */ + free(rom->rom); + rom->rom = NULL; + return (-1); } - rom->sz = sz; + rom->sz = sz; rom->mask = mask; mem_mapping_add(&rom->mapping, - addr, sz, - rom_read, rom_readw, rom_readl, - NULL, NULL, NULL, - rom->rom, flags | MEM_MAPPING_ROM_WS, rom); + addr, sz, + rom_read, rom_readw, rom_readl, + NULL, NULL, NULL, + rom->rom, flags | MEM_MAPPING_ROM_WS, rom); - return(0); + return (0); } - int rom_init_oddeven(rom_t *rom, char *fn, uint32_t addr, int sz, int mask, int off, uint32_t flags) { @@ -632,26 +604,25 @@ rom_init_oddeven(rom_t *rom, char *fn, uint32_t addr, int sz, int mask, int off, memset(rom->rom, 0xff, sz); /* Load the image file into the buffer. */ - if (! rom_load_linear_oddeven(fn, addr, sz, off, rom->rom)) { - /* Nope.. clean up. */ - free(rom->rom); - rom->rom = NULL; - return(-1); + if (!rom_load_linear_oddeven(fn, addr, sz, off, rom->rom)) { + /* Nope.. clean up. */ + free(rom->rom); + rom->rom = NULL; + return (-1); } - rom->sz = sz; + rom->sz = sz; rom->mask = mask; mem_mapping_add(&rom->mapping, - addr, sz, - rom_read, rom_readw, rom_readl, - NULL, NULL, NULL, - rom->rom, flags | MEM_MAPPING_ROM_WS, rom); + addr, sz, + rom_read, rom_readw, rom_readl, + NULL, NULL, NULL, + rom->rom, flags | MEM_MAPPING_ROM_WS, rom); - return(0); + return (0); } - int rom_init_interleaved(rom_t *rom, char *fnl, char *fnh, uint32_t addr, int sz, int mask, int off, uint32_t flags) { @@ -660,21 +631,21 @@ rom_init_interleaved(rom_t *rom, char *fnl, char *fnh, uint32_t addr, int sz, in memset(rom->rom, 0xff, sz); /* Load the image file into the buffer. */ - if (! rom_load_interleaved(fnl, fnh, addr, sz, off, rom->rom)) { - /* Nope.. clean up. */ - free(rom->rom); - rom->rom = NULL; - return(-1); + if (!rom_load_interleaved(fnl, fnh, addr, sz, off, rom->rom)) { + /* Nope.. clean up. */ + free(rom->rom); + rom->rom = NULL; + return (-1); } - rom->sz = sz; + rom->sz = sz; rom->mask = mask; mem_mapping_add(&rom->mapping, - addr, sz, - rom_read, rom_readw, rom_readl, - NULL, NULL, NULL, - rom->rom, flags | MEM_MAPPING_ROM_WS, rom); + addr, sz, + rom_read, rom_readw, rom_readl, + NULL, NULL, NULL, + rom->rom, flags | MEM_MAPPING_ROM_WS, rom); - return(0); + return (0); } diff --git a/src/mem/smram.c b/src/mem/smram.c index 9333264d9..64f3417aa 100644 --- a/src/mem/smram.c +++ b/src/mem/smram.c @@ -29,117 +29,107 @@ #include <86box/mem.h> #include <86box/smram.h> +static smram_t *base_smram, *last_smram; -static smram_t *base_smram, *last_smram; - -static uint8_t use_separate_smram = 0; -static uint8_t smram[0x40000]; - +static uint8_t use_separate_smram = 0; +static uint8_t smram[0x40000]; #ifdef ENABLE_SMRAM_LOG int smram_do_log = ENABLE_SMRAM_LOG; - static void smram_log(const char *fmt, ...) { va_list ap; if (smram_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define smram_log(fmt, ...) +# define smram_log(fmt, ...) #endif - static uint8_t smram_read(uint32_t addr, void *priv) { - smram_t *dev = (smram_t *) priv; + smram_t *dev = (smram_t *) priv; uint32_t new_addr = addr - dev->host_base + dev->ram_base; if (new_addr >= (1 << 30)) - return mem_read_ram_2gb(new_addr, priv); + return mem_read_ram_2gb(new_addr, priv); else if (!use_separate_smram || (new_addr >= 0xa0000)) - return mem_read_ram(new_addr, priv); + return mem_read_ram(new_addr, priv); else - return dev->mapping.exec[addr - dev->host_base]; + return dev->mapping.exec[addr - dev->host_base]; } - static uint16_t smram_readw(uint32_t addr, void *priv) { - smram_t *dev = (smram_t *) priv; + smram_t *dev = (smram_t *) priv; uint32_t new_addr = addr - dev->host_base + dev->ram_base; if (new_addr >= (1 << 30)) - return mem_read_ram_2gbw(new_addr, priv); + return mem_read_ram_2gbw(new_addr, priv); else if (!use_separate_smram || (new_addr >= 0xa0000)) - return mem_read_ramw(new_addr, priv); + return mem_read_ramw(new_addr, priv); else - return *(uint16_t *) &(dev->mapping.exec[addr - dev->host_base]); + return *(uint16_t *) &(dev->mapping.exec[addr - dev->host_base]); } - static uint32_t smram_readl(uint32_t addr, void *priv) { - smram_t *dev = (smram_t *) priv; + smram_t *dev = (smram_t *) priv; uint32_t new_addr = addr - dev->host_base + dev->ram_base; if (new_addr >= (1 << 30)) - return mem_read_ram_2gbl(new_addr, priv); + return mem_read_ram_2gbl(new_addr, priv); else if (!use_separate_smram || (new_addr >= 0xa0000)) - return mem_read_raml(new_addr, priv); + return mem_read_raml(new_addr, priv); else - return *(uint32_t *) &(dev->mapping.exec[addr - dev->host_base]); + return *(uint32_t *) &(dev->mapping.exec[addr - dev->host_base]); } - static void smram_write(uint32_t addr, uint8_t val, void *priv) { - smram_t *dev = (smram_t *) priv; + smram_t *dev = (smram_t *) priv; uint32_t new_addr = addr - dev->host_base + dev->ram_base; if (!use_separate_smram || (new_addr >= 0xa0000)) - mem_write_ram(new_addr, val, priv); + mem_write_ram(new_addr, val, priv); else - dev->mapping.exec[addr - dev->host_base] = val; + dev->mapping.exec[addr - dev->host_base] = val; } - static void smram_writew(uint32_t addr, uint16_t val, void *priv) { - smram_t *dev = (smram_t *) priv; + smram_t *dev = (smram_t *) priv; uint32_t new_addr = addr - dev->host_base + dev->ram_base; if (!use_separate_smram || (new_addr >= 0xa0000)) - mem_write_ramw(new_addr, val, priv); + mem_write_ramw(new_addr, val, priv); else - *(uint16_t *) &(dev->mapping.exec[addr - dev->host_base]) = val; + *(uint16_t *) &(dev->mapping.exec[addr - dev->host_base]) = val; } - static void smram_writel(uint32_t addr, uint32_t val, void *priv) { - smram_t *dev = (smram_t *) priv; + smram_t *dev = (smram_t *) priv; uint32_t new_addr = addr - dev->host_base + dev->ram_base; if (!use_separate_smram || (new_addr >= 0xa0000)) - mem_write_raml(new_addr, val, priv); + mem_write_raml(new_addr, val, priv); else - *(uint32_t *) &(dev->mapping.exec[addr - dev->host_base]) = val; + *(uint32_t *) &(dev->mapping.exec[addr - dev->host_base]) = val; } - /* Make a backup copy of host_base and size of all the SMRAM structs, needed so that if the SMRAM mappings change while in SMM, they will be recalculated on return. */ void @@ -148,15 +138,14 @@ smram_backup_all(void) smram_t *temp_smram = base_smram, *next; while (temp_smram != NULL) { - temp_smram->old_host_base = temp_smram->host_base; - temp_smram->old_size = temp_smram->size; + temp_smram->old_host_base = temp_smram->host_base; + temp_smram->old_size = temp_smram->size; - next = temp_smram->next; - temp_smram = next; + next = temp_smram->next; + temp_smram = next; } } - /* Recalculate any mappings, including the backup if returning from SMM. */ void smram_recalc_all(int ret) @@ -164,55 +153,54 @@ smram_recalc_all(int ret) smram_t *temp_smram = base_smram, *next; if (base_smram == NULL) - return; + return; if (ret) { - while (temp_smram != NULL) { - if (temp_smram->old_size != 0x00000000) - mem_mapping_recalc(temp_smram->old_host_base, temp_smram->old_size); - temp_smram->old_host_base = temp_smram->old_size = 0x00000000; + while (temp_smram != NULL) { + if (temp_smram->old_size != 0x00000000) + mem_mapping_recalc(temp_smram->old_host_base, temp_smram->old_size); + temp_smram->old_host_base = temp_smram->old_size = 0x00000000; - next = temp_smram->next; - temp_smram = next; - } + next = temp_smram->next; + temp_smram = next; + } } temp_smram = base_smram; while (temp_smram != NULL) { - if (temp_smram->size != 0x00000000) - mem_mapping_recalc(temp_smram->host_base, temp_smram->size); + if (temp_smram->size != 0x00000000) + mem_mapping_recalc(temp_smram->host_base, temp_smram->size); - next = temp_smram->next; - temp_smram = next; + next = temp_smram->next; + temp_smram = next; } flushmmucache(); } - /* Delete a SMRAM mapping. */ void smram_del(smram_t *smr) { /* Do a sanity check */ if ((base_smram == NULL) && (last_smram != NULL)) { - fatal("smram_del(): NULL base SMRAM with non-NULL last SMRAM\n"); - return; + fatal("smram_del(): NULL base SMRAM with non-NULL last SMRAM\n"); + return; } else if ((base_smram != NULL) && (last_smram == NULL)) { - fatal("smram_del(): Non-NULL base SMRAM with NULL last SMRAM\n"); - return; + fatal("smram_del(): Non-NULL base SMRAM with NULL last SMRAM\n"); + return; } else if ((base_smram != NULL) && (base_smram->prev != NULL)) { - fatal("smram_del(): Base SMRAM with a preceding SMRAM\n"); - return; + fatal("smram_del(): Base SMRAM with a preceding SMRAM\n"); + return; } else if ((last_smram != NULL) && (last_smram->next != NULL)) { - fatal("smram_del(): Last SMRAM with a following SMRAM\n"); - return; + fatal("smram_del(): Last SMRAM with a following SMRAM\n"); + return; } if (smr == NULL) { - fatal("smram_del(): Invalid SMRAM mapping\n"); - return; + fatal("smram_del(): Invalid SMRAM mapping\n"); + return; } /* Disable the entry. */ @@ -220,20 +208,19 @@ smram_del(smram_t *smr) /* Zap it from the list. */ if (smr->prev != NULL) - smr->prev->next = smr->next; + smr->prev->next = smr->next; if (smr->next != NULL) - smr->next->prev = smr->prev; + smr->next->prev = smr->prev; /* Check if it's the first or the last mapping. */ if (base_smram == smr) - base_smram = smr->next; + base_smram = smr->next; if (last_smram == smr) - last_smram = smr->prev; + last_smram = smr->prev; free(smr); } - /* Add a SMRAM mapping. */ smram_t * smram_add(void) @@ -242,63 +229,61 @@ smram_add(void) /* Do a sanity check */ if ((base_smram == NULL) && (last_smram != NULL)) { - fatal("smram_add(): NULL base SMRAM with non-NULL last SMRAM\n"); - return NULL; + fatal("smram_add(): NULL base SMRAM with non-NULL last SMRAM\n"); + return NULL; } else if ((base_smram != NULL) && (last_smram == NULL)) { - fatal("smram_add(): Non-NULL base SMRAM with NULL last SMRAM\n"); - return NULL; + fatal("smram_add(): Non-NULL base SMRAM with NULL last SMRAM\n"); + return NULL; } else if ((base_smram != NULL) && (base_smram->prev != NULL)) { - fatal("smram_add(): Base SMRAM with a preceding SMRAM\n"); - return NULL; + fatal("smram_add(): Base SMRAM with a preceding SMRAM\n"); + return NULL; } else if ((last_smram != NULL) && (last_smram->next != NULL)) { - fatal("smram_add(): Last SMRAM with a following SMRAM\n"); - return NULL; + fatal("smram_add(): Last SMRAM with a following SMRAM\n"); + return NULL; } temp_smram = (smram_t *) malloc(sizeof(smram_t)); if (temp_smram == NULL) { - fatal("smram_add(): temp_smram malloc failed\n"); - return NULL; + fatal("smram_add(): temp_smram malloc failed\n"); + return NULL; } memset(temp_smram, 0x00, sizeof(smram_t)); memset(&(temp_smram->mapping), 0x00, sizeof(mem_mapping_t)); /* Add struct to the beginning of the list if necessary.*/ if (base_smram == NULL) - base_smram = temp_smram; + base_smram = temp_smram; /* Add struct to the end of the list.*/ if (last_smram == NULL) - temp_smram->prev = NULL; - else { - temp_smram->prev = last_smram; - last_smram->next = temp_smram; + temp_smram->prev = NULL; + else { + temp_smram->prev = last_smram; + last_smram->next = temp_smram; } last_smram = temp_smram; mem_mapping_add(&(temp_smram->mapping), 0x00000000, 0x00000000, - smram_read,smram_readw,smram_readl, - smram_write,smram_writew,smram_writel, - ram, MEM_MAPPING_SMRAM, temp_smram); + smram_read, smram_readw, smram_readl, + smram_write, smram_writew, smram_writel, + ram, MEM_MAPPING_SMRAM, temp_smram); smram_set_separate_smram(0); return temp_smram; } - /* Set memory state in the specified model (normal or SMM) according to the specified flags, separately for bus and CPU. */ void smram_map_ex(int bus, int smm, uint32_t addr, uint32_t size, int is_smram) { if (bus) - mem_set_access_smram_bus(smm, addr, size, is_smram); + mem_set_access_smram_bus(smm, addr, size, is_smram); else - mem_set_access_smram_cpu(smm, addr, size, is_smram); + mem_set_access_smram_cpu(smm, addr, size, is_smram); } - /* Set memory state in the specified model (normal or SMM) according to the specified flags. */ void smram_map(int smm, uint32_t addr, uint32_t size, int is_smram) @@ -307,28 +292,26 @@ smram_map(int smm, uint32_t addr, uint32_t size, int is_smram) smram_map_ex(1, smm, addr, size, is_smram); } - /* Disable a specific SMRAM mapping. */ void smram_disable(smram_t *smr) { if (smr == NULL) { - fatal("smram_disable(): Invalid SMRAM mapping\n"); - return; + fatal("smram_disable(): Invalid SMRAM mapping\n"); + return; } if (smr->size != 0x00000000) { - smram_map(0, smr->host_base, smr->size, 0); - smram_map(1, smr->host_base, smr->size, 0); + smram_map(0, smr->host_base, smr->size, 0); + smram_map(1, smr->host_base, smr->size, 0); - smr->host_base = smr->ram_base = 0x00000000; - smr->size = 0x00000000; + smr->host_base = smr->ram_base = 0x00000000; + smr->size = 0x00000000; - mem_mapping_disable(&(smr->mapping)); + mem_mapping_disable(&(smr->mapping)); } } - /* Disable all SMRAM mappings. */ void smram_disable_all(void) @@ -336,56 +319,54 @@ smram_disable_all(void) smram_t *temp_smram = base_smram, *next; while (temp_smram != NULL) { - smram_disable(temp_smram); + smram_disable(temp_smram); - next = temp_smram->next; - temp_smram = next; + next = temp_smram->next; + temp_smram = next; } } - /* Enable SMRAM mappings according to flags for both normal and SMM modes, separately for bus and CPU. */ void smram_enable_ex(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size, - int flags_normal, int flags_normal_bus, int flags_smm, int flags_smm_bus) + int flags_normal, int flags_normal_bus, int flags_smm, int flags_smm_bus) { if (smr == NULL) { - fatal("smram_add(): Invalid SMRAM mapping\n"); - return; + fatal("smram_add(): Invalid SMRAM mapping\n"); + return; } if ((size != 0x00000000) && (flags_normal || flags_smm)) { - smr->host_base = host_base; - smr->ram_base = ram_base, - smr->size = size; + smr->host_base = host_base; + smr->ram_base = ram_base, + smr->size = size; - mem_mapping_set_addr(&(smr->mapping), smr->host_base, smr->size); - if (!use_separate_smram || (smr->ram_base >= 0x000a0000)) { - if (smr->ram_base < (1 << 30)) - mem_mapping_set_exec(&(smr->mapping), ram + smr->ram_base); - else - mem_mapping_set_exec(&(smr->mapping), ram2 + smr->ram_base - (1 << 30)); - } else { - if (smr->ram_base == 0x00030000) - mem_mapping_set_exec(&(smr->mapping), smram); - else if (smr->ram_base == 0x00040000) - mem_mapping_set_exec(&(smr->mapping), smram + 0x10000); - else if (smr->ram_base == 0x00060000) - mem_mapping_set_exec(&(smr->mapping), smram + 0x20000); - else if (smr->ram_base == 0x00070000) - mem_mapping_set_exec(&(smr->mapping), smram + 0x30000); - } + mem_mapping_set_addr(&(smr->mapping), smr->host_base, smr->size); + if (!use_separate_smram || (smr->ram_base >= 0x000a0000)) { + if (smr->ram_base < (1 << 30)) + mem_mapping_set_exec(&(smr->mapping), ram + smr->ram_base); + else + mem_mapping_set_exec(&(smr->mapping), ram2 + smr->ram_base - (1 << 30)); + } else { + if (smr->ram_base == 0x00030000) + mem_mapping_set_exec(&(smr->mapping), smram); + else if (smr->ram_base == 0x00040000) + mem_mapping_set_exec(&(smr->mapping), smram + 0x10000); + else if (smr->ram_base == 0x00060000) + mem_mapping_set_exec(&(smr->mapping), smram + 0x20000); + else if (smr->ram_base == 0x00070000) + mem_mapping_set_exec(&(smr->mapping), smram + 0x30000); + } - smram_map_ex(0, 0, host_base, size, flags_normal); - smram_map_ex(1, 0, host_base, size, flags_normal_bus); - smram_map_ex(0, 1, host_base, size, flags_smm); - smram_map_ex(1, 1, host_base, size, flags_smm_bus); + smram_map_ex(0, 0, host_base, size, flags_normal); + smram_map_ex(1, 0, host_base, size, flags_normal_bus); + smram_map_ex(0, 1, host_base, size, flags_smm); + smram_map_ex(1, 1, host_base, size, flags_smm_bus); } else - smram_disable(smr); + smram_disable(smr); } - /* Enable SMRAM mappings according to flags for both normal and SMM modes. */ void smram_enable(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size, int flags_normal, int flags_smm) @@ -393,7 +374,6 @@ smram_enable(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size, smram_enable_ex(smr, host_base, ram_base, size, flags_normal, flags_normal, flags_smm, flags_smm); } - /* Checks if a SMRAM mapping is enabled or not. */ int smram_enabled(smram_t *smr) @@ -401,27 +381,25 @@ smram_enabled(smram_t *smr) int ret = 0; if (smr == NULL) - ret = 0; + ret = 0; else - ret = (smr->size != 0x00000000); + ret = (smr->size != 0x00000000); return ret; } - /* Changes the SMRAM state. */ void smram_state_change(smram_t *smr, int smm, int flags) { if (smr == NULL) { - fatal("smram_tate_change(): Invalid SMRAM mapping\n"); - return; + fatal("smram_tate_change(): Invalid SMRAM mapping\n"); + return; } smram_map(smm, smr->host_base, smr->size, flags); } - void smram_set_separate_smram(uint8_t set) { diff --git a/src/mem/spd.c b/src/mem/spd.c index acc7ced9f..b88508a61 100644 --- a/src/mem/spd.c +++ b/src/mem/spd.c @@ -28,58 +28,52 @@ #include <86box/version.h> #include <86box/machine.h> +#define SPD_ROLLUP(x) ((x) >= 16 ? ((x) -15) : (x)) -#define SPD_ROLLUP(x) ((x) >= 16 ? ((x) - 15) : (x)) - - -int spd_present = 0; -spd_t *spd_modules[SPD_MAX_SLOTS]; +int spd_present = 0; +spd_t *spd_modules[SPD_MAX_SLOTS]; static const device_t spd_device; - #ifdef ENABLE_SPD_LOG int spd_do_log = ENABLE_SPD_LOG; - static void spd_log(const char *fmt, ...) { va_list ap; if (spd_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define spd_log(fmt, ...) +# define spd_log(fmt, ...) #endif - static void spd_close(void *priv) { spd_log("SPD: close()\n"); for (uint8_t i = 0; i < SPD_MAX_SLOTS; i++) { - if (spd_modules[i]) - i2c_eeprom_close(spd_modules[i]->eeprom); + if (spd_modules[i]) + i2c_eeprom_close(spd_modules[i]->eeprom); } spd_present = 0; } - static void * spd_init(const device_t *info) { spd_log("SPD: init()\n"); for (uint8_t i = 0; i < SPD_MAX_SLOTS; i++) { - if (spd_modules[i]) - spd_modules[i]->eeprom = i2c_eeprom_init(i2c_smbus, SPD_BASE_ADDR + i, spd_modules[i]->data, sizeof(spd_modules[i]->data), 0); + if (spd_modules[i]) + spd_modules[i]->eeprom = i2c_eeprom_init(i2c_smbus, SPD_BASE_ADDR + i, spd_modules[i]->data, sizeof(spd_modules[i]->data), 0); } spd_present = 1; @@ -87,7 +81,6 @@ spd_init(const device_t *info) return &spd_modules; } - int comp_ui16_rev(const void *elem1, const void *elem2) { @@ -96,123 +89,120 @@ comp_ui16_rev(const void *elem1, const void *elem2) return ((a > b) ? -1 : ((a < b) ? 1 : 0)); } - void spd_populate(uint16_t *rows, uint8_t slot_count, uint16_t total_size, uint16_t min_module_size, uint16_t max_module_size, uint8_t enable_asym) { - uint8_t row, next_empty_row, split, i; + uint8_t row, next_empty_row, split, i; uint16_t asym; /* Populate rows with modules in power-of-2 capacities. */ memset(rows, 0, SPD_MAX_SLOTS << 1); for (row = 0; row < slot_count && total_size; row++) { - /* populate slot */ - rows[row] = 1 << log2i(MIN(total_size, max_module_size)); - if (total_size >= rows[row]) { - spd_log("SPD: Initial row %d = %d MB\n", row, rows[row]); - total_size -= rows[row]; - } else { - rows[row] = 0; - break; - } + /* populate slot */ + rows[row] = 1 << log2i(MIN(total_size, max_module_size)); + if (total_size >= rows[row]) { + spd_log("SPD: Initial row %d = %d MB\n", row, rows[row]); + total_size -= rows[row]; + } else { + rows[row] = 0; + break; + } } /* Did we populate all the RAM? */ if (total_size) { - /* Work backwards to add the missing RAM as asymmetric modules if possible. */ - if (enable_asym) { - row = slot_count - 1; - do { - asym = (1 << log2i(MIN(total_size, rows[row]))); - if (rows[row] + asym <= max_module_size) { - rows[row] += asym; - total_size -= asym; - } - } while ((row-- > 0) && total_size); - } + /* Work backwards to add the missing RAM as asymmetric modules if possible. */ + if (enable_asym) { + row = slot_count - 1; + do { + asym = (1 << log2i(MIN(total_size, rows[row]))); + if (rows[row] + asym <= max_module_size) { + rows[row] += asym; + total_size -= asym; + } + } while ((row-- > 0) && total_size); + } - if (total_size) /* still not enough */ - spd_log("SPD: Not enough RAM slots (%d) to cover memory (%d MB short)\n", slot_count, total_size); + if (total_size) /* still not enough */ + spd_log("SPD: Not enough RAM slots (%d) to cover memory (%d MB short)\n", slot_count, total_size); } /* Populate empty rows by splitting modules... */ split = (total_size == 0); /* ...if possible. */ while (split) { - /* Look for a module to split. */ - split = 0; - for (row = 0; row < slot_count; row++) { - if ((rows[row] < (min_module_size << 1)) || (rows[row] != (1 << log2i(rows[row])))) - continue; /* no module here, module is too small to be split, or asymmetric module */ + /* Look for a module to split. */ + split = 0; + for (row = 0; row < slot_count; row++) { + if ((rows[row] < (min_module_size << 1)) || (rows[row] != (1 << log2i(rows[row])))) + continue; /* no module here, module is too small to be split, or asymmetric module */ - /* Find next empty row. */ - next_empty_row = 0; - for (i = row + 1; i < slot_count && !next_empty_row; i++) { - if (!rows[i]) - next_empty_row = i; - } - if (!next_empty_row) - break; /* no empty rows left */ + /* Find next empty row. */ + next_empty_row = 0; + for (i = row + 1; i < slot_count && !next_empty_row; i++) { + if (!rows[i]) + next_empty_row = i; + } + if (!next_empty_row) + break; /* no empty rows left */ - /* Split the module into its own row and the next empty row. */ - spd_log("SPD: splitting row %d (%d MB) into %d and %d (%d MB each)\n", row, rows[row], row, next_empty_row, rows[row] >> 1); - rows[row] = rows[next_empty_row] = rows[row] >> 1; - split = 1; - break; - } + /* Split the module into its own row and the next empty row. */ + spd_log("SPD: splitting row %d (%d MB) into %d and %d (%d MB each)\n", row, rows[row], row, next_empty_row, rows[row] >> 1); + rows[row] = rows[next_empty_row] = rows[row] >> 1; + split = 1; + break; + } - /* Sort rows by descending capacity if any were split. */ - if (split) - qsort(rows, slot_count, sizeof(uint16_t), comp_ui16_rev); + /* Sort rows by descending capacity if any were split. */ + if (split) + qsort(rows, slot_count, sizeof(uint16_t), comp_ui16_rev); } } - static int spd_write_part_no(char *part_no, char *type, uint16_t size) { char size_unit; if (size >= 1024) { - size_unit = 'G'; - size >>= 10; + size_unit = 'G'; + size >>= 10; } else { - size_unit = 'M'; + size_unit = 'M'; } return sprintf(part_no, EMU_NAME "-%s-%03d%c", type, size, size_unit); } - void spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) { - uint8_t slot, slot_count, row, i; - uint16_t min_module_size, rows[SPD_MAX_SLOTS], asym; - spd_edo_t *edo_data; + uint8_t slot, slot_count, row, i; + uint16_t min_module_size, rows[SPD_MAX_SLOTS], asym; + spd_edo_t *edo_data; spd_sdram_t *sdram_data; /* Determine the minimum module size for this RAM type. */ switch (ram_type) { - case SPD_TYPE_FPM: - case SPD_TYPE_EDO: - min_module_size = SPD_MIN_SIZE_EDO; - break; + case SPD_TYPE_FPM: + case SPD_TYPE_EDO: + min_module_size = SPD_MIN_SIZE_EDO; + break; - case SPD_TYPE_SDRAM: - min_module_size = SPD_MIN_SIZE_SDRAM; - break; + case SPD_TYPE_SDRAM: + min_module_size = SPD_MIN_SIZE_SDRAM; + break; - default: - spd_log("SPD: unknown RAM type %02X\n", ram_type); - return; + default: + spd_log("SPD: unknown RAM type %02X\n", ram_type); + return; } /* Count how many slots are enabled. */ slot_count = 0; for (slot = 0; slot < SPD_MAX_SLOTS; slot++) { - rows[slot] = 0; - if (slot_mask & (1 << slot)) - slot_count++; + rows[slot] = 0; + if (slot_mask & (1 << slot)) + slot_count++; } /* Populate rows. */ @@ -221,372 +211,367 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size) /* Register SPD devices and populate their data according to the rows. */ row = 0; for (slot = 0; (slot < SPD_MAX_SLOTS) && rows[row]; slot++) { - if (!(slot_mask & (1 << slot))) - continue; /* slot disabled */ + if (!(slot_mask & (1 << slot))) + continue; /* slot disabled */ - spd_modules[slot] = (spd_t *) malloc(sizeof(spd_t)); - memset(spd_modules[slot], 0, sizeof(spd_t)); - spd_modules[slot]->slot = slot; - spd_modules[slot]->size = rows[row]; + spd_modules[slot] = (spd_t *) malloc(sizeof(spd_t)); + memset(spd_modules[slot], 0, sizeof(spd_t)); + spd_modules[slot]->slot = slot; + spd_modules[slot]->size = rows[row]; - /* Determine the second row size, from which the first row size can be obtained. */ - asym = rows[row] - (1 << log2i(rows[row])); /* separate the powers of 2 */ - if (!asym) /* is the module asymmetric? */ - asym = rows[row] >> 1; /* symmetric, therefore divide by 2 */ + /* Determine the second row size, from which the first row size can be obtained. */ + asym = rows[row] - (1 << log2i(rows[row])); /* separate the powers of 2 */ + if (!asym) /* is the module asymmetric? */ + asym = rows[row] >> 1; /* symmetric, therefore divide by 2 */ - spd_modules[slot]->row1 = rows[row] - asym; - spd_modules[slot]->row2 = asym; + spd_modules[slot]->row1 = rows[row] - asym; + spd_modules[slot]->row2 = asym; - spd_log("SPD: Registering slot %d = row %d = %d MB (%d/%d)\n", slot, row, rows[row], spd_modules[slot]->row1, spd_modules[slot]->row2); + spd_log("SPD: Registering slot %d = row %d = %d MB (%d/%d)\n", slot, row, rows[row], spd_modules[slot]->row1, spd_modules[slot]->row2); - switch (ram_type) { - case SPD_TYPE_FPM: - case SPD_TYPE_EDO: - edo_data = &spd_modules[slot]->edo_data; + switch (ram_type) { + case SPD_TYPE_FPM: + case SPD_TYPE_EDO: + edo_data = &spd_modules[slot]->edo_data; - /* EDO SPD is specified by JEDEC and present in some modules, but - most utilities cannot interpret it correctly. SIV32 at least gets - the module capacities right, so it was used as a reference here. */ - edo_data->bytes_used = 0x80; - edo_data->spd_size = 0x08; - edo_data->mem_type = ram_type; - edo_data->row_bits = SPD_ROLLUP(7 + log2i(spd_modules[slot]->row1)); /* first row */ - edo_data->col_bits = 9; - if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */ - edo_data->row_bits |= SPD_ROLLUP(7 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */ - edo_data->col_bits |= 9 << 4; /* same as first row, but just in case */ - } - edo_data->banks = 2; - edo_data->data_width_lsb = 64; - edo_data->signal_level = SPD_SIGNAL_LVTTL; - edo_data->trac = 50; - edo_data->tcac = 13; - edo_data->refresh_rate = SPD_REFRESH_NORMAL; - edo_data->dram_width = 8; + /* EDO SPD is specified by JEDEC and present in some modules, but + most utilities cannot interpret it correctly. SIV32 at least gets + the module capacities right, so it was used as a reference here. */ + edo_data->bytes_used = 0x80; + edo_data->spd_size = 0x08; + edo_data->mem_type = ram_type; + edo_data->row_bits = SPD_ROLLUP(7 + log2i(spd_modules[slot]->row1)); /* first row */ + edo_data->col_bits = 9; + if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */ + edo_data->row_bits |= SPD_ROLLUP(7 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */ + edo_data->col_bits |= 9 << 4; /* same as first row, but just in case */ + } + edo_data->banks = 2; + edo_data->data_width_lsb = 64; + edo_data->signal_level = SPD_SIGNAL_LVTTL; + edo_data->trac = 50; + edo_data->tcac = 13; + edo_data->refresh_rate = SPD_REFRESH_NORMAL; + edo_data->dram_width = 8; - edo_data->spd_rev = 0x12; - for (i = spd_write_part_no(edo_data->part_no, (ram_type == SPD_TYPE_FPM) ? "FPM" : "EDO", rows[row]); - i < sizeof(edo_data->part_no); i++) - edo_data->part_no[i] = ' '; /* part number should be space-padded */ - edo_data->rev_code[0] = BCD8(EMU_VERSION_MAJ); - edo_data->rev_code[1] = BCD8(EMU_VERSION_MIN); - edo_data->mfg_year = 20; - edo_data->mfg_week = 17; + edo_data->spd_rev = 0x12; + for (i = spd_write_part_no(edo_data->part_no, (ram_type == SPD_TYPE_FPM) ? "FPM" : "EDO", rows[row]); + i < sizeof(edo_data->part_no); i++) + edo_data->part_no[i] = ' '; /* part number should be space-padded */ + edo_data->rev_code[0] = BCD8(EMU_VERSION_MAJ); + edo_data->rev_code[1] = BCD8(EMU_VERSION_MIN); + edo_data->mfg_year = 20; + edo_data->mfg_week = 17; - for (i = 0; i < 63; i++) - edo_data->checksum += spd_modules[slot]->data[i]; - for (i = 0; i < 129; i++) - edo_data->checksum2 += spd_modules[slot]->data[i]; - break; + for (i = 0; i < 63; i++) + edo_data->checksum += spd_modules[slot]->data[i]; + for (i = 0; i < 129; i++) + edo_data->checksum2 += spd_modules[slot]->data[i]; + break; - case SPD_TYPE_SDRAM: - sdram_data = &spd_modules[slot]->sdram_data; + case SPD_TYPE_SDRAM: + sdram_data = &spd_modules[slot]->sdram_data; - sdram_data->bytes_used = 0x80; - sdram_data->spd_size = 0x08; - sdram_data->mem_type = ram_type; - sdram_data->row_bits = SPD_ROLLUP(6 + log2i(spd_modules[slot]->row1)); /* first row */ - sdram_data->col_bits = 9; - if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */ - sdram_data->row_bits |= SPD_ROLLUP(6 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */ - sdram_data->col_bits |= 9 << 4; /* same as first row, but just in case */ - } - sdram_data->rows = 2; - sdram_data->data_width_lsb = 64; - sdram_data->signal_level = SPD_SIGNAL_LVTTL; - sdram_data->tclk = 0x75; /* 7.5 ns = 133.3 MHz */ - sdram_data->tac = 0x10; - sdram_data->refresh_rate = SPD_SDR_REFRESH_SELF | SPD_REFRESH_NORMAL; - sdram_data->sdram_width = 8; - sdram_data->tccd = 1; - sdram_data->burst = SPD_SDR_BURST_PAGE | 1 | 2 | 4 | 8; - sdram_data->banks = 4; - sdram_data->cas = 0x1c; /* CAS 5/4/3 supported */ - sdram_data->cslat = sdram_data->we = 0x7f; - sdram_data->dev_attr = SPD_SDR_ATTR_EARLY_RAS | SPD_SDR_ATTR_AUTO_PC | SPD_SDR_ATTR_PC_ALL | SPD_SDR_ATTR_W1R_BURST; - sdram_data->tclk2 = 0xA0; /* 10 ns = 100 MHz */ - sdram_data->tclk3 = 0xF0; /* 15 ns = 66.7 MHz */ - sdram_data->tac2 = sdram_data->tac3 = 0x10; - sdram_data->trp = sdram_data->trrd = sdram_data->trcd = sdram_data->tras = 1; - if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { - /* Utilities interpret bank_density a bit differently on asymmetric modules. */ - sdram_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 2); /* first row */ - sdram_data->bank_density |= 1 << (log2i(spd_modules[slot]->row2 >> 1) - 2); /* second row */ - } else { - sdram_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 1); /* symmetric module = only one bit is set */ - } - sdram_data->ca_setup = sdram_data->data_setup = 0x15; - sdram_data->ca_hold = sdram_data->data_hold = 0x08; + sdram_data->bytes_used = 0x80; + sdram_data->spd_size = 0x08; + sdram_data->mem_type = ram_type; + sdram_data->row_bits = SPD_ROLLUP(6 + log2i(spd_modules[slot]->row1)); /* first row */ + sdram_data->col_bits = 9; + if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */ + sdram_data->row_bits |= SPD_ROLLUP(6 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */ + sdram_data->col_bits |= 9 << 4; /* same as first row, but just in case */ + } + sdram_data->rows = 2; + sdram_data->data_width_lsb = 64; + sdram_data->signal_level = SPD_SIGNAL_LVTTL; + sdram_data->tclk = 0x75; /* 7.5 ns = 133.3 MHz */ + sdram_data->tac = 0x10; + sdram_data->refresh_rate = SPD_SDR_REFRESH_SELF | SPD_REFRESH_NORMAL; + sdram_data->sdram_width = 8; + sdram_data->tccd = 1; + sdram_data->burst = SPD_SDR_BURST_PAGE | 1 | 2 | 4 | 8; + sdram_data->banks = 4; + sdram_data->cas = 0x1c; /* CAS 5/4/3 supported */ + sdram_data->cslat = sdram_data->we = 0x7f; + sdram_data->dev_attr = SPD_SDR_ATTR_EARLY_RAS | SPD_SDR_ATTR_AUTO_PC | SPD_SDR_ATTR_PC_ALL | SPD_SDR_ATTR_W1R_BURST; + sdram_data->tclk2 = 0xA0; /* 10 ns = 100 MHz */ + sdram_data->tclk3 = 0xF0; /* 15 ns = 66.7 MHz */ + sdram_data->tac2 = sdram_data->tac3 = 0x10; + sdram_data->trp = sdram_data->trrd = sdram_data->trcd = sdram_data->tras = 1; + if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { + /* Utilities interpret bank_density a bit differently on asymmetric modules. */ + sdram_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 2); /* first row */ + sdram_data->bank_density |= 1 << (log2i(spd_modules[slot]->row2 >> 1) - 2); /* second row */ + } else { + sdram_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 1); /* symmetric module = only one bit is set */ + } + sdram_data->ca_setup = sdram_data->data_setup = 0x15; + sdram_data->ca_hold = sdram_data->data_hold = 0x08; - sdram_data->spd_rev = 0x12; - for (i = spd_write_part_no(sdram_data->part_no, "SDR", rows[row]); - i < sizeof(sdram_data->part_no); i++) - sdram_data->part_no[i] = ' '; /* part number should be space-padded */ - sdram_data->rev_code[0] = BCD8(EMU_VERSION_MAJ); - sdram_data->rev_code[1] = BCD8(EMU_VERSION_MIN); - sdram_data->mfg_year = 20; - sdram_data->mfg_week = 13; + sdram_data->spd_rev = 0x12; + for (i = spd_write_part_no(sdram_data->part_no, "SDR", rows[row]); + i < sizeof(sdram_data->part_no); i++) + sdram_data->part_no[i] = ' '; /* part number should be space-padded */ + sdram_data->rev_code[0] = BCD8(EMU_VERSION_MAJ); + sdram_data->rev_code[1] = BCD8(EMU_VERSION_MIN); + sdram_data->mfg_year = 20; + sdram_data->mfg_week = 13; - sdram_data->freq = 100; - sdram_data->features = 0xFF; + sdram_data->freq = 100; + sdram_data->features = 0xFF; - for (i = 0; i < 63; i++) - sdram_data->checksum += spd_modules[slot]->data[i]; - for (i = 0; i < 129; i++) - sdram_data->checksum2 += spd_modules[slot]->data[i]; - break; - } + for (i = 0; i < 63; i++) + sdram_data->checksum += spd_modules[slot]->data[i]; + for (i = 0; i < 129; i++) + sdram_data->checksum2 += spd_modules[slot]->data[i]; + break; + } - row++; + row++; } device_add(&spd_device); } - void spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit) { - uint8_t row, dimm, drb, apollo = 0; + uint8_t row, dimm, drb, apollo = 0; uint16_t size, rows[SPD_MAX_SLOTS]; /* Special case for VIA Apollo Pro family, which jumps from 5F to 56. */ if (reg_max < reg_min) { - apollo = reg_max; - reg_max = reg_min + 7; + apollo = reg_max; + reg_max = reg_min + 7; } /* No SPD: split SIMMs into pairs as if they were "DIMM"s. */ if (!spd_present) { - dimm = ((reg_max - reg_min) + 1) >> 1; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */ - spd_populate(rows, dimm, mem_size >> 10, drb_unit, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0); + dimm = ((reg_max - reg_min) + 1) >> 1; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */ + spd_populate(rows, dimm, mem_size >> 10, drb_unit, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0); } /* Write DRBs for each row. */ spd_log("SPD: Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit); for (row = 0; row <= (reg_max - reg_min); row++) { - dimm = (row >> 1); - size = 0; + dimm = (row >> 1); + size = 0; - if (spd_present) { - /* SPD enabled: use SPD info for this slot, if present. */ - if (spd_modules[dimm]) { - if (spd_modules[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */ - size = (row & 1) ? 0 : drb_unit; - else - size = (row & 1) ? spd_modules[dimm]->row2 : spd_modules[dimm]->row1; - } - } else { - /* No SPD: use the values calculated above. */ - size = (rows[dimm] >> 1); - } + if (spd_present) { + /* SPD enabled: use SPD info for this slot, if present. */ + if (spd_modules[dimm]) { + if (spd_modules[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */ + size = (row & 1) ? 0 : drb_unit; + else + size = (row & 1) ? spd_modules[dimm]->row2 : spd_modules[dimm]->row1; + } + } else { + /* No SPD: use the values calculated above. */ + size = (rows[dimm] >> 1); + } - /* Determine the DRB register to write. */ - drb = reg_min + row; - if (apollo && ((drb & 0xf) < 0xa)) - drb = apollo + (drb & 0xf); + /* Determine the DRB register to write. */ + drb = reg_min + row; + if (apollo && ((drb & 0xf) < 0xa)) + drb = apollo + (drb & 0xf); - /* Write DRB register, adding the previous DRB's value. */ - if (row == 0) - regs[drb] = 0; - else if ((apollo) && (drb == apollo)) - regs[drb] = regs[drb | 0xf]; /* 5F comes before 56 */ - else - regs[drb] = regs[drb - 1]; - if (size) - regs[drb] += size / drb_unit; /* this will intentionally overflow on 440GX with 2 GB */ - spd_log("SPD: DRB[%d] = %d MB (%02Xh raw)\n", row, size, regs[drb]); + /* Write DRB register, adding the previous DRB's value. */ + if (row == 0) + regs[drb] = 0; + else if ((apollo) && (drb == apollo)) + regs[drb] = regs[drb | 0xf]; /* 5F comes before 56 */ + else + regs[drb] = regs[drb - 1]; + if (size) + regs[drb] += size / drb_unit; /* this will intentionally overflow on 440GX with 2 GB */ + spd_log("SPD: DRB[%d] = %d MB (%02Xh raw)\n", row, size, regs[drb]); } } - /* Needed for 430LX. */ void spd_write_drbs_with_ext(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit) { - uint8_t row, dimm, drb; + uint8_t row, dimm, drb; uint16_t size, row_val = 0, rows[SPD_MAX_SLOTS]; - int shift; + int shift; /* No SPD: split SIMMs into pairs as if they were "DIMM"s. */ if (!spd_present) { - dimm = ((reg_max - reg_min) + 1) >> 1; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */ - spd_populate(rows, dimm, mem_size >> 10, drb_unit, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0); + dimm = ((reg_max - reg_min) + 1) >> 1; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */ + spd_populate(rows, dimm, mem_size >> 10, drb_unit, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0); } /* Write DRBs for each row. */ spd_log("SPD: Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit); for (row = 0; row <= (reg_max - reg_min); row++) { - dimm = (row >> 1); - size = 0; + dimm = (row >> 1); + size = 0; - if (spd_present) { - /* SPD enabled: use SPD info for this slot, if present. */ - if (spd_modules[dimm]) { - if (spd_modules[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */ - size = (row & 1) ? 0 : drb_unit; - else - size = (row & 1) ? spd_modules[dimm]->row2 : spd_modules[dimm]->row1; - } - } else { - /* No SPD: use the values calculated above. */ - size = (rows[dimm] >> 1); - } + if (spd_present) { + /* SPD enabled: use SPD info for this slot, if present. */ + if (spd_modules[dimm]) { + if (spd_modules[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */ + size = (row & 1) ? 0 : drb_unit; + else + size = (row & 1) ? spd_modules[dimm]->row2 : spd_modules[dimm]->row1; + } + } else { + /* No SPD: use the values calculated above. */ + size = (rows[dimm] >> 1); + } - /* Determine the DRB register to write. */ - drb = reg_min + row; + /* Determine the DRB register to write. */ + drb = reg_min + row; - /* Write DRB register, adding the previous DRB's value. */ - if (row == 0) - row_val = 0; - if (size) - row_val += size / drb_unit; /* this will intentionally overflow on 440GX with 2 GB */ - regs[drb] = row_val & 0xff; - drb = reg_min + 8 + (row >> 1); - shift = (row & 0x01) << 3; - regs[drb] = (((row_val & 0xfff) >> 8) << shift); - spd_log("SPD: DRB[%d] = %d MB (%02Xh raw)\n", row, size, regs[drb]); + /* Write DRB register, adding the previous DRB's value. */ + if (row == 0) + row_val = 0; + if (size) + row_val += size / drb_unit; /* this will intentionally overflow on 440GX with 2 GB */ + regs[drb] = row_val & 0xff; + drb = reg_min + 8 + (row >> 1); + shift = (row & 0x01) << 3; + regs[drb] = (((row_val & 0xfff) >> 8) << shift); + spd_log("SPD: DRB[%d] = %d MB (%02Xh raw)\n", row, size, regs[drb]); } } - /* Used by ALi M1531 and M1541/2. */ void spd_write_drbs_interleaved(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit) { - uint8_t row, dimm; - uint8_t drb; + uint8_t row, dimm; + uint8_t drb; uint16_t size, size_acc = 0; uint16_t rows[SPD_MAX_SLOTS]; /* No SPD: split SIMMs into pairs as if they were "DIMM"s. */ if (!spd_present) { - dimm = ((reg_max - reg_min) + 1) >> 2; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */ - spd_populate(rows, dimm, mem_size >> 10, drb_unit, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0); + dimm = ((reg_max - reg_min) + 1) >> 2; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */ + spd_populate(rows, dimm, mem_size >> 10, drb_unit, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0); } /* Write DRBs for each row. */ spd_log("SPD: Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit); for (row = 0; row <= (reg_max - reg_min); row += 2) { - dimm = (row >> 2); - size = 0; + dimm = (row >> 2); + size = 0; - if (spd_present) { - /* SPD enabled: use SPD info for this slot, if present. */ - if (spd_modules[dimm]) { - if (spd_modules[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */ - size = ((row >> 1) & 1) ? 0 : drb_unit; - else - size = ((row >> 1) & 1) ? spd_modules[dimm]->row2 : spd_modules[dimm]->row1; - } - } else { - /* No SPD: use the values calculated above. */ - size = (rows[dimm] >> 1); - } + if (spd_present) { + /* SPD enabled: use SPD info for this slot, if present. */ + if (spd_modules[dimm]) { + if (spd_modules[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */ + size = ((row >> 1) & 1) ? 0 : drb_unit; + else + size = ((row >> 1) & 1) ? spd_modules[dimm]->row2 : spd_modules[dimm]->row1; + } + } else { + /* No SPD: use the values calculated above. */ + size = (rows[dimm] >> 1); + } - /* Determine the DRB register to write. */ - drb = reg_min + row; + /* Determine the DRB register to write. */ + drb = reg_min + row; - /* Calculate previous and new size. */ - if (row == 0) - size_acc = 0; - else - size_acc += (size / drb_unit); + /* Calculate previous and new size. */ + if (row == 0) + size_acc = 0; + else + size_acc += (size / drb_unit); - /* Write DRB register, adding the previous DRB's value. */ - regs[drb] = size_acc & 0xff; - regs[drb + 1] = (regs[drb + 1] & 0xf0) | ((size_acc >> 8) & 0x0f); + /* Write DRB register, adding the previous DRB's value. */ + regs[drb] = size_acc & 0xff; + regs[drb + 1] = (regs[drb + 1] & 0xf0) | ((size_acc >> 8) & 0x0f); - spd_log("SPD: DRB[%d] = %d MB (%02Xh raw)\n", row >> 1, size, regs[drb]); + spd_log("SPD: DRB[%d] = %d MB (%02Xh raw)\n", row >> 1, size, regs[drb]); } } - /* This is needed because the ALi M1621 does this stuff completely differently, as it has DRAM bank registers instead of DRAM row boundary registers. */ void spd_write_drbs_ali1621(uint8_t *regs, uint8_t reg_min, uint8_t reg_max) { - uint8_t dimm, drb; + uint8_t dimm, drb; uint16_t size; uint16_t rows[SPD_MAX_SLOTS]; /* No SPD: split SIMMs into pairs as if they were "DIMM"s. */ if (!spd_present) { - dimm = ((reg_max - reg_min) + 1) >> 2; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */ - spd_populate(rows, dimm, mem_size >> 10, 4, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0); + dimm = ((reg_max - reg_min) + 1) >> 2; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */ + spd_populate(rows, dimm, mem_size >> 10, 4, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0); } /* Write DRBs for each row. */ spd_log("SPD: Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit); for (dimm = 0; dimm <= ((reg_max - reg_min) >> 2); dimm++) { - size = 0; - drb = reg_min + (dimm << 2); + size = 0; + drb = reg_min + (dimm << 2); - regs[drb] = 0xff; - regs[drb + 1] = 0xff; - regs[drb + 2] = 0x00; - regs[drb + 3] = 0xf0; + regs[drb] = 0xff; + regs[drb + 1] = 0xff; + regs[drb + 2] = 0x00; + regs[drb + 3] = 0xf0; - if (spd_modules[dimm] == NULL) - continue; + if (spd_modules[dimm] == NULL) + continue; - if (spd_present) { - /* SPD enabled: use SPD info for this slot, if present. */ - size = (spd_modules[dimm]->row1 + spd_modules[dimm]->row2) >> 1; - } else { - /* No SPD: use the values calculated above. */ - size = (rows[dimm] >> 1); - } + if (spd_present) { + /* SPD enabled: use SPD info for this slot, if present. */ + size = (spd_modules[dimm]->row1 + spd_modules[dimm]->row2) >> 1; + } else { + /* No SPD: use the values calculated above. */ + size = (rows[dimm] >> 1); + } - if (spd_modules[dimm]->row1) - regs[drb + 3] |= 0x06; + if (spd_modules[dimm]->row1) + regs[drb + 3] |= 0x06; - switch (size) { - case 4: - default: - regs[drb + 2] = 0x00; - break; - case 8: - regs[drb + 2] = 0x10; - break; - case 16: - regs[drb + 2] = 0x20; - break; - case 32: - regs[drb + 2] = 0x30; - break; - case 64: - regs[drb + 2] = 0x40; - break; - case 128: - regs[drb + 2] = 0x50; - break; - case 256: - regs[drb + 2] = 0x60; - break; - } + switch (size) { + case 4: + default: + regs[drb + 2] = 0x00; + break; + case 8: + regs[drb + 2] = 0x10; + break; + case 16: + regs[drb + 2] = 0x20; + break; + case 32: + regs[drb + 2] = 0x30; + break; + case 64: + regs[drb + 2] = 0x40; + break; + case 128: + regs[drb + 2] = 0x50; + break; + case 256: + regs[drb + 2] = 0x60; + break; + } - if (spd_modules[dimm]->row2) { - regs[drb + 3] |= 0x01; - regs[drb + 2] |= 0x80; - } + if (spd_modules[dimm]->row2) { + regs[drb + 3] |= 0x01; + regs[drb + 2] |= 0x80; + } - spd_log("SPD: DIMM %i: %02X %02X %02X %02X\n", regs[drb], regs[drb + 1], regs[drb + 2], regs[drb + 3]); + spd_log("SPD: DIMM %i: %02X %02X %02X %02X\n", regs[drb], regs[drb + 1], regs[drb + 2], regs[drb + 3]); } } - static const device_t spd_device = { - .name = "Serial Presence Detect ROMs", + .name = "Serial Presence Detect ROMs", .internal_name = "spd", - .flags = DEVICE_ISA, - .local = 0, - .init = spd_init, - .close = spd_close, - .reset = NULL, + .flags = DEVICE_ISA, + .local = 0, + .init = spd_init, + .close = spd_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/mem/sst_flash.c b/src/mem/sst_flash.c index 9aa0d4345..d94ca501b 100644 --- a/src/mem/sst_flash.c +++ b/src/mem/sst_flash.c @@ -32,62 +32,57 @@ #include <86box/plat.h> #include <86box/m_xt_xi8088.h> +typedef struct sst_t { + uint8_t manufacturer, id, has_bbp, is_39, + page_bytes, sdp, bbp_first_8k, bbp_last_8k; -typedef struct sst_t -{ - uint8_t manufacturer, id, has_bbp, is_39, - page_bytes, sdp, bbp_first_8k, bbp_last_8k; + int command_state, id_mode, + dirty; - int command_state, id_mode, - dirty; + uint32_t size, mask, + page_mask, page_base, + last_addr; - uint32_t size, mask, - page_mask, page_base, - last_addr; + uint8_t page_buffer[128], + page_dirty[128]; + uint8_t *array; - uint8_t page_buffer[128], - page_dirty[128]; - uint8_t *array; + mem_mapping_t mapping[8], mapping_h[8]; - mem_mapping_t mapping[8], mapping_h[8]; - - pc_timer_t page_write_timer; + pc_timer_t page_write_timer; } sst_t; +static char flash_path[1024]; -static char flash_path[1024]; +#define SST_CHIP_ERASE 0x10 /* Both 29 and 39, 6th cycle */ +#define SST_SDP_DISABLE 0x20 /* Only 29, Software data protect disable and write - treat as write */ +#define SST_SECTOR_ERASE 0x30 /* Only 39, 6th cycle */ +#define W_BOOT_BLOCK_PROT 0x40 /* Only W29C020 */ +#define SST_SET_ID_MODE_ALT 0x60 /* Only 29, 6th cycle */ +#define SST_ERASE 0x80 /* Both 29 and 39 */ + /* With data 60h on 6th cycle, it's alt. ID */ +#define SST_SET_ID_MODE 0x90 /* Both 29 and 39 */ +#define SST_BYTE_PROGRAM 0xa0 /* Both 29 and 39 */ +#define SST_CLEAR_ID_MODE 0xf0 /* Both 29 and 39 */ + /* 1st cycle variant only on 39 */ +#define SST 0xbf /* SST Manufacturer's ID */ +#define SST29EE010 0x0700 +#define SST29LE_VE010 0x0800 +#define SST29EE020 0x1000 +#define SST29LE_VE020 0x1200 +#define SST39SF512 0xb400 +#define SST39SF010 0xb500 +#define SST39SF020 0xb600 +#define SST39SF040 0xb700 -#define SST_CHIP_ERASE 0x10 /* Both 29 and 39, 6th cycle */ -#define SST_SDP_DISABLE 0x20 /* Only 29, Software data protect disable and write - treat as write */ -#define SST_SECTOR_ERASE 0x30 /* Only 39, 6th cycle */ -#define W_BOOT_BLOCK_PROT 0x40 /* Only W29C020 */ -#define SST_SET_ID_MODE_ALT 0x60 /* Only 29, 6th cycle */ -#define SST_ERASE 0x80 /* Both 29 and 39 */ - /* With data 60h on 6th cycle, it's alt. ID */ -#define SST_SET_ID_MODE 0x90 /* Both 29 and 39 */ -#define SST_BYTE_PROGRAM 0xa0 /* Both 29 and 39 */ -#define SST_CLEAR_ID_MODE 0xf0 /* Both 29 and 39 */ - /* 1st cycle variant only on 39 */ - -#define SST 0xbf /* SST Manufacturer's ID */ -#define SST29EE010 0x0700 -#define SST29LE_VE010 0x0800 -#define SST29EE020 0x1000 -#define SST29LE_VE020 0x1200 -#define SST39SF512 0xb400 -#define SST39SF010 0xb500 -#define SST39SF020 0xb600 -#define SST39SF040 0xb700 - -#define WINBOND 0xda /* Winbond Manufacturer's ID */ -#define W29C020 0x4500 - -#define SIZE_512K 0x010000 -#define SIZE_1M 0x020000 -#define SIZE_2M 0x040000 -#define SIZE_4M 0x080000 +#define WINBOND 0xda /* Winbond Manufacturer's ID */ +#define W29C020 0x4500 +#define SIZE_512K 0x010000 +#define SIZE_1M 0x020000 +#define SIZE_2M 0x040000 +#define SIZE_4M 0x080000 static void sst_sector_erase(sst_t *dev, uint32_t addr) @@ -95,330 +90,323 @@ sst_sector_erase(sst_t *dev, uint32_t addr) uint32_t base = addr & (dev->mask & ~0xfff); if ((base < 0x2000) && (dev->bbp_first_8k & 0x01)) - return; + return; else if ((base >= (dev->size - 0x2000)) && (dev->bbp_last_8k & 0x01)) - return; + return; memset(&dev->array[base], 0xff, 4096); dev->dirty = 1; } - static void sst_new_command(sst_t *dev, uint32_t addr, uint8_t val) { uint32_t base = 0x00000, size = dev->size; - if (dev->command_state == 5) switch (val) { - case SST_CHIP_ERASE: - if (dev->bbp_first_8k & 0x01) { - base += 0x2000; - size -= 0x2000; - } + if (dev->command_state == 5) + switch (val) { + case SST_CHIP_ERASE: + if (dev->bbp_first_8k & 0x01) { + base += 0x2000; + size -= 0x2000; + } - if (dev->bbp_last_8k & 0x01) - size -= 0x2000; + if (dev->bbp_last_8k & 0x01) + size -= 0x2000; - memset(&(dev->array[base]), 0xff, size); - dev->command_state = 0; - break; + memset(&(dev->array[base]), 0xff, size); + dev->command_state = 0; + break; - case SST_SDP_DISABLE: - if (!dev->is_39) - dev->sdp = 0; - dev->command_state = 0; - break; + case SST_SDP_DISABLE: + if (!dev->is_39) + dev->sdp = 0; + dev->command_state = 0; + break; - case SST_SECTOR_ERASE: - if (dev->is_39) - sst_sector_erase(dev, addr); - dev->command_state = 0; - break; + case SST_SECTOR_ERASE: + if (dev->is_39) + sst_sector_erase(dev, addr); + dev->command_state = 0; + break; - case SST_SET_ID_MODE_ALT: - dev->id_mode = 1; - dev->command_state = 0; - break; + case SST_SET_ID_MODE_ALT: + dev->id_mode = 1; + dev->command_state = 0; + break; - default: - dev->command_state = 0; - break; - } else switch (val) { - case SST_ERASE: - dev->command_state = 3; - break; + default: + dev->command_state = 0; + break; + } + else + switch (val) { + case SST_ERASE: + dev->command_state = 3; + break; - case SST_SET_ID_MODE: - dev->id_mode = 1; - dev->command_state = 0; - break; + case SST_SET_ID_MODE: + dev->id_mode = 1; + dev->command_state = 0; + break; - case SST_BYTE_PROGRAM: - if (!dev->is_39) { - dev->sdp = 1; - memset(dev->page_buffer, 0xff, 128); - memset(dev->page_dirty, 0x00, 128); - dev->page_bytes = 0; - dev->last_addr = 0xffffffff; - timer_on_auto(&dev->page_write_timer, 210.0); - } - dev->command_state = 6; - break; + case SST_BYTE_PROGRAM: + if (!dev->is_39) { + dev->sdp = 1; + memset(dev->page_buffer, 0xff, 128); + memset(dev->page_dirty, 0x00, 128); + dev->page_bytes = 0; + dev->last_addr = 0xffffffff; + timer_on_auto(&dev->page_write_timer, 210.0); + } + dev->command_state = 6; + break; - case W_BOOT_BLOCK_PROT: - dev->command_state = dev->has_bbp ? 8 : 0; - break; + case W_BOOT_BLOCK_PROT: + dev->command_state = dev->has_bbp ? 8 : 0; + break; - case SST_CLEAR_ID_MODE: - dev->id_mode = 0; - dev->command_state = 0; - break; + case SST_CLEAR_ID_MODE: + dev->id_mode = 0; + dev->command_state = 0; + break; - default: - dev->command_state = 0; - break; - } + default: + dev->command_state = 0; + break; + } } - static void sst_page_write(void *priv) { sst_t *dev = (sst_t *) priv; - int i; + int i; if (dev->last_addr != 0xffffffff) { - dev->page_base = dev->last_addr & dev->page_mask; - for (i = 0; i < 128; i++) { - if (dev->page_dirty[i]) { - if (((dev->page_base + i) < 0x2000) && (dev->bbp_first_8k & 0x01)) - continue; - else if (((dev->page_base + i) >= (dev->size - 0x2000)) && (dev->bbp_last_8k & 0x01)) - continue; + dev->page_base = dev->last_addr & dev->page_mask; + for (i = 0; i < 128; i++) { + if (dev->page_dirty[i]) { + if (((dev->page_base + i) < 0x2000) && (dev->bbp_first_8k & 0x01)) + continue; + else if (((dev->page_base + i) >= (dev->size - 0x2000)) && (dev->bbp_last_8k & 0x01)) + continue; - dev->array[dev->page_base + i] = dev->page_buffer[i]; - dev->dirty |= 1; - } - } + dev->array[dev->page_base + i] = dev->page_buffer[i]; + dev->dirty |= 1; + } + } } - dev->page_bytes = 0; + dev->page_bytes = 0; dev->command_state = 0; timer_disable(&dev->page_write_timer); } - static uint8_t sst_read_id(uint32_t addr, void *p) { - sst_t *dev = (sst_t *) p; + sst_t *dev = (sst_t *) p; uint8_t ret = 0x00; if ((addr & 0xffff) == 0) - ret = dev->manufacturer; + ret = dev->manufacturer; else if ((addr & 0xffff) == 1) - ret = dev->id; + ret = dev->id; #ifdef UNKNOWN_FLASH else if ((addr & 0xffff) == 0x100) - ret = 0x1c; + ret = 0x1c; else if ((addr & 0xffff) == 0x101) - ret = 0x92; + ret = 0x92; #endif else if (dev->has_bbp) { - if (addr == 0x00002) - ret = dev->bbp_first_8k; - else if (addr == 0x3fff2) - ret = dev->bbp_last_8k; + if (addr == 0x00002) + ret = dev->bbp_first_8k; + else if (addr == 0x3fff2) + ret = dev->bbp_last_8k; } return ret; } - static void sst_buf_write(sst_t *dev, uint32_t addr, uint8_t val) { dev->page_buffer[addr & 0x0000007f] = val; - dev->page_dirty[addr & 0x0000007f] = 1; + dev->page_dirty[addr & 0x0000007f] = 1; dev->page_bytes++; dev->last_addr = addr; if (dev->page_bytes >= 128) { - sst_page_write(dev); + sst_page_write(dev); } else - timer_on_auto(&dev->page_write_timer, 210.0); + timer_on_auto(&dev->page_write_timer, 210.0); } - static void sst_write(uint32_t addr, uint8_t val, void *p) { sst_t *dev = (sst_t *) p; switch (dev->command_state) { - case 0: - case 3: - /* 1st and 4th Bus Write Cycle */ - if ((val == 0xf0) && dev->is_39 && (dev->command_state == 0)) { - if (dev->id_mode) - dev->id_mode = 0; - dev->command_state = 0; - } else if (((addr & 0x7fff) == 0x5555) && (val == 0xaa)) - dev->command_state++; - else { - if (!dev->is_39 && !dev->sdp && (dev->command_state == 0)) { - /* 29 series, software data protection off, start loading the page. */ - memset(dev->page_buffer, 0xff, 128); - memset(dev->page_dirty, 0x00, 128); - dev->page_bytes = 0; - dev->command_state = 7; - sst_buf_write(dev, addr, val); - } else - dev->command_state = 0; - } - break; - case 1: - case 4: - /* 2nd and 5th Bus Write Cycle */ - if (((addr & 0x7fff) == 0x2aaa) && (val == 0x55)) - dev->command_state++; - else - dev->command_state = 0; - break; - case 2: - case 5: - /* 3rd and 6th Bus Write Cycle */ - if ((dev->command_state == 5) && (val == SST_SECTOR_ERASE)) { - /* Sector erase - can be on any address. */ - sst_new_command(dev, addr, val); - } else if ((addr & 0x7fff) == 0x5555) - sst_new_command(dev, addr, val); - else - dev->command_state = 0; - break; - case 6: - /* Page Load Cycle (29) / Data Write Cycle (39SF) */ - if (dev->is_39) { - dev->command_state = 0; + case 0: + case 3: + /* 1st and 4th Bus Write Cycle */ + if ((val == 0xf0) && dev->is_39 && (dev->command_state == 0)) { + if (dev->id_mode) + dev->id_mode = 0; + dev->command_state = 0; + } else if (((addr & 0x7fff) == 0x5555) && (val == 0xaa)) + dev->command_state++; + else { + if (!dev->is_39 && !dev->sdp && (dev->command_state == 0)) { + /* 29 series, software data protection off, start loading the page. */ + memset(dev->page_buffer, 0xff, 128); + memset(dev->page_dirty, 0x00, 128); + dev->page_bytes = 0; + dev->command_state = 7; + sst_buf_write(dev, addr, val); + } else + dev->command_state = 0; + } + break; + case 1: + case 4: + /* 2nd and 5th Bus Write Cycle */ + if (((addr & 0x7fff) == 0x2aaa) && (val == 0x55)) + dev->command_state++; + else + dev->command_state = 0; + break; + case 2: + case 5: + /* 3rd and 6th Bus Write Cycle */ + if ((dev->command_state == 5) && (val == SST_SECTOR_ERASE)) { + /* Sector erase - can be on any address. */ + sst_new_command(dev, addr, val); + } else if ((addr & 0x7fff) == 0x5555) + sst_new_command(dev, addr, val); + else + dev->command_state = 0; + break; + case 6: + /* Page Load Cycle (29) / Data Write Cycle (39SF) */ + if (dev->is_39) { + dev->command_state = 0; - dev->array[addr & dev->mask] = val; - dev->dirty = 1; - } else { - dev->command_state++; - sst_buf_write(dev, addr, val); - } - break; - case 7: - if (!dev->is_39) - sst_buf_write(dev, addr, val); - break; - case 8: - if ((addr == 0x00000) && (val == 0x00)) - dev->bbp_first_8k = 0xff; - else if ((addr == 0x3ffff) && (val == 0xff)) - dev->bbp_last_8k = 0xff; - dev->command_state = 0; - break; + dev->array[addr & dev->mask] = val; + dev->dirty = 1; + } else { + dev->command_state++; + sst_buf_write(dev, addr, val); + } + break; + case 7: + if (!dev->is_39) + sst_buf_write(dev, addr, val); + break; + case 8: + if ((addr == 0x00000) && (val == 0x00)) + dev->bbp_first_8k = 0xff; + else if ((addr == 0x3ffff) && (val == 0xff)) + dev->bbp_last_8k = 0xff; + dev->command_state = 0; + break; } } - static uint8_t sst_read(uint32_t addr, void *p) { - sst_t *dev = (sst_t *) p; + sst_t *dev = (sst_t *) p; uint8_t ret = 0xff; addr &= 0x000fffff; if (dev->id_mode) - ret = sst_read_id(addr, p); + ret = sst_read_id(addr, p); else { - if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) - ret = dev->array[addr - biosaddr]; + if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) + ret = dev->array[addr - biosaddr]; } return ret; } - static uint16_t sst_readw(uint32_t addr, void *p) { - sst_t *dev = (sst_t *) p; + sst_t *dev = (sst_t *) p; uint16_t ret = 0xffff; addr &= 0x000fffff; if (dev->id_mode) - ret = sst_read(addr, p) | (sst_read(addr + 1, p) << 8); + ret = sst_read(addr, p) | (sst_read(addr + 1, p) << 8); else { - if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) - ret = *(uint16_t *)&dev->array[addr - biosaddr]; + if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) + ret = *(uint16_t *) &dev->array[addr - biosaddr]; } return ret; } - static uint32_t sst_readl(uint32_t addr, void *p) { - sst_t *dev = (sst_t *) p; + sst_t *dev = (sst_t *) p; uint32_t ret = 0xffffffff; addr &= 0x000fffff; if (dev->id_mode) - ret = sst_readw(addr, p) | (sst_readw(addr + 2, p) << 16); + ret = sst_readw(addr, p) | (sst_readw(addr + 2, p) << 16); else { - if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) - ret = *(uint32_t *)&dev->array[addr - biosaddr]; + if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) + ret = *(uint32_t *) &dev->array[addr - biosaddr]; } return ret; } - static void sst_add_mappings(sst_t *dev) { - int i = 0, count; + int i = 0, count; uint32_t base, fbase; uint32_t root_base; - count = dev->size >> 16; + count = dev->size >> 16; root_base = 0x100000 - dev->size; for (i = 0; i < count; i++) { - base = root_base + (i << 16); - fbase = base & biosmask; + base = root_base + (i << 16); + fbase = base & biosmask; - memcpy(&dev->array[fbase], &rom[base & biosmask], 0x10000); + memcpy(&dev->array[fbase], &rom[base & biosmask], 0x10000); - if (base >= 0xe0000) { - mem_mapping_add(&(dev->mapping[i]), base, 0x10000, - sst_read, sst_readw, sst_readl, - sst_write, NULL, NULL, - dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, (void *) dev); - } - if (is6117) { - mem_mapping_add(&(dev->mapping_h[i]), (base | 0x3f00000), 0x10000, - sst_read, sst_readw, sst_readl, - sst_write, NULL, NULL, - dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, (void *) dev); - } else { - mem_mapping_add(&(dev->mapping_h[i]), (base | (cpu_16bitbus ? 0xf00000 : 0xfff00000)), 0x10000, - sst_read, sst_readw, sst_readl, - sst_write, NULL, NULL, - dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, (void *) dev); - } + if (base >= 0xe0000) { + mem_mapping_add(&(dev->mapping[i]), base, 0x10000, + sst_read, sst_readw, sst_readl, + sst_write, NULL, NULL, + dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev); + } + if (is6117) { + mem_mapping_add(&(dev->mapping_h[i]), (base | 0x3f00000), 0x10000, + sst_read, sst_readw, sst_readl, + sst_write, NULL, NULL, + dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev); + } else { + mem_mapping_add(&(dev->mapping_h[i]), (base | (cpu_16bitbus ? 0xf00000 : 0xfff00000)), 0x10000, + sst_read, sst_readw, sst_readl, + sst_write, NULL, NULL, + dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev); + } } } - static void * sst_init(const device_t *info) { - FILE *f; + FILE *f; sst_t *dev = malloc(sizeof(sst_t)); memset(dev, 0, sizeof(sst_t)); @@ -431,48 +419,47 @@ sst_init(const device_t *info) memset(dev->array, 0xff, biosmask + 1); dev->manufacturer = info->local & 0xff; - dev->id = (info->local >> 8) & 0xff; - dev->has_bbp = (dev->manufacturer == WINBOND) && ((info->local & 0xff00) >= W29C020); - dev->is_39 = (dev->manufacturer == SST) && ((info->local & 0xff00) >= SST39SF512); + dev->id = (info->local >> 8) & 0xff; + dev->has_bbp = (dev->manufacturer == WINBOND) && ((info->local & 0xff00) >= W29C020); + dev->is_39 = (dev->manufacturer == SST) && ((info->local & 0xff00) >= SST39SF512); dev->size = info->local & 0xffff0000; if ((dev->size == 0x20000) && (strstr(machine_get_internal_name_ex(machine), "xi8088")) && !xi8088_bios_128kb()) - dev->size = 0x10000; + dev->size = 0x10000; - dev->mask = dev->size - 1; - dev->page_mask = dev->mask & 0xffffff80; /* Filter out A0-A6. */ - dev->sdp = 1; + dev->mask = dev->size - 1; + dev->page_mask = dev->mask & 0xffffff80; /* Filter out A0-A6. */ + dev->sdp = 1; dev->bbp_first_8k = dev->bbp_last_8k = 0xfe; sst_add_mappings(dev); f = nvr_fopen(flash_path, "rb"); if (f) { - if (fread(&(dev->array[0x00000]), 1, dev->size, f) != dev->size) - pclog("Less than %i bytes read from the SST Flash ROM file\n", dev->size); - fclose(f); + if (fread(&(dev->array[0x00000]), 1, dev->size, f) != dev->size) + pclog("Less than %i bytes read from the SST Flash ROM file\n", dev->size); + fclose(f); } else - dev->dirty = 1; /* It is by definition dirty on creation. */ + dev->dirty = 1; /* It is by definition dirty on creation. */ if (!dev->is_39) - timer_add(&dev->page_write_timer, sst_page_write, dev, 0); + timer_add(&dev->page_write_timer, sst_page_write, dev, 0); return dev; } - static void sst_close(void *p) { - FILE *f; - sst_t *dev = (sst_t *)p; + FILE *f; + sst_t *dev = (sst_t *) p; if (dev->dirty) { - f = nvr_fopen(flash_path, "wb"); - if (f != NULL) { - fwrite(&(dev->array[0x00000]), dev->size, 1, f); - fclose(f); - } + f = nvr_fopen(flash_path, "wb"); + if (f != NULL) { + fwrite(&(dev->array[0x00000]), dev->size, 1, f); + fclose(f); + } } free(dev->array); @@ -482,85 +469,85 @@ sst_close(void *p) } const device_t sst_flash_29ee010_device = { - .name = "SST 29EE010 Flash BIOS", + .name = "SST 29EE010 Flash BIOS", .internal_name = "sst_flash_29ee010", - .flags = 0, - .local = SST | SST29EE010 | SIZE_1M, - .init = sst_init, - .close = sst_close, - .reset = NULL, + .flags = 0, + .local = SST | SST29EE010 | SIZE_1M, + .init = sst_init, + .close = sst_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t sst_flash_29ee020_device = { - .name = "SST 29EE020 Flash BIOS", + .name = "SST 29EE020 Flash BIOS", .internal_name = "sst_flash_29ee020", - .flags = 0, - .local = SST | SST29EE020 | SIZE_2M, - .init = sst_init, - .close = sst_close, - .reset = NULL, + .flags = 0, + .local = SST | SST29EE020 | SIZE_2M, + .init = sst_init, + .close = sst_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t winbond_flash_w29c020_device = { - .name = "Winbond W29C020 Flash BIOS", + .name = "Winbond W29C020 Flash BIOS", .internal_name = "winbond_flash_w29c020", - .flags = 0, - .local = WINBOND | W29C020 | SIZE_2M, - .init = sst_init, - .close = sst_close, - .reset = NULL, + .flags = 0, + .local = WINBOND | W29C020 | SIZE_2M, + .init = sst_init, + .close = sst_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t sst_flash_39sf010_device = { - .name = "SST 39SF010 Flash BIOS", + .name = "SST 39SF010 Flash BIOS", .internal_name = "sst_flash_39sf010", - .flags = 0, - .local = SST | SST39SF010 | SIZE_1M, - .init = sst_init, - .close = sst_close, - .reset = NULL, + .flags = 0, + .local = SST | SST39SF010 | SIZE_1M, + .init = sst_init, + .close = sst_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t sst_flash_39sf020_device = { - .name = "SST 39SF020 Flash BIOS", + .name = "SST 39SF020 Flash BIOS", .internal_name = "sst_flash_39sf020", - .flags = 0, - .local = SST | SST39SF020 | SIZE_2M, - .init = sst_init, - .close = sst_close, - .reset = NULL, + .flags = 0, + .local = SST | SST39SF020 | SIZE_2M, + .init = sst_init, + .close = sst_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t sst_flash_39sf040_device = { - .name = "SST 39SF040 Flash BIOS", + .name = "SST 39SF040 Flash BIOS", .internal_name = "sst_flash_39sf040", - .flags = 0, - .local = SST | SST39SF040 | SIZE_4M, - .init = sst_init, - .close = sst_close, - .reset = NULL, + .flags = 0, + .local = SST | SST39SF040 | SIZE_4M, + .init = sst_init, + .close = sst_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL };