From 474ab60c9748d1adb0789b1df52430eee953d23f Mon Sep 17 00:00:00 2001
From: Cacodemon345 <wahil1976@outlook.com>
Date: Mon, 5 Sep 2022 01:11:04 +0600
Subject: [PATCH] NEC TEST1 instruction (#4)

---
 src/cpu/808x.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/src/cpu/808x.c b/src/cpu/808x.c
index d8d10e37a..311c927dc 100644
--- a/src/cpu/808x.c
+++ b/src/cpu/808x.c
@@ -1716,7 +1716,7 @@ execx86(int cycs)
 					case 0x28: /* ROL4 r/m */
 					{
 						do_mod_rm();
-						wait(22, 0);
+						wait(21, 0);
 						{
 							uint8_t temp_val = geteab();
 							uint8_t temp_al = AL;
@@ -1735,7 +1735,7 @@ execx86(int cycs)
 					case 0x2a: /* ROR4 r/m */
 					{
 						do_mod_rm();
-						wait(22, 0);
+						wait(21, 0);
 						{
 							uint8_t temp_val = geteab();
 							uint8_t temp_al = AL;
@@ -1748,6 +1748,22 @@ execx86(int cycs)
 						handled = 1;
 						break;
 					}
+					case 0x10: /* TEST1 r8/m8, CL*/
+					case 0x11: /* TEST1 r16/m16, CL*/
+					case 0x18: /* TEST1 r8/m8, imm3 */
+					case 0x19: /* TEST1 r16/m16, imm4 */
+					{
+						bits = 8 << (opcode & 0x1);
+						do_mod_rm();
+						wait(3, 0);
+						{
+							uint8_t bit = (opcode & 0x8) ? (pfq_fetchb() & 0x7) : (CL & 0xF);
+							read_ea(0, bits);
+
+							set_zf_ex(!(cpu_data & (1 << bit)));
+							cpu_state.flags &= ~(V_FLAG | C_FLAG);
+						}
+					}
 					default: {
 						opcode = orig_opcode;
 						break;