Clean up 450KX formatting

src/chipset/intel_i450kx.c

@@ -32,14 +32,13 @@ i450GX is way more popular of an option but needs more stuff.
 #include <86box/timer.h>
 #include <86box/io.h>
 #include <86box/device.h>
-
 #include <86box/mem.h>
 #include <86box/pci.h>
 #include <86box/smram.h>
 #include <86box/spd.h>
-
 #include <86box/chipset.h>
 
+
 #ifdef ENABLE_450KX_LOG
 int i450kx_do_log = ENABLE_450KX_LOG;
 static void
@@ -58,6 +57,7 @@ i450kx_log(const char *fmt, ...)
 #define i450kx_log(fmt, ...)
 #endif
 
+
 /* Shadow RAM Flags */
 #define LSB_DECISION (((shadow_value & 1) ? MEM_READ_EXTANY : MEM_READ_INTERNAL) | ((shadow_value & 2) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL))
 #define MSB_DECISION (((shadow_value & 0x10) ? MEM_READ_EXTANY : MEM_READ_INTERNAL) | ((shadow_value & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL))
@@ -74,29 +74,30 @@ i450kx_log(const char *fmt, ...)
 #define ENABLE_SEGMENT (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
 #define DISABLE_SEGMENT (MEM_READ_DISABLED | MEM_WRITE_DISABLED)
 
-typedef struct i450kx_t
+
-{
+typedef struct i450kx_t {
     smram_t *smram;
 
     uint8_t pb_pci_conf[256], mc_pci_conf[256];
 } i450kx_t;
 
-void i450kx_shadow(int is_mc, int cur_reg, uint8_t shadow_value, i450kx_t *dev)
+
-{
+static void
-    if (cur_reg == 0x59)
+i450kx_shadow(int is_mc, int cur_reg, uint8_t shadow_value, i450kx_t *dev)
 {
+    if (cur_reg == 0x59) {
 	mem_set_mem_state_both(0x80000, 0x20000, (is_mc) ? LSB_DECISION_MC : LSB_DECISION);
 	mem_set_mem_state_both(0xf0000, 0x10000, (is_mc) ? MSB_DECISION_MC : MSB_DECISION);
-    }
+    } else {
-    else
-    {
 	mem_set_mem_state_both(0xc0000 + (((cur_reg & 7) - 2) * 0x8000), 0x4000, (is_mc) ? LSB_DECISION_MC : LSB_DECISION);
 	mem_set_mem_state_both(0xc4000 + (((cur_reg & 7) - 2) * 0x8000), 0x4000, (is_mc) ? MSB_DECISION_MC : MSB_DECISION);
     }
     flushmmucache_nopc();
 }
 
-void i450kx_smm(uint32_t smram_addr, uint32_t smram_size, i450kx_t *dev)
+
+static void
+i450kx_smm(uint32_t smram_addr, uint32_t smram_size, i450kx_t *dev)
 {
     smram_disable_all();
 
@@ -106,13 +107,13 @@ void i450kx_smm(uint32_t smram_addr, uint32_t smram_size, i450kx_t *dev)
     flushmmucache();
 }
 
+
 static void
 pb_write(int func, int addr, uint8_t val, void *priv)
 {
     i450kx_t *dev = (i450kx_t *)priv;
 
-    switch (addr)
+    switch (addr) {
-    {
 	case 0x04:
 		dev->pb_pci_conf[addr] &= val & 0xd7;
 		break;
@@ -288,6 +289,7 @@ pb_write(int func, int addr, uint8_t val, void *priv)
     i450kx_log("i450KX-PB: dev->regs[%02x] = %02x POST: %02x\n", addr, dev->pb_pci_conf[addr], inb(0x80));
 }
 
+
 static uint8_t
 pb_read(int func, int addr, void *priv)
 {
@@ -295,6 +297,7 @@ pb_read(int func, int addr, void *priv)
     return dev->pb_pci_conf[addr];
 }
 
+
 static void
 mc_write(int func, int addr, uint8_t val, void *priv)
 {
@@ -467,6 +470,7 @@ mc_write(int func, int addr, uint8_t val, void *priv)
     i450kx_log("i450KX-MC: dev->regs[%02x] = %02x POST: %02x\n", addr, dev->mc_pci_conf[addr], inb(0x80));
 }
 
+
 static uint8_t
 mc_read(int func, int addr, void *priv)
 {
@@ -474,6 +478,7 @@ mc_read(int func, int addr, void *priv)
     return dev->mc_pci_conf[addr];
 }
 
+
 static void
 i450kx_reset(void *priv)
 {
@@ -531,6 +536,7 @@ i450kx_reset(void *priv)
     dev->mc_pci_conf[0xbc] = 1;
 }
 
+
 static void
 i450kx_close(void *priv)
 {
@@ -540,13 +546,14 @@ i450kx_close(void *priv)
     free(dev);
 }
 
+
 static void *
 i450kx_init(const device_t *info)
 {
     i450kx_t *dev = (i450kx_t *)malloc(sizeof(i450kx_t));
     memset(dev, 0, sizeof(i450kx_t));
     pci_add_card(PCI_ADD_NORTHBRIDGE, pb_read, pb_write, dev); /* Device 19: Intel 450KX PCI Bridge PB */
-    pci_add_card(PCI_ADD_SOUTHBRIDGE, mc_read, mc_write, dev); /* Device 14: Intel 450KX Memory Controller MC */
+    pci_add_card(PCI_ADD_NORTHBRIDGE, mc_read, mc_write, dev); /* Device 14: Intel 450KX Memory Controller MC */
 
     dev->smram = smram_add();
 
@@ -559,6 +566,7 @@ i450kx_init(const device_t *info)
     return dev;
 }
 
+
 const device_t i450kx_device = {
     "Intel 450KX (Mars)",
     DEVICE_PCI,
@@ -569,4 +577,5 @@ const device_t i450kx_device = {
     { NULL },
     NULL,
     NULL,
-    NULL};
+    NULL
+};

src/machine/m_at_socket8.c

@@ -53,7 +53,7 @@ machine_at_p6rp4_init(const machine_t *model)
 
     pci_init(PCI_CONFIG_TYPE_1);
     pci_register_slot(0x19, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
-    pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
+    pci_register_slot(0x12, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
     pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
     pci_register_slot(0x07, PCI_CARD_NORMAL, 1, 2, 3, 4);
     pci_register_slot(0x06, PCI_CARD_NORMAL, 2, 3, 4, 1);