From 4fe7ee9675d2c6936597442ed8c0a0576cee4336 Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 8 May 2024 23:44:43 +0200 Subject: [PATCH] Added a PC Partner MB500N specific workaround to the i4x0 cache control register write. --- src/chipset/intel_4x0.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index 8abbe50c1..26a973be0 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -518,7 +518,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430FX: case INTEL_430VX: case INTEL_430TX: - regs[0x52] = (regs[0x52] & 0xf0) | (val & 0x0b); + if (!strcmp(machine_get_internal_name(), "mb500n")) + regs[0x52] = val; + else + regs[0x52] = (regs[0x52] & 0xf4) | (val & 0x0b); cpu_cache_ext_enabled = ((val & 0x03) == 0x01); cpu_update_waitstates(); break;