diff --git a/src/cpu_common/808x.c b/src/cpu_common/808x.c index abee70e26..28a96a73b 100644 --- a/src/cpu_common/808x.c +++ b/src/cpu_common/808x.c @@ -918,14 +918,11 @@ reset_common(int hard) stack32 = 0; msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21); msw = 0; - if (is486) + if (hascache) cr0 = 1 << 30; else cr0 = 0; - if (isibmcpu) - cpu_cache_int_enabled = 1; - else - cpu_cache_int_enabled = 0; + cpu_cache_int_enabled = 0; cpu_update_waitstates(); cr4 = 0; cpu_state.eflags = 0; diff --git a/src/cpu_common/cpu.c b/src/cpu_common/cpu.c index 1cd856236..3727fa857 100644 --- a/src/cpu_common/cpu.c +++ b/src/cpu_common/cpu.c @@ -159,7 +159,8 @@ int is286, is486 = 1, is486sx, is486dx, is486sx2, is486dx2, isdx4, cpu_iscyrix, - isibmcpu, + hascache, + isibm486, israpidcad, is_pentium; @@ -281,16 +282,17 @@ cpu_set(void) is8086 = (cpu_s->cpu_type > CPU_8088); is286 = (cpu_s->cpu_type >= CPU_286); is386 = (cpu_s->cpu_type >= CPU_386SX); - isibmcpu = (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL); israpidcad = (cpu_s->cpu_type == CPU_RAPIDCAD); - is486 = (cpu_s->cpu_type >= CPU_i486SX) || (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_RAPIDCAD || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL ); + isibm486 = (cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL); + is486 = (cpu_s->cpu_type >= CPU_i486SX) || (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_RAPIDCAD); is486sx = (cpu_s->cpu_type >= CPU_i486SX) && (cpu_s->cpu_type < CPU_i486SX2); is486sx2 = (cpu_s->cpu_type >= CPU_i486SX2) && (cpu_s->cpu_type < CPU_i486DX); is486dx = (cpu_s->cpu_type >= CPU_i486DX) && (cpu_s->cpu_type < CPU_i486DX2); - is486dx2 = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP); - isdx4 = (cpu_s->cpu_type >= CPU_i486DX2) && (cpu_s->cpu_type < CPU_iDX4); + is486dx2 = (cpu_s->cpu_type >= CPU_i486DX2) && (cpu_s->cpu_type < CPU_iDX4); + isdx4 = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP); is_pentium = (cpu_s->cpu_type >= CPU_WINCHIP); hasfpu = (cpu_s->cpu_type >= CPU_i486DX) || (cpu_s->cpu_type == CPU_RAPIDCAD); + hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL); #if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)) cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1); #else @@ -518,7 +520,13 @@ cpu_set(void) timing_jmp_pm = 23; timing_jmp_pm_gate = 38; break; - + + case CPU_IBM486SLC: +#ifdef USE_DYNAREC + x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); +#else + x86_setopcodes(ops_386, ops_486_0f); +#endif case CPU_IBM386SLC: case CPU_386SX: timing_rr = 2; /*register dest - register src*/ @@ -550,7 +558,13 @@ cpu_set(void) timing_jmp_pm = 27; timing_jmp_pm_gate = 45; break; - + + case CPU_IBM486BL: +#ifdef USE_DYNAREC + x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); +#else + x86_setopcodes(ops_386, ops_486_0f); +#endif case CPU_386DX: timing_rr = 2; /*register dest - register src*/ timing_rm = 6; /*register dest - memory src*/ @@ -582,80 +596,7 @@ cpu_set(void) timing_jmp_pm_gate = 45; break; - case CPU_IBM486SLC: -#ifdef USE_DYNAREC - x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); -#else - x86_setopcodes(ops_386, ops_486_0f); -#endif - timing_rr = 1; /*register dest - register src*/ - timing_rm = 2; /*register dest - memory src*/ - timing_mr = 5; /*memory dest - register src*/ - timing_mm = 3; - timing_rml = 4; /*register dest - memory src long*/ - timing_mrl = 5; /*memory dest - register src long*/ - timing_mml = 5; - timing_bt = 3-1; /*branch taken*/ - timing_bnt = 1; /*branch not taken*/ - timing_int = 4; - timing_int_rm = 26; - timing_int_v86 = 82; - timing_int_pm = 44; - timing_int_pm_outer = 71; - timing_iret_rm = 15; - timing_iret_v86 = 36; /*unknown*/ - timing_iret_pm = 20; - timing_iret_pm_outer = 36; - timing_call_rm = 18; - timing_call_pm = 20; - timing_call_pm_gate = 35; - timing_call_pm_gate_inner = 69; - timing_retf_rm = 13; - timing_retf_pm = 17; - timing_retf_pm_outer = 35; - timing_jmp_rm = 17; - timing_jmp_pm = 19; - timing_jmp_pm_gate = 32; - timing_misaligned = 3; - break; - - case CPU_IBM486BL: -#ifdef USE_DYNAREC - x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); -#else - x86_setopcodes(ops_386, ops_486_0f); -#endif - timing_rr = 1; /*register dest - register src*/ - timing_rm = 2; /*register dest - memory src*/ - timing_mr = 3; /*memory dest - register src*/ - timing_mm = 3; - timing_rml = 2; /*register dest - memory src long*/ - timing_mrl = 3; /*memory dest - register src long*/ - timing_mml = 3; - timing_bt = 3-1; /*branch taken*/ - timing_bnt = 1; /*branch not taken*/ - timing_int = 4; - timing_int_rm = 26; - timing_int_v86 = 82; - timing_int_pm = 44; - timing_int_pm_outer = 71; - timing_iret_rm = 15; - timing_iret_v86 = 36; /*unknown*/ - timing_iret_pm = 20; - timing_iret_pm_outer = 36; - timing_call_rm = 18; - timing_call_pm = 20; - timing_call_pm_gate = 35; - timing_call_pm_gate_inner = 69; - timing_retf_rm = 13; - timing_retf_pm = 17; - timing_retf_pm_outer = 35; - timing_jmp_rm = 17; - timing_jmp_pm = 19; - timing_jmp_pm_gate = 32; - timing_misaligned = 3; - break; - + case CPU_RAPIDCAD: #ifdef USE_DYNAREC x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); diff --git a/src/cpu_common/cpu.h b/src/cpu_common/cpu.h index 92a0cfe9f..636273b75 100644 --- a/src/cpu_common/cpu.h +++ b/src/cpu_common/cpu.h @@ -382,7 +382,8 @@ extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment penalties when crossing 8-byte boundaries*/ extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4; -extern int isibmcpu; +extern int hascache; +extern int isibm486; extern int is_rapidcad; extern int hasfpu; #define CPU_FEATURE_RDTSC (1 << 0) diff --git a/src/cpu_common/cpu_table.c b/src/cpu_common/cpu_table.c index f5f1dca4c..d13877db7 100644 --- a/src/cpu_common/cpu_table.c +++ b/src/cpu_common/cpu_table.c @@ -150,9 +150,9 @@ CPU cpus_i386DX[] = { {"i386DX/25", CPU_386DX, 25000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, {"i386DX/33", CPU_386DX, 33333333, 1, 0x0308, 0, 0, 0, 6,6,3,3, 4}, {"i386DX/40", CPU_386DX, 40000000, 1, 0x0308, 0, 0, 0, 7,7,3,3, 5}, - {"RapidCAD/25", CPU_RAPIDCAD, 25000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3}, - {"RapidCAD/33", CPU_RAPIDCAD, 33333333, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4}, - {"RapidCAD/40", CPU_RAPIDCAD, 40000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5}, + {"RapidCAD/25", CPU_RAPIDCAD, 25000000, 1, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3}, + {"RapidCAD/33", CPU_RAPIDCAD, 33333333, 1, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4}, + {"RapidCAD/40", CPU_RAPIDCAD, 40000000, 1, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5}, {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} }; @@ -187,30 +187,30 @@ CPU cpus_486SLC[] = { CPU cpus_IBM386SLC[] = { /*IBM 386SLC*/ - {"386SLC/16", CPU_IBM386SLC, 16000000, 1, 0x300, 0, 0, 0, 3,3,3,3, 2}, - {"386SLC/20", CPU_IBM386SLC, 20000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, - {"386SLC/25", CPU_IBM386SLC, 25000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, + {"386SLC/16", CPU_IBM386SLC, 16000000, 1, 0xA301, 0, 0, 0, 3,3,3,3, 2}, + {"386SLC/20", CPU_IBM386SLC, 20000000, 1, 0xA301, 0, 0, 0, 4,4,3,3, 3}, + {"386SLC/25", CPU_IBM386SLC, 25000000, 1, 0xA301, 0, 0, 0, 4,4,3,3, 3}, {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} }; CPU cpus_IBM486SLC[] = { /*IBM 486SLC*/ - {"486SLC/33", CPU_IBM486SLC, 33333333, 1, 0x400, 0, 0, 0, 6,6,3,3, 4}, - {"486SLC2/40", CPU_IBM486SLC, 40000000, 2, 0x400, 0, 0, 0, 7,7,6,6, 5}, - {"486SLC2/50", CPU_IBM486SLC, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, - {"486SLC2/66", CPU_IBM486SLC, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, - {"486SLC3/60", CPU_IBM486SLC, 60000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 7}, - {"486SLC3/75", CPU_IBM486SLC, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, - {"486SLC3/100", CPU_IBM486SLC, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, + {"486SLC/33", CPU_IBM486SLC, 33333333, 1, 0xA401, 0, 0, 0, 6,6,3,3, 4}, + {"486SLC2/40", CPU_IBM486SLC, 40000000, 2, 0xA421, 0, 0, 0, 7,7,6,6, 5}, + {"486SLC2/50", CPU_IBM486SLC, 50000000, 2, 0xA421, 0, 0, 0, 8,8,6,6, 6}, + {"486SLC2/66", CPU_IBM486SLC, 66666666, 2, 0xA421, 0, 0, 0, 12,12,6,6, 8}, + {"486SLC3/60", CPU_IBM486SLC, 60000000, 3, 0xA439, 0, 0, 0, 12,12,9,9, 7}, + {"486SLC3/75", CPU_IBM486SLC, 75000000, 3, 0xA439, 0, 0, 0, 12,12,9,9, 9}, + {"486SLC3/100", CPU_IBM486SLC, 100000000, 3, 0xA439, 0, 0, 0, 18,18,9,9, 12}, {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} }; CPU cpus_IBM486BL[] = { /*IBM Blue Lightning*/ - {"486BL2/50", CPU_IBM486BL, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, - {"486BL2/66", CPU_IBM486BL, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, - {"486BL3/75", CPU_IBM486BL, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, - {"486BL3/100", CPU_IBM486BL, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, + {"486BL2/50", CPU_IBM486BL, 50000000, 2, 0xA439, 0, 0, 0, 8,8,6,6, 6}, + {"486BL2/66", CPU_IBM486BL, 66666666, 2, 0xA439, 0, 0, 0, 12,12,6,6, 8}, + {"486BL3/75", CPU_IBM486BL, 75000000, 3, 0xA439, 0, 0, 0, 12,12,9,9, 9}, + {"486BL3/100", CPU_IBM486BL, 100000000, 3, 0xA439, 0, 0, 0, 18,18,9,9, 12}, {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} }; diff --git a/src/cpu_common/x86_ops_atomic.h b/src/cpu_common/x86_ops_atomic.h index 4011a0aa4..fca1c244a 100644 --- a/src/cpu_common/x86_ops_atomic.h +++ b/src/cpu_common/x86_ops_atomic.h @@ -1,12 +1,6 @@ static int opCMPXCHG_b_a16(uint32_t fetchdat) { uint8_t temp, temp2 = AL; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteab(); if (cpu_state.abrt) return 1; @@ -20,12 +14,6 @@ static int opCMPXCHG_b_a16(uint32_t fetchdat) static int opCMPXCHG_b_a32(uint32_t fetchdat) { uint8_t temp, temp2 = AL; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteab(); if (cpu_state.abrt) return 1; @@ -40,12 +28,6 @@ static int opCMPXCHG_b_a32(uint32_t fetchdat) static int opCMPXCHG_w_a16(uint32_t fetchdat) { uint16_t temp, temp2 = AX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteaw(); if (cpu_state.abrt) return 1; @@ -59,12 +41,6 @@ static int opCMPXCHG_w_a16(uint32_t fetchdat) static int opCMPXCHG_w_a32(uint32_t fetchdat) { uint16_t temp, temp2 = AX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteaw(); if (cpu_state.abrt) return 1; @@ -79,12 +55,6 @@ static int opCMPXCHG_w_a32(uint32_t fetchdat) static int opCMPXCHG_l_a16(uint32_t fetchdat) { uint32_t temp, temp2 = EAX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); if (cpu_state.abrt) return 1; @@ -98,12 +68,6 @@ static int opCMPXCHG_l_a16(uint32_t fetchdat) static int opCMPXCHG_l_a32(uint32_t fetchdat) { uint32_t temp, temp2 = EAX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); if (cpu_state.abrt) return 1; @@ -118,12 +82,6 @@ static int opCMPXCHG_l_a32(uint32_t fetchdat) static int opCMPXCHG8B_a16(uint32_t fetchdat) { uint32_t temp, temp_hi, temp2 = EAX, temp2_hi = EDX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 0; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); @@ -150,12 +108,6 @@ static int opCMPXCHG8B_a16(uint32_t fetchdat) static int opCMPXCHG8B_a32(uint32_t fetchdat) { uint32_t temp, temp_hi, temp2 = EAX, temp2_hi = EDX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 0; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); @@ -183,12 +135,6 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat) static int opXADD_b_a16(uint32_t fetchdat) { uint8_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteab(); if (cpu_state.abrt) return 1; @@ -201,12 +147,6 @@ static int opXADD_b_a16(uint32_t fetchdat) static int opXADD_b_a32(uint32_t fetchdat) { uint8_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteab(); if (cpu_state.abrt) return 1; @@ -220,12 +160,6 @@ static int opXADD_b_a32(uint32_t fetchdat) static int opXADD_w_a16(uint32_t fetchdat) { uint16_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteaw(); if (cpu_state.abrt) return 1; @@ -238,12 +172,6 @@ static int opXADD_w_a16(uint32_t fetchdat) static int opXADD_w_a32(uint32_t fetchdat) { uint16_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteaw(); if (cpu_state.abrt) return 1; @@ -257,12 +185,6 @@ static int opXADD_w_a32(uint32_t fetchdat) static int opXADD_l_a16(uint32_t fetchdat) { uint32_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); if (cpu_state.abrt) return 1; @@ -275,12 +197,6 @@ static int opXADD_l_a16(uint32_t fetchdat) static int opXADD_l_a32(uint32_t fetchdat) { uint32_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); if (cpu_state.abrt) return 1; diff --git a/src/cpu_common/x86_ops_flag.h b/src/cpu_common/x86_ops_flag.h index 099f2e35f..0d9db70a7 100644 --- a/src/cpu_common/x86_ops_flag.h +++ b/src/cpu_common/x86_ops_flag.h @@ -264,11 +264,11 @@ static int opPOPFD(uint32_t fetchdat) else if (IOPLp) cpu_state.flags = (cpu_state.flags & 0x3000) | (templ & 0x4fd5) | 2; else cpu_state.flags = (cpu_state.flags & 0x3200) | (templ & 0x4dd5) | 2; - templ &= is486 ? 0x3c0000 : 0; + templ &= (is486 || isibm486) ? 0x3c0000 : 0; templ |= ((cpu_state.eflags&3) << 16); if (cpu_CR4_mask & CR4_VME) cpu_state.eflags = (templ >> 16) & 0x3f; else if (CPUID) cpu_state.eflags = (templ >> 16) & 0x27; - else if (is486) cpu_state.eflags = (templ >> 16) & 7; + else if (is486 || isibm486) cpu_state.eflags = (templ >> 16) & 7; else cpu_state.eflags = (templ >> 16) & 3; flags_extract(); diff --git a/src/cpu_common/x86_ops_misc.h b/src/cpu_common/x86_ops_misc.h index 91118211b..91994785e 100644 --- a/src/cpu_common/x86_ops_misc.h +++ b/src/cpu_common/x86_ops_misc.h @@ -741,22 +741,12 @@ static int opCLTS(uint32_t fetchdat) static int opINVD(uint32_t fetchdat) { - if (!is486) - { - x86illegal(); - return 1; - } CLOCK_CYCLES(1000); CPU_BLOCK_END(); return 0; } static int opWBINVD(uint32_t fetchdat) { - if (!is486) - { - x86illegal(); - return 1; - } CLOCK_CYCLES(10000); CPU_BLOCK_END(); return 0; diff --git a/src/cpu_common/x86_ops_mov_ctrl.h b/src/cpu_common/x86_ops_mov_ctrl.h index 06a89884b..569fb4dce 100644 --- a/src/cpu_common/x86_ops_mov_ctrl.h +++ b/src/cpu_common/x86_ops_mov_ctrl.h @@ -10,7 +10,7 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat) { case 0: cpu_state.regs[cpu_rm].l = cr0; - if (is486) + if (is486 || isibm486) cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/ break; case 2: @@ -46,7 +46,7 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat) { case 0: cpu_state.regs[cpu_rm].l = cr0; - if (is486) + if (is486 || isibm486) cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/ break; case 2: @@ -118,13 +118,11 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat) cr0 |= 0x10; if (!(cr0 & 0x80000000)) mmu_perm=4; - if (is486 && !(cr0 & (1 << 30))) + if (hascache && !(cr0 & (1 << 30))) cpu_cache_int_enabled = 1; - else if (isibmcpu) - cpu_cache_int_enabled = 1; else cpu_cache_int_enabled = 0; - if (is486 && ((cr0 ^ old_cr0) & (1 << 30))) + if (hascache && ((cr0 ^ old_cr0) & (1 << 30))) cpu_update_waitstates(); if (cr0 & 1) cpu_cur_status |= CPU_STATUS_PMODE; @@ -174,11 +172,11 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat) cr0 |= 0x10; if (!(cr0 & 0x80000000)) mmu_perm=4; - if (is486 && !(cr0 & (1 << 30))) + if (hascache && !(cr0 & (1 << 30))) cpu_cache_int_enabled = 1; else cpu_cache_int_enabled = 0; - if (is486 && ((cr0 ^ old_cr0) & (1 << 30))) + if (hascache && ((cr0 ^ old_cr0) & (1 << 30))) cpu_update_waitstates(); if (cr0 & 1) cpu_cur_status |= CPU_STATUS_PMODE; diff --git a/src/cpu_common/x86_ops_pmode.h b/src/cpu_common/x86_ops_pmode.h index 7fe5d4938..26bdc3a11 100644 --- a/src/cpu_common/x86_ops_pmode.h +++ b/src/cpu_common/x86_ops_pmode.h @@ -370,7 +370,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32) case 0x20: /*SMSW*/ if (cpu_mod != 3) SEG_CHECK_WRITE(cpu_state.ea_seg); - if (is486) seteaw(msw); + if (is486 || isibm486) seteaw(msw); else if (is386) seteaw(msw | 0xFF00); else seteaw(msw | 0xFFF0); CLOCK_CYCLES(2); @@ -401,7 +401,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32) break; case 0x38: /*INVLPG*/ - if (is486) + if (is486 || isibm486) { if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1)) {