diff --git a/src/Makefile.mingw b/src/Makefile.mingw index ec298348f..ffe7582f5 100644 --- a/src/Makefile.mingw +++ b/src/Makefile.mingw @@ -49,5 +49,8 @@ clean : %.o : %.cc $(CPP) $(CFLAGS) -c $< +%.o : %.cpp + $(CPP) $(CFLAGS) -c $< + pc.res: pc.rc $(WINDRES) $(RFLAGS) -i pc.rc --input-format=rc -o pc.res -O coff diff --git a/src/Makefile.mingw64 b/src/Makefile.mingw64 index 389e2296e..56f114255 100644 --- a/src/Makefile.mingw64 +++ b/src/Makefile.mingw64 @@ -49,5 +49,8 @@ clean : %.o : %.cc $(CPP) $(CFLAGS) -c $< +%.o : %.cpp + $(CPP) $(CFLAGS) -c $< + pc.res: pc.rc $(WINDRES) $(RFLAGS) -i pc.rc --input-format=rc -o pc.res -O coff diff --git a/src/cpu.c b/src/cpu.c index 6db4457ab..fc811f532 100644 --- a/src/cpu.c +++ b/src/cpu.c @@ -1939,9 +1939,9 @@ void cpu_RDMSR() switch (ECX) { case 0x10: - EAX = tsc & 0xffffffff; - EDX = tsc >> 32; - break; + EAX = tsc & 0xffffffff; + EDX = tsc >> 32; + break; } break; case CPU_Cx6x86: @@ -2150,8 +2150,8 @@ void cpu_WRMSR() switch (ECX) { case 0x10: - tsc = EAX | ((uint64_t)EDX << 32); - break; + tsc = EAX | ((uint64_t)EDX << 32); + break; } break; case CPU_Cx6x86: diff --git a/src/disc.c b/src/disc.c index 8a273f463..b1401df7a 100644 --- a/src/disc.c +++ b/src/disc.c @@ -207,6 +207,9 @@ double disc_real_period(int drive) void disc_poll(int drive) { + disc_poll_time[drive] += (int) (((romset == ROM_MRTHOR) ? 16.0 : 32.0) * TIMER_USEC); + return; + if (drive >= FDD_NUM) { disc_poll_time[drive] += (int) (((romset == ROM_MRTHOR) ? 16.0 : 32.0) * TIMER_USEC); diff --git a/src/fdc.c b/src/fdc.c index e310d5e17..b3b61f7da 100644 --- a/src/fdc.c +++ b/src/fdc.c @@ -1,6 +1,7 @@ /* Copyright holders: Sarah Walker, Tenshi see COPYING for more details */ +#include #include #include #include "ibm.h" @@ -2165,9 +2166,9 @@ void fdc_indexpulse() // rfdc_log("c82c711_fdc_indexpulse\n"); } -void fdc_init() +void fdc_hard_reset() { - timer_add(fdc_callback, &disctime, &disctime, NULL); + memset(&fdc, 0, sizeof(FDC)); fdc.dskchg_activelow = 0; fdc.enable_3f1 = 1; @@ -2201,6 +2202,16 @@ void fdc_init() swwp = 0; disable_write = 0; + + disc_reset(); + fdc_reset(); +} + +void fdc_init() +{ + fdc_hard_reset(); + + timer_add(fdc_callback, &disctime, &disctime, NULL); } void fdc_add() diff --git a/src/fdc37c665.c b/src/fdc37c665.c index d076ae2cb..59e0bcb78 100644 --- a/src/fdc37c665.c +++ b/src/fdc37c665.c @@ -139,31 +139,30 @@ uint8_t fdc37c665_read(uint16_t port, void *priv) return 0xff; } -void fdc37c665_init() +void fdc37c665_reset(void) { - io_sethandler(0x03f0, 0x0002, fdc37c665_read, NULL, NULL, fdc37c665_write, NULL, NULL, NULL); - fdc_update_is_nsc(0); - fdc37c665_lock[0] = fdc37c665_lock[1] = 0; + memset(fdc37c665_lock, 0, 2); + memset(fdc37c665_regs, 0, 16); fdc37c665_regs[0x0] = 0x3b; fdc37c665_regs[0x1] = 0x9f; fdc37c665_regs[0x2] = 0xdc; fdc37c665_regs[0x3] = 0x78; - fdc37c665_regs[0x4] = 0x00; - fdc37c665_regs[0x5] = 0x00; fdc37c665_regs[0x6] = 0xff; - fdc37c665_regs[0x7] = 0x00; - fdc37c665_regs[0x8] = 0x00; - fdc37c665_regs[0x9] = 0x00; - fdc37c665_regs[0xa] = 0x00; - fdc37c665_regs[0xb] = 0x00; - fdc37c665_regs[0xc] = 0x00; fdc37c665_regs[0xd] = 0x65; fdc37c665_regs[0xe] = 0x01; - fdc37c665_regs[0xf] = 0x00; fdc_update_densel_polarity(1); fdc_update_densel_force(0); fdd_swap = 0; } + +void fdc37c665_init() +{ + io_sethandler(0x03f0, 0x0002, fdc37c665_read, NULL, NULL, fdc37c665_write, NULL, NULL, NULL); + + fdc37c665_reset(); + + pci_reset_handler.super_io_reset = fdc37c665_reset; +} diff --git a/src/fdc37c932fr.c b/src/fdc37c932fr.c index 68abfea5e..27385712a 100644 --- a/src/fdc37c932fr.c +++ b/src/fdc37c932fr.c @@ -393,12 +393,10 @@ uint8_t fdc37c932fr_read(uint16_t port, void *priv) } } -void fdc37c932fr_init() +void fdc37c932fr_reset(void) { int i = 0; - lpt2_remove(); - fdc37c932fr_regs[3] = 3; fdc37c932fr_regs[0x20] = 3; fdc37c932fr_regs[0x21] = 1; @@ -485,8 +483,19 @@ void fdc37c932fr_init() fdc_update_drvrate(2, 0); fdc_update_drvrate(3, 0); fdc_update_max_track(79); + + fdc37c932fr_locked = 0; +} + +void fdc37c932fr_init() +{ + lpt2_remove(); + + fdc37c932fr_reset(); + io_sethandler(0xe0, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL); io_sethandler(0xea, 0x0002, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL); io_sethandler(0x3f0, 0x0002, fdc37c932fr_read, NULL, NULL, fdc37c932fr_write, NULL, NULL, NULL); - fdc37c932fr_locked = 0; + + pci_reset_handler.super_io_reset = fdc37c932fr_reset; } diff --git a/src/i430fx.c b/src/i430fx.c index 9e4addfc6..34420f75f 100644 --- a/src/i430fx.c +++ b/src/i430fx.c @@ -102,27 +102,8 @@ uint8_t i430fx_read(int func, int addr, void *priv) return card_i430fx[addr]; } -/*The Turbo-Reset Control Register isn't listed in the i430FX datasheet, however - the Advanced/EV BIOS seems to assume it exists. It aliases with one of the PCI - registers.*/ -static uint8_t trc = 0; - -void i430fx_trc_write(uint16_t port, uint8_t val, void *p) +void i430fx_reset(void) { - if ((val & 4) && !(trc & 4)) - { - if (val & 2) /*Hard reset*/ - i430fx_write(0, 0x59, 0xf, NULL); /*Should reset all PCI devices, but just set PAM0 to point to ROM for now*/ - resetx86(); - } - - trc = val; -} - -void i430fx_init() -{ - pci_add_specific(0, i430fx_read, i430fx_write, NULL); - memset(card_i430fx, 0, 256); card_i430fx[0x00] = 0x86; card_i430fx[0x01] = 0x80; /*Intel*/ card_i430fx[0x02] = 0x22; card_i430fx[0x03] = 0x01; /*SB82437FX-66*/ @@ -138,8 +119,6 @@ void i430fx_init() card_i430fx[0x53] = 0x14; card_i430fx[0x56] = 0x52; /*DRAM control*/ } -// card_i430fx[0x53] = 0x14; -// card_i430fx[0x56] = 0x52; /*DRAM control*/ card_i430fx[0x57] = 0x01; card_i430fx[0x60] = card_i430fx[0x61] = card_i430fx[0x62] = card_i430fx[0x63] = card_i430fx[0x64] = 0x02; if (romset == ROM_MB500N) @@ -148,17 +127,24 @@ void i430fx_init() card_i430fx[0x69] = 0x03; card_i430fx[0x70] = 0x20; } -// card_i430fx[0x67] = 0x11; -// card_i430fx[0x69] = 0x03; -// card_i430fx[0x70] = 0x20; card_i430fx[0x72] = 0x02; -// card_i430fx[0x74] = 0x0e; -// card_i430fx[0x78] = 0x23; if (romset == ROM_MB500N) { card_i430fx[0x74] = 0x0e; card_i430fx[0x78] = 0x23; } - - if (romset != ROM_MB500N) io_sethandler(0x0cf9, 0x0001, NULL, NULL, NULL, i430fx_trc_write, NULL, NULL, NULL); +} + +void i430fx_pci_reset(void) +{ + i430fx_write(0, 0x59, 0xf, NULL); +} + +void i430fx_init() +{ + pci_add_specific(0, i430fx_read, i430fx_write, NULL); + + i430fx_reset(); + + pci_reset_handler.pci_master_reset = i430fx_pci_reset; } diff --git a/src/i430hx.c b/src/i430hx.c index 33f8e137d..8d20e98e4 100644 --- a/src/i430hx.c +++ b/src/i430hx.c @@ -103,11 +103,8 @@ uint8_t i430hx_read(int func, int addr, void *priv) return card_i430hx[addr]; } - -void i430hx_init() +void i430hx_reset(void) { - pci_add_specific(0, i430hx_read, i430hx_write, NULL); - memset(card_i430hx, 0, 256); card_i430hx[0x00] = 0x86; card_i430hx[0x01] = 0x80; /*Intel*/ card_i430hx[0x02] = 0x50; card_i430hx[0x03] = 0x12; /*82439HX*/ @@ -115,9 +112,7 @@ void i430hx_init() card_i430hx[0x06] = 0x00; card_i430hx[0x07] = 0x02; card_i430hx[0x08] = 0x00; /*A0 stepping*/ card_i430hx[0x09] = 0x00; card_i430hx[0x0a] = 0x00; card_i430hx[0x0b] = 0x06; - // card_i430hx[0x52] = 0x42; /*256kb PLB cache*/ card_i430hx[0x51] = 0x20; - // card_i430hx[0x52] = 0xB2; /*512kb cache*/ card_i430hx[0x52] = 0xB5; /*512kb cache*/ card_i430hx[0x59] = 0x40; @@ -129,3 +124,17 @@ void i430hx_init() card_i430hx[0x68] = 0x11; card_i430hx[0x72] = 0x02; } + +void i430hx_pci_reset(void) +{ + i430hx_write(0, 0x59, 0xf, NULL); +} + +void i430hx_init() +{ + pci_add_specific(0, i430hx_read, i430hx_write, NULL); + + i430hx_reset(); + + pci_reset_handler.pci_master_reset = i430hx_pci_reset; +} diff --git a/src/i430lx.c b/src/i430lx.c index 6a2d4a0ea..624d3f8d0 100644 --- a/src/i430lx.c +++ b/src/i430lx.c @@ -105,29 +105,8 @@ uint8_t i430lx_read(int func, int addr, void *priv) return card_i430lx[addr]; } -static uint8_t trc = 0; - -uint8_t i430lx_trc_read(uint16_t port, void *p) +void i430lx_reset(void) { - return trc; -} - -void i430lx_trc_write(uint16_t port, uint8_t val, void *p) -{ - if ((val & 4) && !(trc & 4)) - { - if (val & 2) /*Hard reset*/ - i430lx_write(0, 0x59, 0xf, NULL); /*Should reset all PCI devices, but just set PAM0 to point to ROM for now*/ - resetx86(); - } - - trc = val; -} - -void i430lx_init() -{ - pci_add_specific(0, i430lx_read, i430lx_write, NULL); - memset(card_i430lx, 0, 256); card_i430lx[0x00] = 0x86; card_i430lx[0x01] = 0x80; /*Intel*/ card_i430lx[0x02] = 0xa3; card_i430lx[0x03] = 0x04; /*82434LX*/ @@ -137,16 +116,20 @@ void i430lx_init() card_i430lx[0x09] = 0x00; card_i430lx[0x0a] = 0x00; card_i430lx[0x0b] = 0x06; card_i430lx[0x50] = 0x80; card_i430lx[0x52] = 0x40; /*256kb PLB cache*/ -// card_i430lx[0x53] = 0x14; -// card_i430lx[0x56] = 0x52; /*DRAM control*/ card_i430lx[0x57] = 0x31; card_i430lx[0x60] = card_i430lx[0x61] = card_i430lx[0x62] = card_i430lx[0x63] = card_i430lx[0x64] = 0x02; -// card_i430lx[0x67] = 0x11; -// card_i430lx[0x69] = 0x03; -// card_i430lx[0x70] = 0x20; -// card_i430lx[0x72] = 0x02; -// card_i430lx[0x74] = 0x0e; -// card_i430lx[0x78] = 0x23; - - io_sethandler(0x0cf9, 0x0001, i430lx_trc_read, NULL, NULL, i430lx_trc_write, NULL, NULL, NULL); +} + +void i430lx_pci_reset(void) +{ + i430lx_write(0, 0x59, 0xf, NULL); +} + +void i430lx_init() +{ + pci_add_specific(0, i430lx_read, i430lx_write, NULL); + + i430lx_reset(); + + pci_reset_handler.pci_master_reset = i430lx_pci_reset; } diff --git a/src/i430nx.c b/src/i430nx.c index 9b7ef653b..9b58d4000 100644 --- a/src/i430nx.c +++ b/src/i430nx.c @@ -102,29 +102,8 @@ uint8_t i430nx_read(int func, int addr, void *priv) return card_i430nx[addr]; } -static uint8_t trc = 0; - -uint8_t i430nx_trc_read(uint16_t port, void *p) +void i430nx_reset(void) { - return trc; -} - -void i430nx_trc_write(uint16_t port, uint8_t val, void *p) -{ - if ((val & 4) && !(trc & 4)) - { - if (val & 2) /*Hard reset*/ - i430nx_write(0, 0x59, 0xf, NULL); /*Should reset all PCI devices, but just set PAM0 to point to ROM for now*/ - resetx86(); - } - - trc = val; -} - -void i430nx_init() -{ - pci_add_specific(0, i430nx_read, i430nx_write, NULL); - memset(card_i430nx, 0, 256); card_i430nx[0x00] = 0x86; card_i430nx[0x01] = 0x80; /*Intel*/ card_i430nx[0x02] = 0xa3; card_i430nx[0x03] = 0x04; /*82434NX*/ @@ -134,17 +113,21 @@ void i430nx_init() card_i430nx[0x09] = 0x00; card_i430nx[0x0a] = 0x00; card_i430nx[0x0b] = 0x06; card_i430nx[0x50] = 0xA0; card_i430nx[0x52] = 0x44; /*256kb PLB cache*/ -// card_i430nx[0x53] = 0x14; -// card_i430nx[0x56] = 0x52; /*DRAM control*/ card_i430nx[0x57] = 0x31; card_i430nx[0x60] = card_i430nx[0x61] = card_i430nx[0x62] = card_i430nx[0x63] = card_i430nx[0x64] = 0x02; card_i430nx[0x66] = card_i430nx[0x67] = 0x02; -// card_i430nx[0x67] = 0x11; -// card_i430nx[0x69] = 0x03; -// card_i430nx[0x70] = 0x20; -// card_i430nx[0x72] = 0x02; -// card_i430nx[0x74] = 0x0e; -// card_i430nx[0x78] = 0x23; - - io_sethandler(0x0cf9, 0x0001, i430nx_trc_read, NULL, NULL, i430nx_trc_write, NULL, NULL, NULL); +} + +void i430nx_pci_reset(void) +{ + i430nx_write(0, 0x59, 0xf, NULL); +} + +void i430nx_init() +{ + pci_add_specific(0, i430nx_read, i430nx_write, NULL); + + i430nx_reset(); + + pci_reset_handler.pci_master_reset = i430nx_pci_reset; } diff --git a/src/i430vx.c b/src/i430vx.c index 487c1f977..ae9aec90e 100644 --- a/src/i430vx.c +++ b/src/i430vx.c @@ -103,11 +103,8 @@ uint8_t i430vx_read(int func, int addr, void *priv) return card_i430vx[addr]; } - -void i430vx_init() +void i430vx_reset(void) { - pci_add_specific(0, i430vx_read, i430vx_write, NULL); - memset(card_i430vx, 0, 256); card_i430vx[0x00] = 0x86; card_i430vx[0x01] = 0x80; /*Intel*/ card_i430vx[0x02] = 0x30; card_i430vx[0x03] = 0x70; /*82437VX*/ @@ -127,3 +124,17 @@ void i430vx_init() card_i430vx[0x74] = 0x0e; card_i430vx[0x78] = 0x23; } + +void i430vx_pci_reset(void) +{ + i430vx_write(0, 0x59, 0xf, NULL); +} + +void i430vx_init() +{ + pci_add_specific(0, i430vx_read, i430vx_write, NULL); + + i430vx_reset(); + + pci_reset_handler.pci_master_reset = i430vx_pci_reset; +} diff --git a/src/i440fx.c b/src/i440fx.c index 43889c0ec..3481adfab 100644 --- a/src/i440fx.c +++ b/src/i440fx.c @@ -103,11 +103,8 @@ uint8_t i440fx_read(int func, int addr, void *priv) return card_i440fx[addr]; } - -void i440fx_init() +void i440fx_reset(void) { - pci_add_specific(0, i440fx_read, i440fx_write, NULL); - memset(card_i440fx, 0, 256); card_i440fx[0x00] = 0x86; card_i440fx[0x01] = 0x80; /*Intel*/ card_i440fx[0x02] = 0x37; card_i440fx[0x03] = 0x12; /*82441FX*/ @@ -129,8 +126,19 @@ void i440fx_init() card_i440fx[0x58] = 0x10; card_i440fx[0x5a] = card_i440fx[0x5b] = card_i440fx[0x5c] = card_i440fx[0x5d] = card_i440fx[0x5e] = 0x11; card_i440fx[0x5f] = 0x31; - // card_i440fx[0x60] = card_i440fx[0x61] = card_i440fx[0x62] = card_i440fx[0x63] = card_i440fx[0x64] = card_i440fx[0x65] = card_i440fx[0x66] = card_i440fx[0x67] = 0x02; - // card_i440fx[0x70] = 0x20; - // card_i440fx[0x71] = 0x10; card_i440fx[0x72] = 0x02; } + +void i440fx_pci_reset(void) +{ + i440fx_write(0, 0x59, 0xf, NULL); +} + +void i440fx_init() +{ + pci_add_specific(0, i440fx_read, i440fx_write, NULL); + + i440fx_reset(); + + pci_reset_handler.pci_master_reset = i440fx_pci_reset; +} diff --git a/src/ibm.h b/src/ibm.h index 3f0ed78ee..726192285 100644 --- a/src/ibm.h +++ b/src/ibm.h @@ -610,3 +610,17 @@ extern int ne2000_do_log; #endif extern int suppress_overscan; + +typedef struct PCI_RESET +{ + void (*pci_master_reset)(void); + void (*pci_set_reset)(void); + void (*super_io_reset)(void); +} PCI_RESET; + +extern PCI_RESET pci_reset_handler; + +uint8_t trc_read(uint16_t port, void *priv); +void trc_write(uint16_t port, uint8_t val, void *priv); +void trc_init(); + diff --git a/src/io.c b/src/io.c index 4ec126c1d..6361e6afa 100644 --- a/src/io.c +++ b/src/io.c @@ -128,7 +128,7 @@ uint8_t inb(uint16_t port) temp &= port_inb[port][1](port, port_priv[port][1]); /* if (!port_inb[port][0] && !port_inb[port][1]) - pclog("Bad INB %04X %04X:%04X\n", port, CS, pc); */ + pclog("Bad INB %04X %04X:%04X\n", port, CS, cpu_state.pc); */ return temp; } @@ -143,7 +143,7 @@ void outb(uint16_t port, uint8_t val) port_outb[port][1](port, val, port_priv[port][1]); /* if (!port_outb[port][0] && !port_outb[port][1]) - pclog("Bad OUTB %04X %02X %04X:%08X\n", port, val, CS, pc); */ + pclog("Bad OUTB %04X %02X %04X:%08X\n", port, val, CS, cpu_state.pc); */ return; } diff --git a/src/mem.c b/src/mem.c index e79b54d6c..b9f3d6eec 100644 --- a/src/mem.c +++ b/src/mem.c @@ -677,7 +677,6 @@ int loadbios() biosmask = 0x1ffff; return 1; -#if 0 case ROM_POWERMATE_V: f = romfopen("roms/powermate_v/BIOS.ROM", "rb"); /* Works */ if (!f) break; @@ -685,7 +684,6 @@ int loadbios() fclose(f); biosmask = 0x1ffff; return 1; -#endif case ROM_P54TP4XE: f = romfopen("roms/p54tp4xe/T15I0302.AWD", "rb"); @@ -2115,7 +2113,7 @@ void mem_reset_page_blocks() } } -void mem_reset() +/* void mem_reset() { int c; @@ -2135,7 +2133,7 @@ void mem_reset() mem_a20_key = 2; mem_a20_recalc(); -} +} */ static int port_92_reg = 0; diff --git a/src/memregs.c b/src/memregs.c index 578f9e3d4..de269223d 100644 --- a/src/memregs.c +++ b/src/memregs.c @@ -13,14 +13,26 @@ static uint8_t mem_regs[2] = {0xFF, 0xFF}; +static uint8_t mem_reg_ffff = 0; + void memregs_write(uint16_t port, uint8_t val, void *priv) { - mem_regs[port - 0xE1] = val; + if (port == 0xffff) + { + mem_reg_ffff = 0; + } + + mem_regs[(port & 1) ^ 1] = val; } uint8_t memregs_read(uint16_t port, void *priv) { - return mem_regs[port - 0xE1]; + if (port == 0xffff) + { + return mem_reg_ffff; + } + + return mem_regs[(port & 1) ^ 1]; } void memregs_init() @@ -28,4 +40,12 @@ void memregs_init() pclog("Memory Registers Init\n"); io_sethandler(0x00e1, 0x0002, memregs_read, NULL, NULL, memregs_write, NULL, NULL, NULL); -} \ No newline at end of file +} + +void powermate_memregs_init() +{ + pclog("Memory Registers Init\n"); + + io_sethandler(0x00ed, 0x0002, memregs_read, NULL, NULL, memregs_write, NULL, NULL, NULL); + io_sethandler(0xffff, 0x0001, memregs_read, NULL, NULL, memregs_write, NULL, NULL, NULL); +} diff --git a/src/model.c b/src/model.c index a6e7dc8f4..2a33af2a5 100644 --- a/src/model.c +++ b/src/model.c @@ -101,9 +101,7 @@ void at_r418_init(); void at_586mc1_init(); void at_plato_init(); void at_mb500n_init(); -#if 0 void at_powermate_v_init(); -#endif void at_p54tp4xe_init(); void at_acerm3a_init(); void at_acerv35n_init(); @@ -117,6 +115,8 @@ int model; int AMSTRAD, AT, PCI, TANDY; +PCI_RESET pci_reset_handler; + MODEL models[] = { {"IBM PC", ROM_IBMPC, { "", cpus_8088, "", NULL, "", NULL}, 0, 0, 64, 640, 64, xt_init, NULL}, @@ -166,9 +166,7 @@ MODEL models[] = {"Intel Premiere/PCI II",ROM_PLATO, { "Intel", cpus_PentiumS5,"IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, MODEL_AT|MODEL_PS2, 1, 128, 1, at_plato_init, NULL}, {"Intel Advanced/EV", ROM_ENDEAVOR, { "Intel", cpus_PentiumS5,"IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, MODEL_AT|MODEL_PS2, 1, 128, 1, at_endeavor_init, NULL}, {"PC Partner MB500N", ROM_MB500N, { "Intel", cpus_PentiumS5,"IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, MODEL_AT|MODEL_PS2, 1, 128, 1, at_mb500n_init, NULL}, -#if 0 {"NEC PowerMate V", ROM_POWERMATE_V, { "Intel", cpus_PentiumS5,"IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, MODEL_AT|MODEL_PS2, 1, 128, 1, at_powermate_v_init, NULL}, -#endif {"Intel Advanced/ATX", ROM_THOR, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT|MODEL_PS2, 1, 256, 1, at_endeavor_init, NULL}, {"MR Intel Advanced/ATX", ROM_MRTHOR, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT|MODEL_PS2, 1, 256, 1, at_endeavor_init, NULL}, {"ASUS P/I-P54TP4XE", ROM_P54TP4XE, { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, MODEL_AT|MODEL_PS2, 1, 512, 1, at_p54tp4xe_init, NULL}, @@ -529,11 +527,10 @@ void at_mb500n_init() device_add(&intel_flash_bxt_device); } -#if 0 void at_powermate_v_init() { at_init(); - memregs_init(); + powermate_memregs_init(); pci_init(PCI_CONFIG_TYPE_1, 0, 31); i430fx_init(); piix_init(7); @@ -541,7 +538,6 @@ void at_powermate_v_init() acerm3a_io_init(); device_add(&intel_flash_bxt_device); } -#endif void at_p54tp4xe_init() { @@ -639,6 +635,9 @@ void model_init() AMSTRAD = AT = PCI = TANDY = 0; io_init(); + pci_reset_handler.pci_master_reset = NULL; + pci_reset_handler.pci_set_reset = NULL; + pci_reset_handler.super_io_reset = NULL; fdc_update_is_nsc(0); models[model].init(); if (models[model].device) diff --git a/src/nvr.c b/src/nvr.c index f5e632724..186e61f08 100644 --- a/src/nvr.c +++ b/src/nvr.c @@ -233,9 +233,7 @@ void loadnvr() case ROM_586MC1: f = romfopen(nvr_concat("586mc1.nvr"), "rb"); nvrmask = 127; break; case ROM_PLATO: f = romfopen(nvr_concat("plato.nvr"), "rb"); nvrmask = 127; break; case ROM_MB500N: f = romfopen(nvr_concat("mb500n.nvr"), "rb"); nvrmask = 127; break; -#if 0 case ROM_POWERMATE_V: f = romfopen(nvr_concat("powermate_v.nvr"), "rb"); nvrmask = 127; break; -#endif case ROM_P54TP4XE: f = romfopen(nvr_concat("p54tp4xe.nvr"), "rb"); nvrmask = 127; break; case ROM_ACERM3A: f = romfopen(nvr_concat("acerm3a.nvr"), "rb"); nvrmask = 127; break; case ROM_ACERV35N: f = romfopen(nvr_concat("acerv35n.nvr"), "rb"); nvrmask = 127; break; @@ -310,9 +308,7 @@ void savenvr() case ROM_586MC1: f = romfopen(nvr_concat("586mc1.nvr"), "wb"); break; case ROM_PLATO: f = romfopen(nvr_concat("plato.nvr"), "wb"); break; case ROM_MB500N: f = romfopen(nvr_concat("mb500n.nvr"), "wb"); break; -#if 0 case ROM_POWERMATE_V: f = romfopen(nvr_concat("powermate_v.nvr"), "wb"); break; -#endif case ROM_P54TP4XE: f = romfopen(nvr_concat("p54tp4xe.nvr"), "wb"); break; case ROM_ACERM3A: f = romfopen(nvr_concat("acerm3a.nvr"), "wb"); break; case ROM_ACERV35N: f = romfopen(nvr_concat("acerv35n.nvr"), "wb"); break; diff --git a/src/pc.c b/src/pc.c index 3067757bc..68f3a2ac0 100644 --- a/src/pc.c +++ b/src/pc.c @@ -40,6 +40,7 @@ #include "serial.h" #include "sound.h" #include "sound_cms.h" +#include "sound_dbopl.h" #include "sound_opl.h" #include "sound_sb.h" #include "sound_ssi2001.h" @@ -854,6 +855,7 @@ void loadconfig(char *fn) enable_flash = config_get_int(NULL, "enable_flash", 1); enable_sync = config_get_int(NULL, "enable_sync", 1); + opl3_type = config_get_int(NULL, "opl3_type", 1); window_w = config_get_int(NULL, "window_w", 0); window_h = config_get_int(NULL, "window_h", 0); @@ -1046,6 +1048,7 @@ void saveconfig() config_set_int(NULL, "enable_flash", enable_flash); config_set_int(NULL, "enable_sync", enable_sync); + config_set_int(NULL, "opl3_type", opl3_type); config_set_int(NULL, "joystick_type", joystick_type); config_set_int(NULL, "mouse_type", mouse_type); diff --git a/src/pc.rc b/src/pc.rc index 10067fd2d..da2ad821b 100644 --- a/src/pc.rc +++ b/src/pc.rc @@ -312,9 +312,12 @@ BEGIN POPUP "&Settings" BEGIN MENUITEM "&Configure...", IDM_CONFIG + MENUITEM SEPARATOR MENUITEM "&Load configuration...", IDM_CONFIG_LOAD MENUITEM "&Save configuration...", IDM_CONFIG_SAVE MENUITEM SEPARATOR + MENUITEM "Use &Nuked OPL for OPL 3...", IDM_USE_NUKEDOPL + MENUITEM SEPARATOR POPUP "&Video" BEGIN MENUITEM "&Resizeable window",IDM_VID_RESIZE diff --git a/src/pc87306.c b/src/pc87306.c index d10fb4844..ac1c2abdb 100644 --- a/src/pc87306.c +++ b/src/pc87306.c @@ -361,14 +361,11 @@ void pc87306_gpio_init() } } -void pc87306_init() +void pc87306_reset(void) { memset(pc87306_regs, 0, 29); - lpt2_remove(); - // pc87306_regs[0] = 0xF; pc87306_regs[0] = 0x4B; - // pc87306_regs[1] = 0x11; pc87306_regs[1] = 0x01; pc87306_regs[3] = 2; pc87306_regs[5] = 0xD; @@ -388,5 +385,15 @@ void pc87306_init() fdc_update_densel_polarity(1); fdc_update_max_track(85); fdd_swap = 0; - io_sethandler(0x02e, 0x0002, pc87306_read, NULL, NULL, pc87306_write, NULL, NULL, NULL); +} + +void pc87306_init() +{ + lpt2_remove(); + + pc87306_reset(); + + io_sethandler(0x02e, 0x0002, pc87306_read, NULL, NULL, pc87306_write, NULL, NULL, NULL); + + pci_reset_handler.super_io_reset = pc87306_reset; } diff --git a/src/piix.c b/src/piix.c index 2a28547c9..d0672e63d 100644 --- a/src/piix.c +++ b/src/piix.c @@ -500,9 +500,41 @@ void piix_bus_master_set_irq(int channel) piix_busmaster[channel].status |= 4; } -static int reset_reg = 0; +/* static int reset_reg = 0; -void piix_reset() +static uint8_t rc_read(uint16_t port, void *priv) +{ + return reset_reg & 0xfb; +} + +static void rc_write(uint16_t port, uint8_t val, void *priv) +{ + if (!(reset_reg & 4) && (val & 4)) + { + if (reset_reg & 2) + { + // pclog("PIIX: Hard reset\n"); + resetpchard(); + } + else + { + // pclog("PIIX: Soft reset\n"); + if (piix_type == 3) + { + piix3_reset(); + } + else + { + piix_reset(); + } + resetide(); + softresetx86(); + } + } + reset_reg = val; +} */ + +void piix_reset(void) { memset(card_piix, 0, 256); card_piix[0x00] = 0x86; card_piix[0x01] = 0x80; /*Intel*/ @@ -541,7 +573,7 @@ void piix_reset() card_piix_ide[0x42] = card_piix_ide[0x43] = 0x00; } -void piix3_reset() +void piix3_reset(void) { memset(card_piix, 0, 256); card_piix[0x00] = 0x86; card_piix[0x01] = 0x80; /*Intel*/ @@ -582,57 +614,25 @@ void piix3_reset() card_piix_ide[0x44] = 0x00; } -static uint8_t rc_read(uint16_t port, void *priv) -{ - return reset_reg & 0xfb; -} - -static void rc_write(uint16_t port, uint8_t val, void *priv) -{ - if (!(reset_reg & 4) && (val & 4)) - { - if (reset_reg & 2) - { - // pclog("PIIX: Hard reset\n"); - resetpchard(); - } - else - { - // pclog("PIIX: Soft reset\n"); - if (piix_type == 3) - { - piix3_reset(); - } - else - { - piix_reset(); - } - resetide(); - softresetx86(); - } - } - reset_reg = val; -} - void piix_init(int card) { pci_add_specific(card, piix_read, piix_write, NULL); piix_reset(); - reset_reg = 0; - piix_type = 1; ide_set_bus_master(piix_bus_master_dma_read, piix_bus_master_dma_write, piix_bus_master_set_irq); - io_sethandler(0x0cf9, 0x0001, rc_read, NULL, NULL, rc_write, NULL, NULL, NULL); + trc_init(); port_92_reset(); port_92_add(); dma_alias_set(); + + pci_reset_handler.pci_set_reset = piix_reset; } void piix3_init(int card) @@ -641,17 +641,17 @@ void piix3_init(int card) piix3_reset(); - reset_reg = 0; - piix_type = 3; ide_set_bus_master(piix_bus_master_dma_read, piix_bus_master_dma_write, piix_bus_master_set_irq); - io_sethandler(0x0cf9, 0x0001, rc_read, NULL, NULL, rc_write, NULL, NULL, NULL); + trc_init(); port_92_reset(); port_92_add(); dma_alias_set(); + + pci_reset_handler.pci_set_reset = piix_reset; } diff --git a/src/resources.h b/src/resources.h index 406bfba81..dbd056533 100644 --- a/src/resources.h +++ b/src/resources.h @@ -15,6 +15,7 @@ #define IDM_CONFIG 40020 #define IDM_CONFIG_LOAD 40021 #define IDM_CONFIG_SAVE 40022 +#define IDM_USE_NUKEDOPL 40023 #define IDM_STATUS 40030 #define IDM_VID_RESIZE 40050 #define IDM_VID_REMEMBER 40051 diff --git a/src/sio.c b/src/sio.c index a808aeb7b..ffc676995 100644 --- a/src/sio.c +++ b/src/sio.c @@ -9,6 +9,8 @@ #include #include "ibm.h" +#include "cdrom.h" +#include "cpu.h" #include "ide.h" #include "io.h" #include "mem.h" @@ -82,9 +84,64 @@ uint8_t sio_read(int func, int addr, void *priv) return card_sio[addr]; } -static int reset_reg = 0; +static int trc_reg = 0; -void sio_reset() +uint8_t trc_read(uint16_t port, void *priv) +{ + return trc_reg & 0xfb; +} + +void trc_write(uint16_t port, uint8_t val, void *priv) +{ + int i = 0; + + pclog("TRC Write: %02X\n", val); + if (!(trc_reg & 4) && (val & 4)) + { + if (val & 2) + { + if (pci_reset_handler.pci_master_reset) + { + pci_reset_handler.pci_master_reset(); + } + + if (pci_reset_handler.pci_set_reset) + { + pci_reset_handler.pci_set_reset(); + } + + fdc_hard_reset(); + + if (pci_reset_handler.super_io_reset) + { + pci_reset_handler.super_io_reset(); + } + + resetide(); + for (i = 0; i < CDROM_NUM; i++) + { + if (!cdrom_drives[i].bus_type) + { + cdrom_reset(i); + } + } + + port_92_reset(); + keyboard_at_reset(); + } + resetx86(); + } + trc_reg = val & 0xfd; +} + +void trc_init() +{ + trc_reg = 0; + + io_sethandler(0x0cf9, 0x0001, trc_read, NULL, NULL, trc_write, NULL, NULL, NULL); +} + +void sio_reset(void) { memset(card_sio, 0, 256); card_sio[0x00] = 0x86; card_sio[0x01] = 0x80; /*Intel*/ @@ -109,44 +166,19 @@ void sio_reset() card_sio[0xA8] = 0x0F; } -static uint8_t rc_read(uint16_t port, void *priv) -{ - return reset_reg & 0xfb; -} - -static void rc_write(uint16_t port, uint8_t val, void *priv) -{ - if (!(reset_reg & 4) && (val & 4)) - { - if (reset_reg & 2) - { - // pclog("SIO: Hard reset\n"); - resetpchard(); - } - else - { - // pclog("SIO: Soft reset\n"); - sio_reset(); - resetide(); - softresetx86(); - } - } - reset_reg = val; -} - void sio_init(int card) { pci_add_specific(card, sio_read, sio_write, NULL); - sio_reset(); + sio_reset(); - reset_reg = 0; - - io_sethandler(0x0cf9, 0x0001, rc_read, NULL, NULL, rc_write, NULL, NULL, NULL); + trc_init(); port_92_reset(); port_92_add(); dma_alias_set(); + + pci_reset_handler.pci_set_reset = sio_reset; } diff --git a/src/sound_dbopl.cc b/src/sound_dbopl.cc index cd13180f3..13f87df44 100644 --- a/src/sound_dbopl.cc +++ b/src/sound_dbopl.cc @@ -5,6 +5,8 @@ #include "dosbox/nukedopl.h" #include "sound_dbopl.h" +int opl3_type = 0; + static struct { DBOPL::Chip chip; @@ -38,13 +40,13 @@ enum void opl_init(void (*timer_callback)(void *param, int timer, int64_t period), void *timer_param, int nr, int is_opl3) { - if (!is_opl3) + if (!is_opl3 || !opl3_type) { DBOPL::InitTables(); opl[nr].chip.Setup(48000, 0); opl[nr].timer_callback = timer_callback; opl[nr].timer_param = timer_param; - opl[nr].is_opl3 = 0; + opl[nr].is_opl3 = is_opl3; } else { @@ -154,5 +156,18 @@ void opl2_update(int nr, int16_t *buffer, int samples) void opl3_update(int nr, int16_t *buffer, int samples) { + int c; + Bit32s buffer_32[samples*2]; + + if (opl3_type) + { OPL3_GenerateStream(&opl[nr].opl3chip, buffer, samples); + } + else + { + opl[nr].chip.GenerateBlock3(samples, buffer_32); + + for (c = 0; c < samples*2; c++) + buffer[c] = (int16_t)buffer_32[c]; + } } diff --git a/src/sound_dbopl.h b/src/sound_dbopl.h index d16ce9549..49b2aa095 100644 --- a/src/sound_dbopl.h +++ b/src/sound_dbopl.h @@ -10,6 +10,8 @@ extern "C" { void opl_timer_over(int nr, int timer); void opl2_update(int nr, int16_t *buffer, int samples); void opl3_update(int nr, int16_t *buffer, int samples); + + extern int opl3_type; #ifdef __cplusplus } #endif diff --git a/src/vid_voodoo.c b/src/vid_voodoo.c index 8d8afeb39..172a6e17e 100644 --- a/src/vid_voodoo.c +++ b/src/vid_voodoo.c @@ -3411,7 +3411,6 @@ static inline void queue_triangle(voodoo_t *voodoo, voodoo_params_t *params) static void voodoo_fastfill(voodoo_t *voodoo, voodoo_params_t *params) { int y; - int low_y, high_y; if (params->fbzMode & (1 << 17)) @@ -3425,7 +3424,7 @@ static void voodoo_fastfill(voodoo_t *voodoo, voodoo_params_t *params) high_y = params->clipHighY; } - if (params->fbzMode & FBZ_RGB_WMASK) + if (params->fbzMode & FBZ_RGB_WMASK) { int r, g, b; uint16_t col; @@ -4610,21 +4609,21 @@ static void voodoo_reg_writel(uint32_t addr, uint32_t val, void *p) break; case SST_bltSrcChromaRange: voodoo->bltSrcChromaRange = val; - voodoo->bltSrcChromaMinR = val & 0x1f; + voodoo->bltSrcChromaMinB = val & 0x1f; voodoo->bltSrcChromaMinG = (val >> 5) & 0x3f; - voodoo->bltSrcChromaMinB = (val >> 11) & 0x1f; - voodoo->bltSrcChromaMaxR = (val >> 16) & 0x1f; + voodoo->bltSrcChromaMinR = (val >> 11) & 0x1f; + voodoo->bltSrcChromaMaxB = (val >> 16) & 0x1f; voodoo->bltSrcChromaMaxG = (val >> 21) & 0x3f; - voodoo->bltSrcChromaMaxB = (val >> 27) & 0x1f; + voodoo->bltSrcChromaMaxR = (val >> 27) & 0x1f; break; case SST_bltDstChromaRange: voodoo->bltDstChromaRange = val; - voodoo->bltDstChromaMinR = val & 0x1f; + voodoo->bltDstChromaMinB = val & 0x1f; voodoo->bltDstChromaMinG = (val >> 5) & 0x3f; - voodoo->bltDstChromaMinB = (val >> 11) & 0x1f; - voodoo->bltDstChromaMaxR = (val >> 16) & 0x1f; + voodoo->bltDstChromaMinR = (val >> 11) & 0x1f; + voodoo->bltDstChromaMaxB = (val >> 16) & 0x1f; voodoo->bltDstChromaMaxG = (val >> 21) & 0x3f; - voodoo->bltDstChromaMaxB = (val >> 27) & 0x1f; + voodoo->bltDstChromaMaxR = (val >> 27) & 0x1f; break; case SST_bltClipX: voodoo->bltClipRight = val & 0xfff; @@ -5627,6 +5626,8 @@ static uint32_t voodoo_readl(uint32_t addr, void *p) temp |= (voodoo->swap_count << 28); if (voodoo->cmd_written - voodoo->cmd_read) temp |= 0x380; /*Busy*/ + if (voodoo->cmdfifo_depth_rd != voodoo->cmdfifo_depth_wr) + temp |= 0x380; /*Busy*/ if (!voodoo->v_retrace) temp |= 0x40; if (!voodoo->voodoo_busy) diff --git a/src/w83877f.c b/src/w83877f.c index ef595040f..0096b998d 100644 --- a/src/w83877f.c +++ b/src/w83877f.c @@ -481,13 +481,14 @@ uint8_t w83877f_read(uint16_t port, void *priv) } } -void w83877f_init() +void w83877f_reset(void) { - fdc_remove(); - fdc_add_for_superio(); lpt1_remove(); lpt1_init(0x378); - lpt2_remove(); + + fdc_remove(); + fdc_add_for_superio(); + w83877f_regs[3] = 0x30; w83877f_regs[7] = 0xF5; w83877f_regs[9] = 0x0A; @@ -525,3 +526,12 @@ void w83877f_init() w83877f_locked = 0; w83877f_rw_locked = 0; } + +void w83877f_init() +{ + lpt2_remove(); + + w83877f_reset(); + + pci_reset_handler.super_io_reset = w83877f_reset; +} diff --git a/src/win.c b/src/win.c index 33840cd63..79b46de76 100644 --- a/src/win.c +++ b/src/win.c @@ -32,6 +32,7 @@ #include "nethandler.h" #include "nvr.h" #include "sound.h" +#include "sound_dbopl.h" #include "thread.h" #include "disc.h" @@ -772,6 +773,7 @@ int WINAPI WinMain (HINSTANCE hThisInstance, #endif #endif + CheckMenuItem(menu, IDM_USE_NUKEDOPL, opl3_type ? MF_CHECKED : MF_UNCHECKED); CheckMenuItem(menu, IDM_VID_FORCE43, force_43 ? MF_CHECKED : MF_UNCHECKED); CheckMenuItem(menu, IDM_VID_OVERSCAN, enable_overscan ? MF_CHECKED : MF_UNCHECKED); CheckMenuItem(menu, IDM_VID_FLASH, enable_flash ? MF_CHECKED : MF_UNCHECKED); @@ -1525,6 +1527,20 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM saveconfig(); break; + case IDM_USE_NUKEDOPL: + if (MessageBox(NULL,"This will reset 86Box!\nOkay to continue?","86Box",MB_OKCANCEL) != IDOK) + { + break; + } + pause = 1; + Sleep(100); + opl3_type ^= 1; + CheckMenuItem(hmenu, IDM_USE_NUKEDOPL, opl3_type ? MF_CHECKED : MF_UNCHECKED); + saveconfig(); + resetpchard(); + pause = 0; + break; + case IDM_VID_FORCE43: video_toggle_option(hmenu, &force_43, IDM_VID_FORCE43); break;