From 56a8da6cf534d9df4805162905ca43742ef44d31 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Fri, 8 Nov 2019 08:06:02 +0100
Subject: [PATCH] PCI Reset Control register now forces bit 4 to be written as
 0, fixes resets through this register from the second soft reset onwards.

---
 src/pci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/pci.c b/src/pci.c
index 1e27becdf..05519cc2e 100644
--- a/src/pci.c
+++ b/src/pci.c
@@ -8,7 +8,7 @@
  *
  *		Implementation the PCI bus.
  *
- * Version:	@(#)pci.c	1.0.3	2019/10/30
+ * Version:	@(#)pci.c	1.0.4	2019/11/06
  *
  * Authors:	Miran Grca, <mgrca8@gmail.com>
  *		Fred N. van Kempen, <decwiz@yahoo.com>
@@ -635,7 +635,7 @@ trc_write(uint16_t port, uint8_t val, void *priv)
     if (!(trc_reg & 4) && (val & 4))
 	trc_reset(val);
 
-    trc_reg = val & 0xfd;
+    trc_reg = val & 0xfb;
 }