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Slightly dumbed down the NCR 53c810 external BIOS support - it violates the PCI standard (because the BIOS' presence is not declared in the PCI registers) but it works.

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This commit is contained in:
OBattler
2018-05-23 01:33:35 +02:00
parent ae644a8fda
commit 56c2007b91
1 changed files with 2 additions and 60 deletions
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62
src/scsi/scsi_ncr53c810.c
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@@ -191,7 +191,6 @@ typedef struct {
uint8_t pci_slot; uint8_t pci_slot;
int has_bios; int has_bios;
rom_t bios; rom_t bios;
uint32_t bios_addr, bios_mask;
int PCIBase; int PCIBase;
int MMIOBase; int MMIOBase;
mem_mapping_t mmio_mapping; mem_mapping_t mmio_mapping;
@@ -1980,28 +1979,7 @@ ncr53c810_mem_disable(ncr53c810_t *dev)
uint8_t ncr53c810_pci_regs[256]; uint8_t ncr53c810_pci_regs[256];
bar_t ncr53c810_pci_bar[3]; bar_t ncr53c810_pci_bar[2];
static void
ncr53c810_bios_update(ncr53c810_t *dev)
{
int bios_enabled = ncr53c810_pci_bar[2].addr_regs[0] & 0x01;
if (!dev->has_bios)
return;
/* PCI BIOS stuff, just enable_disable. */
if ((dev->bios_addr > 0) && bios_enabled) {
mem_mapping_enable(&dev->bios.mapping);
mem_mapping_set_addr(&dev->bios.mapping,
dev->bios_addr, 0x4000);
ncr53c810_log("NCR53c810: BIOS now at: %06X\n", dev->bios_addr);
} else {
ncr53c810_log("NCR53c810: BIOS disabled\n");
mem_mapping_disable(&dev->bios.mapping);
}
}
static uint8_t static uint8_t
@@ -2011,9 +1989,6 @@ ncr53c810_pci_read(int func, int addr, void *p)
ncr53c810_log("NCR53c810: Reading register %02X\n", addr & 0xff); ncr53c810_log("NCR53c810: Reading register %02X\n", addr & 0xff);
if ((addr >= 0x30) && (addr <= 0x33) && !dev->has_bios)
return 0x00;
if ((addr >= 0x80) && (addr <= 0xDF)) if ((addr >= 0x80) && (addr <= 0xDF))
return ncr53c810_reg_readb(dev, addr & 0x7F); return ncr53c810_reg_readb(dev, addr & 0x7F);
@@ -2069,17 +2044,6 @@ ncr53c810_pci_read(int func, int addr, void *p)
return 0x01; return 0x01;
case 0x2F: case 0x2F:
return 0x00; return 0x00;
case 0x30: /* PCI_ROMBAR */
return ncr53c810_pci_bar[2].addr_regs[0] & 0x01;
case 0x31: /* PCI_ROMBAR 15:11 */
return ncr53c810_pci_bar[2].addr_regs[1];
break;
case 0x32: /* PCI_ROMBAR 23:16 */
return ncr53c810_pci_bar[2].addr_regs[2];
break;
case 0x33: /* PCI_ROMBAR 31:24 */
return ncr53c810_pci_bar[2].addr_regs[3];
break;
case 0x3C: case 0x3C:
return dev->irq; return dev->irq;
case 0x3D: case 0x3D:
@@ -2102,9 +2066,6 @@ ncr53c810_pci_write(int func, int addr, uint8_t val, void *p)
ncr53c810_log("NCR53c810: Write value %02X to register %02X\n", val, addr & 0xff); ncr53c810_log("NCR53c810: Write value %02X to register %02X\n", val, addr & 0xff);
if ((addr >= 0x30) && (addr <= 0x33) && !dev->has_bios)
return;
if ((addr >= 0x80) && (addr <= 0xDF)) { if ((addr >= 0x80) && (addr <= 0xDF)) {
ncr53c810_reg_writeb(dev, addr & 0x7F, val); ncr53c810_reg_writeb(dev, addr & 0x7F, val);
return; return;
@@ -2175,17 +2136,6 @@ ncr53c810_pci_write(int func, int addr, uint8_t val, void *p)
} }
return; return;
case 0x30: /* PCI_ROMBAR */
case 0x31: /* PCI_ROMBAR */
case 0x32: /* PCI_ROMBAR */
case 0x33: /* PCI_ROMBAR */
ncr53c810_pci_bar[2].addr_regs[addr & 3] = val;
ncr53c810_pci_bar[2].addr &= 0xffffc001;
dev->bios_addr = ncr53c810_pci_bar[2].addr & 0xffffc000;
ncr53c810_log("NCR53c810: BIOS BAR %02X = NOW %02X (%02X)\n", addr & 3, ncr53c810_pci_bar[2].addr_regs[addr & 3], val);
ncr53c810_bios_update(dev);
return;
case 0x3C: case 0x3C:
ncr53c810_pci_regs[addr] = val; ncr53c810_pci_regs[addr] = val;
dev->irq = val; dev->irq = val;
@@ -2219,17 +2169,9 @@ ncr53c810_init(const device_t *info)
dev->has_bios = device_get_config_int("bios"); dev->has_bios = device_get_config_int("bios");
/* Enable our BIOS space in PCI, if needed. */ /* Enable our BIOS space in PCI, if needed. */
if (dev->has_bios) { if (dev->has_bios)
dev->bios_mask = 0xffffc000;
rom_init(&dev->bios, NCR53C810_ROM, 0xd8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL); rom_init(&dev->bios, NCR53C810_ROM, 0xd8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
ncr53c810_pci_bar[2].addr = 0xFFFFC000;
mem_mapping_disable(&dev->bios.mapping);
} else
ncr53c810_pci_bar[2].addr = 0;
return(dev); return(dev);
} }