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Align assignments in cpu_table

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Jasmine Iwanek
2024-07-23 19:53:27 -04:00
parent cb6cc140d2
commit 56cc182e61
1 changed files with 6323 additions and 6313 deletions
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16
src/cpu/cpu_table.c
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@@ -2494,8 +2494,8 @@ const cpu_family_t cpu_families[] = {
{ .name = "", 0 } { .name = "", 0 }
} }
}, },
{ { /*OEM versions are 3.3V, Retail versions are 3.3V with a 5V regulator for installation in older boards. They are functionally identical*/
.package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, /*OEM versions are 3.3V, Retail versions are 3.3V with a 5V regulator for installation in older boards. They are functionally identical*/ .package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330,
.manufacturer = "Intel", .manufacturer = "Intel",
.name = "iDX4", .name = "iDX4",
.internal_name = "idx4", .internal_name = "idx4",
@@ -4023,7 +4023,17 @@ const cpu_family_t cpu_families[] = {
.fpus = fpus_internal, .fpus = fpus_internal,
.rspeed = 75000000, .rspeed = 75000000,
.multi = 1.5, .multi = 1.5,
.voltage = 3520, .edx_reset = 0x1542, .cpuid_model = 0x1542, .cyrix_id = 0, .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, .mem_read_cycles = 7, .mem_write_cycles = 7,.cache_read_cycles = 4,.cache_write_cycles = 4, .atclk_div = 9}, .voltage = 3520,
.edx_reset = 0x1542,
.cpuid_model = 0x1542,
.cyrix_id = 0,
.cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER,
.mem_read_cycles = 7,
.mem_write_cycles = 7,
.cache_read_cycles = 4,
.cache_write_cycles = 4,
.atclk_div = 9
},
{ {
.name = "125", .name = "125",
.cpu_type = CPU_PENTIUMMMX, .cpu_type = CPU_PENTIUMMMX,