diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c
index 502b2c86e..1c67c4880 100644
--- a/src/cpu/cpu_table.c
+++ b/src/cpu/cpu_table.c
@@ -1009,12 +1009,92 @@ const cpu_family_t cpu_families[] = {
     .name = "i386SX",
     .internal_name = "i386sx",
     .cpus = (const CPU[]) {
-        {"16",    CPU_386SX, fpus_80386, 16000000,    1, 5000, 0x2308, 0, 0, 0, 3,3,3,3, 2},
-        {"20",    CPU_386SX, fpus_80386, 20000000,    1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
-        {"25",    CPU_386SX, fpus_80386, 25000000,    1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
-        {"33",    CPU_386SX, fpus_80386, 33333333,    1, 5000, 0x2308, 0, 0, 0, 6,6,3,3, 4},
-        {"40",    CPU_386SX, fpus_80386, 40000000,    1, 5000, 0x2308, 0, 0, 0, 7,7,3,3, 5},
-        {"", 0}
+        {
+            .name = "16",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_80386,
+            .rspeed = 16000000,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2308,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 3,
+            .mem_write_cycles = 3,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 2
+        },
+        {
+            .name = "20",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_80386,
+            .rspeed = 20000000,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2308,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 4,
+            .mem_write_cycles = 4,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 3
+        },
+        {
+            .name = "25",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_80386,
+            .rspeed = 25000000,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2308,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 4,
+            .mem_write_cycles = 4,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 3
+        },
+        {
+            .name = "33",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_80386,
+            .rspeed = 33333333,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2308,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 6,
+            .mem_write_cycles = 6,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 4
+        },
+        {
+            .name = "40",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_80386,
+            .rspeed = 40000000,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2308,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 7,
+            .mem_write_cycles = 7,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 5
+        },
+        { .name = "", 0 }
     }
     }, {
     .package = CPU_PKG_386SX,
@@ -1022,12 +1102,92 @@ const cpu_family_t cpu_families[] = {
     .name = "Am386SX",
     .internal_name = "am386sx",
     .cpus = (const CPU[]) {
-        {"16",   CPU_386SX, fpus_80386,     16000000, 1, 5000, 0x2308, 0, 0, 0, 3,3,3,3, 2},
-        {"20",   CPU_386SX, fpus_80386,     20000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
-        {"25",   CPU_386SX, fpus_80386,     25000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
-        {"33",   CPU_386SX, fpus_80386,     33333333, 1, 5000, 0x2308, 0, 0, 0, 6,6,3,3, 4},
-        {"40",   CPU_386SX, fpus_80386,     40000000, 1, 5000, 0x2308, 0, 0, 0, 7,7,3,3, 5},
-        {"", 0}
+        {
+            .name = "16",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_80386,
+            .rspeed = 16000000,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2308,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 3,
+            .mem_write_cycles = 3,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 2
+        },
+        {
+            .name = "20",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_80386,
+            .rspeed = 20000000,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2308,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 4,
+            .mem_write_cycles = 4,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 3
+        },
+        {
+            .name = "25",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_80386,
+            .rspeed = 25000000,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2308,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 4,
+            .mem_write_cycles = 4,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 3
+        },
+        {
+            .name = "33",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_80386,
+            .rspeed = 33333333,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2308,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 6,
+            .mem_write_cycles = 6,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 4
+        },
+        {
+            .name = "40",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_80386,
+            .rspeed = 40000000,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2308,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 7,
+            .mem_write_cycles = 7,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 5
+        },
+        { .name = "", 0 }
     }
     }, {
     .package = CPU_PKG_386DX,
@@ -1081,9 +1241,41 @@ const cpu_family_t cpu_families[] = {
     .name = "M6117",
     .internal_name = "m6117",
     .cpus = (const CPU[]) { /* All timings and edx_reset values assumed. */
-        {"33",    CPU_386SX,      fpus_none,  33333333, 1, 5000, 0x2309, 0, 0, 0, 6,6,3,3, 4},
-        {"40",    CPU_386SX,      fpus_none,  40000000, 1, 5000, 0x2309, 0, 0, 0, 7,7,3,3, 5},
-        {"", 0}
+        {
+            .name = "33",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_none,
+            .rspeed = 33333333,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2309,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 6,
+            .mem_write_cycles = 6,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 4
+        },
+        {
+            .name = "40",
+            .cpu_type = CPU_386SX,
+            .fpus = fpus_none,
+            .rspeed = 40000000,
+            .multi = 1,
+            .voltage = 5000,
+            .edx_reset = 0x2309,
+            .cpuid_model = 0,
+            .cyrix_id = 0,
+            .cpu_flags = 0,
+            .mem_read_cycles = 7,
+            .mem_write_cycles = 7,
+            .cache_read_cycles = 3,
+            .cache_write_cycles = 3,
+            .atclk_div = 5
+        },
+        { .name = "", 0 }
     }
     }, {
     .package = CPU_PKG_386SLC_IBM,