@@ -788,6 +788,7 @@ static void s3_virge_recalctimings(svga_t *svga)
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svga->clock = (cpuclock * (float)(1ull << 32)) / freq;
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svga->clock = (cpuclock * (float)(1ull << 32)) / freq;
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}
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}
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if ((svga->crtc[0x67] & 0xc) != 0xc) /*VGA mode*/
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if ((svga->crtc[0x67] & 0xc) != 0xc) /*VGA mode*/
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{
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{
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svga->ma_latch |= (virge->ma_ext << 16);
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svga->ma_latch |= (virge->ma_ext << 16);
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@@ -982,7 +983,7 @@ s3_virge_mmio_read(uint32_t addr, void *p)
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virge_t *virge = (virge_t *)p;
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virge_t *virge = (virge_t *)p;
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uint8_t ret = 0xff;
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uint8_t ret = 0xff;
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s3_virge_log("MMIO ReadB addr = %04x\n", addr & 0xffff);
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s3_virge_log("[%04X:%08X]: MMIO ReadB addr = %04x\n", CS, cpu_state.pc, addr & 0xffff);
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switch (addr & 0xffff)
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switch (addr & 0xffff)
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{
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{
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@@ -1028,10 +1029,21 @@ static uint16_t
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s3_virge_mmio_read_w(uint32_t addr, void *p)
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s3_virge_mmio_read_w(uint32_t addr, void *p)
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{
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{
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virge_t *virge = (virge_t *)p;
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virge_t *virge = (virge_t *)p;
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uint32_t ret = 0xffff;
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s3_virge_log("MMIO ReadW addr = %04x\n", addr & 0xfffc);
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s3_virge_log("[%04X:%08X]: MMIO ReadW addr = %04x\n", CS, cpu_state.pc, addr & 0xfffe);
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switch (addr & 0xfffe) {
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switch (addr & 0xfffe) {
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case 0x8504:
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if (!virge->fifo_slot)
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virge->subsys_stat |= INT_FIFO_EMP;
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ret |= virge->subsys_stat;
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if (virge->fifo_slot)
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virge->fifo_slot--;
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ret |= 0x30; /*A bit of a workaround at the moment.*/
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s3_virge_update_irqs(virge);
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return ret;
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case 0x859c:
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case 0x859c:
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return virge->cmd_dma;
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return virge->cmd_dma;
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@@ -1050,6 +1062,8 @@ s3_virge_mmio_read_l(uint32_t addr, void *p)
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VIRGEDMAHeader *dmahdr = &virge->dmahdr;
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VIRGEDMAHeader *dmahdr = &virge->dmahdr;
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uint32_t ret = 0xffffffff;
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uint32_t ret = 0xffffffff;
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s3_virge_log("[%04X:%08X]: MMIO ReadL addr = %04x\n", CS, cpu_state.pc, addr & 0xfffc);
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switch (addr & 0xfffc) {
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switch (addr & 0xfffc) {
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case 0x8180:
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case 0x8180:
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ret = virge->streams.pri_ctrl;
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ret = virge->streams.pri_ctrl;
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@@ -1267,8 +1281,9 @@ static void s3_virge_mmio_write(uint32_t addr, uint8_t val, void *p)
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static void
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static void
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s3_virge_mmio_write_w(uint32_t addr, uint16_t val, void *p)
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s3_virge_mmio_write_w(uint32_t addr, uint16_t val, void *p)
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{
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{
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virge_t *virge = (virge_t *)p;
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virge_t *virge = (virge_t *)p;
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s3_virge_log("MMIO WriteW addr = %04x, val = %04x\n", addr & 0xfffe, val);
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s3_virge_log("[%04X:%08X]: MMIO WriteW addr = %04x, val = %04x\n", CS, cpu_state.pc, addr & 0xfffe, val);
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if ((addr & 0xfffe) < 0x8000) {
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if ((addr & 0xfffe) < 0x8000) {
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if (virge->s3d.cmd_set & CMD_SET_MS)
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if (virge->s3d.cmd_set & CMD_SET_MS)
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s3_virge_bitblt(virge, 16, ((val >> 8) | (val << 8)) << 16);
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s3_virge_bitblt(virge, 16, ((val >> 8) | (val << 8)) << 16);
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