Renamed the three CPU folders to their final names.
This commit is contained in:
OBattler
376
src/cpu/386_common.h
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376
src/cpu/386_common.h
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@@ -0,0 +1,376 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Common 386 CPU code.
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*
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*
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*
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* Author: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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* Copyright 2008-2019 Sarah Walker.
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* Copyright 2016-2019 Miran Grca.
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*/
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#ifndef _386_COMMON_H_
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#define _386_COMMON_H_
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#include <stddef.h>
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#ifdef USE_NEW_DYNAREC
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#define readmemb(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1)?readmembl((s)+(a)): *(uint8_t *)(readlookup2[(uint32_t)((s)+(a))>>12] + (uint32_t)((s) + (a))) )
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#define readmemw(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 1))?readmemwl((s)+(a)):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
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#define readmeml(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 3))?readmemll((s)+(a)):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
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#define readmemq(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 7))?readmemql((s)+(a)):*(uint64_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
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#define writememb(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1) writemembl((s)+(a),v); else *(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememw(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 1)) writememwl((s)+(a),v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememl(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 3)) writememll((s)+(a),v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememq(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 7)) writememql((s)+(a),v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#else
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#undef readmemb
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#undef writememb
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#define readmemb(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF)?readmemb386l(s,a): *(uint8_t *)(readlookup2[(uint32_t)((s)+(a))>>12] + (uint32_t)((s) + (a))) )
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#define readmemq(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 7))?readmemql(s,a):*(uint64_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
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#define writememb(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF) writememb386l(s,a,v); else *(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememw(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) writememwl(s,a,v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememl(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) writememll(s,a,v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#define writememq(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 7)) writememql(s,a,v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
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#endif
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int checkio(int port);
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#ifdef USE_NEW_DYNAREC
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#define check_io_perm(port) if (!IOPLp || (cpu_state.eflags&VM_FLAG)) \
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{ \
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int tempi = checkio(port); \
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if (cpu_state.abrt) return 1; \
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if (tempi) \
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{ \
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x86gpf("check_io_perm(): no permission",0); \
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return 1; \
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} \
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}
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#else
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#define check_io_perm(port) if (msw&1 && ((CPL > IOPL) || (cpu_state.eflags&VM_FLAG))) \
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{ \
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int tempi = checkio(port); \
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if (cpu_state.abrt) return 1; \
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if (tempi) \
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{ \
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x86gpf("check_io_perm(): no permission",0); \
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return 1; \
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} \
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}
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#endif
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#define SEG_CHECK_READ(seg) \
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do \
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{ \
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if ((seg)->base == 0xffffffff) \
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{ \
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x86gpf("Segment can't read", 0);\
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return 1; \
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} \
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} while (0)
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#define SEG_CHECK_WRITE(seg) \
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do \
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{ \
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if ((seg)->base == 0xffffffff) \
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{ \
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x86gpf("Segment can't write", 0);\
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return 1; \
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} \
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} while (0)
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#define CHECK_READ(chseg, low, high) \
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if ((low < (chseg)->limit_low) || (high > (chseg)->limit_high) || ((msw & 1) && !(cpu_state.eflags & VM_FLAG) && (((chseg)->access & 10) == 8))) \
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{ \
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x86gpf("Limit check (READ)", 0); \
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return 1; \
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} \
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if (msw&1 && !(cpu_state.eflags&VM_FLAG) && !((chseg)->access & 0x80)) \
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{ \
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if ((chseg) == &cpu_state.seg_ss) \
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x86ss(NULL,(chseg)->seg & 0xfffc); \
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else \
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x86np("Read from seg not present", (chseg)->seg & 0xfffc); \
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return 1; \
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} \
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if (cr0 >> 31) { \
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(void) mmutranslatereal((chseg)->base + low, 0); \
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(void) mmutranslatereal((chseg)->base + high, 0); \
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if (cpu_state.abrt) \
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return 1; \
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}
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#define CHECK_READ_REP(chseg, low, high) \
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if ((low < (chseg)->limit_low) || (high > (chseg)->limit_high)) \
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{ \
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x86gpf("Limit check (READ)", 0); \
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break; \
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} \
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if (msw&1 && !(cpu_state.eflags&VM_FLAG) && !((chseg)->access & 0x80)) \
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{ \
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if ((chseg) == &cpu_state.seg_ss) \
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x86ss(NULL,(chseg)->seg & 0xfffc); \
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else \
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x86np("Read from seg not present", (chseg)->seg & 0xfffc); \
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break; \
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} \
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if (cr0 >> 31) { \
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(void) mmutranslatereal((chseg)->base + low, 0); \
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(void) mmutranslatereal((chseg)->base + high, 0); \
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if (cpu_state.abrt) \
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break; \
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}
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#define CHECK_WRITE_COMMON(chseg, low, high) \
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if ((low < (chseg)->limit_low) || (high > (chseg)->limit_high) || !((chseg)->access & 2) || ((msw & 1) && !(cpu_state.eflags & VM_FLAG) && ((chseg)->access & 8))) \
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{ \
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x86gpf("Limit check (WRITE)", 0); \
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return 1; \
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} \
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if (msw&1 && !(cpu_state.eflags&VM_FLAG) && !((chseg)->access & 0x80)) \
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{ \
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if ((chseg) == &cpu_state.seg_ss) \
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x86ss(NULL,(chseg)->seg & 0xfffc); \
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else \
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x86np("Write to seg not present", (chseg)->seg & 0xfffc); \
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return 1; \
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}
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#define CHECK_WRITE(chseg, low, high) \
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CHECK_WRITE_COMMON(chseg, low, high) \
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if (cr0 >> 31) { \
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(void) mmutranslatereal((chseg)->base + low, 1); \
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(void) mmutranslatereal((chseg)->base + high, 1); \
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if (cpu_state.abrt) \
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return 1; \
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}
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#define CHECK_WRITE_REP(chseg, low, high) \
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if ((low < (chseg)->limit_low) || (high > (chseg)->limit_high)) \
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{ \
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x86gpf("Limit check (WRITE REP)", 0); \
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break; \
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} \
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if (msw&1 && !(cpu_state.eflags&VM_FLAG) && !((chseg)->access & 0x80)) \
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{ \
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if ((chseg) == &cpu_state.seg_ss) \
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x86ss(NULL,(chseg)->seg & 0xfffc); \
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else \
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x86np("Write (REP) to seg not present", (chseg)->seg & 0xfffc); \
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break; \
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} \
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if (cr0 >> 31) { \
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(void) mmutranslatereal((chseg)->base + low, 1); \
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(void) mmutranslatereal((chseg)->base + high, 1); \
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if (cpu_state.abrt) \
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break; \
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}
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#define NOTRM if (!(msw & 1) || (cpu_state.eflags & VM_FLAG))\
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{ \
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x86_int(6); \
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return 1; \
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}
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static __inline uint8_t fastreadb(uint32_t a)
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{
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uint8_t *t;
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if ((a >> 12) == pccache)
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return *((uint8_t *)&pccache2[a]);
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t = getpccache(a);
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if (cpu_state.abrt)
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return 0;
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pccache = a >> 12;
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pccache2 = t;
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return *((uint8_t *)&pccache2[a]);
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}
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static __inline uint16_t fastreadw(uint32_t a)
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{
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uint8_t *t;
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uint16_t val;
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if ((a&0xFFF)>0xFFE)
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{
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val = fastreadb(a);
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val |= (fastreadb(a + 1) << 8);
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return val;
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}
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if ((a>>12)==pccache) return *((uint16_t *)&pccache2[a]);
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t = getpccache(a);
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if (cpu_state.abrt)
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return 0;
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pccache = a >> 12;
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pccache2 = t;
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return *((uint16_t *)&pccache2[a]);
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}
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static __inline uint32_t fastreadl(uint32_t a)
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{
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uint8_t *t;
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uint32_t val;
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if ((a&0xFFF)<0xFFD)
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{
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if ((a>>12)!=pccache)
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{
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t = getpccache(a);
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if (cpu_state.abrt)
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return 0;
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pccache2 = t;
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pccache=a>>12;
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}
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return *((uint32_t *)&pccache2[a]);
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}
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val = fastreadw(a);
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val |= (fastreadw(a + 2) << 16);
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return val;
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}
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static __inline void *get_ram_ptr(uint32_t a)
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{
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if ((a >> 12) == pccache)
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return &pccache2[a];
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else
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{
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uint8_t *t = getpccache(a);
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return &t[a];
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}
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}
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static __inline uint8_t getbyte()
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{
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cpu_state.pc++;
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return fastreadb(cs + (cpu_state.pc - 1));
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}
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static __inline uint16_t getword()
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{
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cpu_state.pc+=2;
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return fastreadw(cs+(cpu_state.pc-2));
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}
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static __inline uint32_t getlong()
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{
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cpu_state.pc+=4;
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return fastreadl(cs+(cpu_state.pc-4));
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}
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static __inline uint64_t getquad()
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{
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cpu_state.pc+=8;
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return fastreadl(cs+(cpu_state.pc-8)) | ((uint64_t)fastreadl(cs+(cpu_state.pc-4)) << 32);
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}
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static __inline uint8_t geteab()
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{
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if (cpu_mod == 3)
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return (cpu_rm & 4) ? cpu_state.regs[cpu_rm & 3].b.h : cpu_state.regs[cpu_rm&3].b.l;
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if (eal_r)
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return *(uint8_t *)eal_r;
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return readmemb(easeg, cpu_state.eaaddr);
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}
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static __inline uint16_t geteaw()
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{
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if (cpu_mod == 3)
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return cpu_state.regs[cpu_rm].w;
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if (eal_r)
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return *(uint16_t *)eal_r;
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return readmemw(easeg, cpu_state.eaaddr);
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}
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static __inline uint32_t geteal()
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{
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if (cpu_mod == 3)
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return cpu_state.regs[cpu_rm].l;
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if (eal_r)
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return *eal_r;
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return readmeml(easeg, cpu_state.eaaddr);
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}
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static __inline uint64_t geteaq()
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{
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return readmemq(easeg, cpu_state.eaaddr);
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}
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static __inline uint8_t geteab_mem()
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{
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if (eal_r) return *(uint8_t *)eal_r;
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return readmemb(easeg,cpu_state.eaaddr);
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}
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static __inline uint16_t geteaw_mem()
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{
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if (eal_r) return *(uint16_t *)eal_r;
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return readmemw(easeg,cpu_state.eaaddr);
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}
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static __inline uint32_t geteal_mem()
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{
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if (eal_r) return *eal_r;
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return readmeml(easeg,cpu_state.eaaddr);
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}
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static __inline int seteaq_cwc(void)
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{
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CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
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return 0;
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}
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static __inline void seteaq(uint64_t v)
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{
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if (seteaq_cwc())
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return;
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#ifdef USE_NEW_DYNAREC
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writememql(easeg + cpu_state.eaaddr, v);
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#else
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writememql(easeg, cpu_state.eaaddr, v);
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#endif
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}
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#ifdef USE_NEW_DYNAREC
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#define seteab(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr); if (eal_w) *(uint8_t *)eal_w=v; else writemembl(easeg+cpu_state.eaaddr,v); } else if (cpu_rm&4) cpu_state.regs[cpu_rm&3].b.h=v; else cpu_state.regs[cpu_rm].b.l=v
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#define seteaw(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg+cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].w=v
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#define seteal(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); if (eal_w) *eal_w=v; else writememll(easeg+cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].l=v
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#else
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#define seteab(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr); if (eal_w) *(uint8_t *)eal_w=v; else { writememb386l(easeg,cpu_state.eaaddr,v); } } else if (cpu_rm&4) cpu_state.regs[cpu_rm&3].b.h=v; else cpu_state.regs[cpu_rm].b.l=v
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#define seteaw(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); if (eal_w) *(uint16_t *)eal_w=v; else { writememwl(easeg,cpu_state.eaaddr,v); } } else cpu_state.regs[cpu_rm].w=v
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#define seteal(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); if (eal_w) *eal_w=v; else { writememll(easeg,cpu_state.eaaddr,v); } } else cpu_state.regs[cpu_rm].l=v
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#endif
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#ifdef USE_NEW_DYNAREC
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#define seteab_mem(v) if (eal_w) *(uint8_t *)eal_w=v; else writemembl(easeg+cpu_state.eaaddr,v);
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#define seteaw_mem(v) if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg+cpu_state.eaaddr,v);
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#define seteal_mem(v) if (eal_w) *eal_w=v; else writememll(easeg+cpu_state.eaaddr,v);
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#else
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#define seteab_mem(v) if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,cpu_state.eaaddr,v);
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||||
#define seteaw_mem(v) if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,cpu_state.eaaddr,v);
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||||
#define seteal_mem(v) if (eal_w) *eal_w=v; else writememll(easeg,cpu_state.eaaddr,v);
|
||||
#endif
|
||||
|
||||
#define getbytef() ((uint8_t)(fetchdat)); cpu_state.pc++
|
||||
#define getwordf() ((uint16_t)(fetchdat)); cpu_state.pc+=2
|
||||
#define getbyte2f() ((uint8_t)(fetchdat>>8)); cpu_state.pc++
|
||||
#define getword2f() ((uint16_t)(fetchdat>>8)); cpu_state.pc+=2
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user