diff --git a/src/chipset/intel_420ex.c b/src/chipset/intel_420ex.c index bf8d84dd5..61f77352b 100644 --- a/src/chipset/intel_420ex.c +++ b/src/chipset/intel_420ex.c @@ -81,16 +81,16 @@ i420ex_map(uint32_t addr, uint32_t size, int state) { switch (state & 3) { case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); break; case 1: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); break; case 2: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); break; case 3: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); break; } flushmmucache_nopc(); @@ -98,7 +98,7 @@ i420ex_map(uint32_t addr, uint32_t size, int state) static void -i420ex_smram_map(i420ex_t *dev, int smm, uint32_t addr, uint32_t size, int is_smram) +i420ex_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram) { mem_set_mem_state_smram(smm, addr, size, is_smram); flushmmucache(); @@ -106,11 +106,16 @@ i420ex_smram_map(i420ex_t *dev, int smm, uint32_t addr, uint32_t size, int is_sm static void -i420ex_smram_handler_phase0(i420ex_t *dev) +i420ex_smram_handler_phase0(void) { /* Disable low extended SMRAM. */ - i420ex_smram_map(dev, 0, 0xa0000, 0x60000, 0); - i420ex_smram_map(dev, 1, 0xa0000, 0x60000, 0); + if (smram[0].size != 0x00000000) { + i420ex_smram_map(0, smram[0].host_base, smram[0].size, 0); + i420ex_smram_map(1, smram[0].host_base, smram[0].size, 0); + + memset(&smram[0], 0x00, sizeof(smram_t)); + mem_mapping_disable(&ram_smram_mapping[0]); + } } @@ -159,15 +164,17 @@ i420ex_smram_handler_phase1(i420ex_t *dev) break; } - if (base != 0x00000000) { + smram[0].size = size; + + if (size != 0x00000000) { mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, 0x00010000); mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base); /* If OSS = 1 and LSS = 0, extended SMRAM is visible outside SMM. */ - i420ex_smram_map(dev, 0, base, size, (regs[0x70] & 0x70) == 0x40); + i420ex_smram_map(0, base, size, (regs[0x70] & 0x70) == 0x40); /* If the register is set accordingly, disable the mapping also in SMM. */ - i420ex_smram_map(dev, 1, base, size, !(regs[0x70] & 0x20)); + i420ex_smram_map(1, base, size, !(regs[0x70] & 0x20)); } } @@ -308,7 +315,7 @@ i420ex_write(int func, int addr, uint8_t val, void *priv) pci_set_irq_routing(PCI_INTA + (addr & 0x01), val & 0xf); break; case 0x70: /* SMRAM */ - i420ex_smram_handler_phase0(dev); + i420ex_smram_handler_phase0(); if (dev->smram_locked) dev->regs[0x70] = (dev->regs[0x70] & 0xdf) | (val & 0x20); else { diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index 3ef03eb08..a65e06dd3 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -63,16 +63,16 @@ i4x0_map(uint32_t addr, uint32_t size, int state) { switch (state & 3) { case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); break; case 1: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); break; case 2: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); break; case 3: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); break; } flushmmucache_nopc(); @@ -92,16 +92,22 @@ i4x0_smram_handler_phase0(i4x0_t *dev) uint32_t tom = (mem_size << 10); /* Disable any active mappings. */ - if (smram[0].host_base != 0x00000000) { - i4x0_smram_map(0, smram[0].host_base, ram_smram_mapping[0].size, 0); - i4x0_smram_map(1, smram[0].host_base, ram_smram_mapping[0].size, 0); + if (smram[0].size != 0x00000000) { + i4x0_smram_map(0, smram[0].host_base, smram[0].size, 0); + i4x0_smram_map(1, smram[0].host_base, smram[0].size, 0); + + memset(&smram[0], 0x00, sizeof(smram_t)); + mem_mapping_disable(&ram_smram_mapping[0]); } - if ((dev->type >= INTEL_440BX) && (smram[1].host_base != 0x00000000)) { - i4x0_smram_map(1, smram[1].host_base, ram_smram_mapping[1].size, 0); + if ((dev->type >= INTEL_440BX) && (smram[1].size != 0x00000000)) { + i4x0_smram_map(1, smram[1].host_base, smram[1].size, 0); tom -= (1 << 20); mem_set_mem_state_smm(tom, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + + memset(&smram[1], 0x00, sizeof(smram_t)); + mem_mapping_disable(&ram_smram_mapping[1]); } } @@ -117,31 +123,33 @@ i4x0_smram_handler_phase1(i4x0_t *dev) if (dev->type >= INTEL_430FX) { /* Set temporary bases and sizes. */ - smram[0].ram_base = 0x000a0000; if ((dev->type >= INTEL_440BX) && (regs[0x73] & 0x80)) { base[0] = 0x100a0000; size[0] = 0x00060000; - smram[0].host_base = 0x100a0000; } else { if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && ((regs[0x72] & 0x07) == 0x04)) { base[0] = 0x000c0000; size[0] = 0x00010000; - smram[0].host_base = smram[0].ram_base = 0x000c0000; } else { base[0] = 0x000a0000; size[0] = 0x00020000; - smram[0].host_base = 0x000a0000; } } - mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, size[0]); - mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base); + if (((regs[0x72] & 0x70) == 0x40) || ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20))) { + smram[0].host_base = base[0]; + smram[0].ram_base = base[0] & 0x000f0000; + smram[0].size = size[0]; - /* If D_OPEN = 1 and D_LCK = 0, extended SMRAM is visible outside SMM. */ - i4x0_smram_map(0, base[0], size[0], ((regs[0x72] & 0x70) == 0x40)); + mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, size[0]); + mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base); - /* If the register is set accordingly, disable the mapping also in SMM. */ - i4x0_smram_map(1, base[0], size[0], ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20))); + /* If D_OPEN = 1 and D_LCK = 0, extended SMRAM is visible outside SMM. */ + i4x0_smram_map(0, base[0], size[0], ((regs[0x72] & 0x70) == 0x40)); + + /* If the register is set accordingly, disable the mapping also in SMM. */ + i4x0_smram_map(1, base[0], size[0], ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20))); + } /* TSEG mapping. */ if (dev->type >= INTEL_440BX) { @@ -153,21 +161,20 @@ i4x0_smram_handler_phase1(i4x0_t *dev) base[1] = size[1] = 0x00000000; if (size[1] != 0x00000000) { - mem_set_mem_state_smm(base[1], size[1], MEM_READ_EXTANY | MEM_WRITE_EXTANY); - smram[1].host_base = base[1] + (1 << 28); smram[1].ram_base = base[1]; + smram[1].size = size[1]; - mem_mapping_set_addr(&ram_smram_mapping[1], smram[1].host_base, size[1]); + mem_mapping_set_addr(&ram_smram_mapping[1], smram[1].host_base, smram[1].size); if (smram[1].ram_base < (1 << 30)) mem_mapping_set_exec(&ram_smram_mapping[1], ram + smram[1].ram_base); else mem_mapping_set_exec(&ram_smram_mapping[1], ram2 + smram[1].ram_base - (1 << 30)); + mem_set_mem_state_smm(base[1], size[1], MEM_READ_EXTANY | MEM_WRITE_EXTANY); i4x0_smram_map(1, smram[1].host_base, size[1], 1); } - } else - base[1] = size[1] = 0x00000000; + } } else { size[0] = 0x00010000; switch (regs[0x72] & 0x03) { @@ -190,18 +197,19 @@ i4x0_smram_handler_phase1(i4x0_t *dev) break; } - if (base[0] != 0x00000000) { + if (((((regs[0x72] & 0x38) == 0x20) || s) || (!(regs[0x72] & 0x10) || s)) && (size[0] != 0x00000000)) { + smram[0].host_base = base[0]; + smram[0].ram_base = base[0]; + smram[0].size = size[0]; + + mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, size[0]); + mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base); + /* If OSS = 1 and LSS = 0, extended SMRAM is visible outside SMM. */ - i4x0_smram_map(0, base[0], size[0], ((regs[0x72] & 0x38) == 0x20) || s); - /* If base is on top of memory, this mapping will point to RAM. - TODO: It should actually point to EXTERNAL (with a SMRAM mapping) instead. */ - /* If we are open, not closed, and not locked, point to RAM. */ + i4x0_smram_map(0, base[0], size[0], (((regs[0x72] & 0x38) == 0x20) || s)); /* If the register is set accordingly, disable the mapping also in SMM. */ - i4x0_smram_map(0, base[0], size[0], !(regs[0x72] & 0x10) || s); - /* If base is on top of memory, this mapping will point to RAM. - TODO: It should actually point to EXTERNAL (with a SMRAM mapping) instead. */ - /* If we are not closed, point to RAM. */ + i4x0_smram_map(0, base[0], size[0], (!(regs[0x72] & 0x10) || s)); } } @@ -1266,9 +1274,6 @@ static void regs = (uint8_t *) dev->regs[0]; - // This is off by default and has to be moved to the appropriate register handling. - // io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); - regs[0x00] = 0x86; regs[0x01] = 0x80; /*Intel*/ switch (dev->type) { diff --git a/src/chipset/via_apollo.c b/src/chipset/via_apollo.c index 6955c025c..a3200669a 100644 --- a/src/chipset/via_apollo.c +++ b/src/chipset/via_apollo.c @@ -46,16 +46,16 @@ apollo_map(uint32_t addr, uint32_t size, int state) { switch (state & 3) { case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); break; case 1: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); break; case 2: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); break; case 3: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); break; } @@ -66,8 +66,13 @@ apollo_map(uint32_t addr, uint32_t size, int state) static void apollo_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram) { - mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, size); - mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base); + if (((is_smram & 0x03) == 0x01) || ((is_smram & 0x03) == 0x02)) { + smram[0].ram_base = 0x000a0000; + smram[0].size = size; + + mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, size); + mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base); + } mem_set_mem_state_smram_ex(smm, addr, size, is_smram & 0x03); flushmmucache(); @@ -264,12 +269,14 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) if ((dev->pci_conf[0][0x63] ^ val) & 0xc0) apollo_map(0xe0000, 0x10000, (val & 0xc0) >> 6); dev->pci_conf[0][0x63] = val; - mem_set_mem_state_smram_ex(0, 0x00030000, 0x00020000, 0x00); - mem_set_mem_state_smram_ex(1, 0x00030000, 0x00020000, 0x00); - mem_set_mem_state_smram_ex(0, 0x000a0000, 0x00020000, 0x00); - mem_set_mem_state_smram_ex(1, 0x000a0000, 0x00020000, 0x00); - smram[0].host_base = 0x000a0000; - smram[0].ram_base = 0x000a0000; + if (smram[0].size != 0x00000000) { + mem_set_mem_state_smram_ex(0, smram[0].host_base, smram[0].size, 0x00); + mem_set_mem_state_smram_ex(1, smram[0].host_base, smram[0].size, 0x00); + + memset(&smram[0], 0x00, sizeof(smram_t)); + mem_mapping_disable(&ram_smram_mapping[0]); + flushmmucache(); + } if (dev->id == 0x0691) switch (val & 0x03) { case 0x00: default: diff --git a/src/cpu/386_common.c b/src/cpu/386_common.c index 1e541edd8..1bda39a95 100644 --- a/src/cpu/386_common.c +++ b/src/cpu/386_common.c @@ -63,6 +63,8 @@ extern uint32_t pccache; int in_sys = 0; +smram_t temp_smram[2]; + #define AMD_SYSCALL_EIP (star & 0xFFFFFFFF) #define AMD_SYSCALL_SB ((star >> 32) & 0xFFFF) @@ -1024,15 +1026,13 @@ enter_smm(int in_hlt) EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP); in_smm = 1; - mem_mapping_recalc(0x00030000, 0x00020000); - mem_mapping_recalc(0x000a0000, 0x00060000); - - if (!cpu_16bitbus) - mem_mapping_recalc(0x100a0000, 0x00060000); - - if (mem_size >= 1024) - mem_mapping_recalc((mem_size << 10) - (1 << 20), (1 << 20)); - + if (smram[0].size) + mem_mapping_recalc(smram[0].host_base, smram[0].size); + if (smram[1].size) + mem_mapping_recalc(smram[1].host_base, smram[1].size); + /* This is used by leave_smm() to make sure we don't keep the old mappings in SMM mode if the SMM + handler has told the chipset to change the actual mappings. */ + memcpy(temp_smram, smram, sizeof(temp_smram)); flushmmucache(); memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t)); @@ -1160,12 +1160,15 @@ leave_smm(void) smram_restore_state_p6(saved_state); in_smm = 0; - mem_mapping_recalc(0x00030000, 0x00020000); - mem_mapping_recalc(0x000a0000, 0x00060000); - if (!cpu_16bitbus) - mem_mapping_recalc(0x100a0000, 0x00060000); - if (mem_size >= 1024) - mem_mapping_recalc((mem_size << 10) - (1 << 20), (1 << 20)); + if (temp_smram[0].size) + mem_mapping_recalc(temp_smram[0].host_base, temp_smram[0].size); + if (temp_smram[1].size) + mem_mapping_recalc(temp_smram[1].host_base, temp_smram[1].size); + memset(temp_smram, 0x00, sizeof(temp_smram)); + if (smram[0].size) + mem_mapping_recalc(smram[0].host_base, smram[0].size); + if (smram[1].size) + mem_mapping_recalc(smram[1].host_base, smram[1].size); flushmmucache(); cpu_state.op32 = use32; diff --git a/src/include/86box/mem.h b/src/include/86box/mem.h index 80b736acb..4104c4fa0 100644 --- a/src/include/86box/mem.h +++ b/src/include/86box/mem.h @@ -94,6 +94,13 @@ #define MEM_GRANULARITY_PAGE (MEM_GRANULARITY_MASK & ~0xfff) #endif +#define mem_set_mem_state_common(smm, base, size, state) mem_set_state(!!smm, 0, base, size, state) +#define mem_set_mem_state(base, size, state) mem_set_state(0, 0, base, size, state) +#define mem_set_mem_state_smm(base, size, state) mem_set_state(1, 0, base, size, state) +#define mem_set_mem_state_both(base, size, state) mem_set_state(2, 0, base, size, state) +#define mem_set_mem_state_smram(smm, base, size, is_smram) mem_set_state(!!smm, 1, base, size, is_smram) +#define mem_set_mem_state_smram_ex(smm, base, size, is_smram) mem_set_state(!!smm, 2, base, size, is_smram) + typedef struct _mem_mapping_ { struct _mem_mapping_ *prev, *next; @@ -178,7 +185,8 @@ typedef struct _page_ { typedef struct { - uint32_t host_base, + uint32_t size, + host_base, ram_base; } smram_t; @@ -300,15 +308,7 @@ extern void mem_mapping_disable(mem_mapping_t *); extern void mem_mapping_enable(mem_mapping_t *); extern void mem_mapping_recalc(uint64_t base, uint64_t size); -extern void mem_set_mem_state_common(int smm, uint32_t base, uint32_t size, int state); - -extern void mem_set_mem_state_smram(int smm, uint32_t base, uint32_t size, int is_smram); -extern void mem_set_mem_state_smram_ex(int smm, uint32_t base, uint32_t size, int is_smram); - -extern void mem_set_mem_state(uint32_t base, uint32_t size, int state); -extern void mem_set_mem_state_smm(uint32_t base, uint32_t size, int state); - -extern void mem_set_mem_state_both(uint32_t base, uint32_t size, int state); +extern void mem_set_state(int smm, int mode, uint32_t base, uint32_t size, uint32_t state); extern uint8_t mem_readb_phys(uint32_t addr); extern uint16_t mem_readw_phys(uint32_t addr); diff --git a/src/mem/mem.c b/src/mem/mem.c index e92652b5c..f83aee0fa 100644 --- a/src/mem/mem.c +++ b/src/mem/mem.c @@ -22,6 +22,7 @@ * Copyright 2016-2020 Miran Grca. * Copyright 2017-2020 Fred N. van Kempen. */ +#include #include #include #include @@ -2085,6 +2086,7 @@ mem_mapping_read_allowed(uint32_t flags, uint32_t state, int exec) { uint32_t smm_state = state >> MEM_STATE_SMM_SHIFT; uint32_t state_masked; + int ret = 0; if (in_smm && ((smm_state & MEM_READ_MASK) != MEM_READ_NORMAL)) state = smm_state; @@ -2092,44 +2094,46 @@ mem_mapping_read_allowed(uint32_t flags, uint32_t state, int exec) state_masked = (state & MEM_READ_MASK); if (state_masked & MEM_READ_SMRAM) - return (flags & MEM_MAPPING_SMRAM); + ret = (flags & MEM_MAPPING_SMRAM); else if ((state_masked & MEM_READ_SMRAM_EX) && exec) - return (flags & MEM_MAPPING_SMRAM); - else if (state_masked & MEM_READ_DISABLED_EX) - return 0; - else switch (state_masked) { - case MEM_READ_DISABLED: - return 0; - + ret = (flags & MEM_MAPPING_SMRAM); + else if (!(state_masked & MEM_READ_DISABLED_EX)) switch (state_masked) { case MEM_READ_ANY: - return !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_SMRAM); + break; /* On external and 0 mappings without ROMCS. */ case MEM_READ_EXTERNAL: - return !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_ROMCS) && !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_ROMCS) && !(flags & MEM_MAPPING_SMRAM); + break; /* On external and 0 mappings with ROMCS. */ case MEM_READ_ROMCS: - return !(flags & MEM_MAPPING_INTERNAL) && (flags & MEM_MAPPING_ROMCS) && !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_INTERNAL) && (flags & MEM_MAPPING_ROMCS) && !(flags & MEM_MAPPING_SMRAM); + break; /* On any external mappings. */ case MEM_READ_EXTANY: - return !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_SMRAM); + break; case MEM_READ_EXTERNAL_EX: if (exec) - return !(flags & MEM_MAPPING_EXTERNAL) && !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_EXTERNAL) && !(flags & MEM_MAPPING_SMRAM); else - return !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_SMRAM); + break; case MEM_READ_INTERNAL: - return !(flags & MEM_MAPPING_EXTERNAL) && !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_EXTERNAL) && !(flags & MEM_MAPPING_SMRAM); + break; default: fatal("mem_mapping_read_allowed : bad state %x\n", state); + break; } - return 0; + return ret; } @@ -2138,6 +2142,7 @@ mem_mapping_write_allowed(uint32_t flags, uint32_t state) { uint32_t smm_state = state >> MEM_STATE_SMM_SHIFT; uint32_t state_masked; + int ret = 0; if (in_smm && ((smm_state & MEM_WRITE_MASK) != MEM_WRITE_NORMAL)) state = smm_state; @@ -2145,36 +2150,37 @@ mem_mapping_write_allowed(uint32_t flags, uint32_t state) state_masked = (state & MEM_WRITE_MASK); if (state_masked & MEM_WRITE_SMRAM) - return (flags & MEM_MAPPING_SMRAM); - else if (state_masked & MEM_WRITE_DISABLED_EX) - return 0; - else switch (state_masked) { - case MEM_WRITE_DISABLED: - return 0; - + ret = (flags & MEM_MAPPING_SMRAM); + else if (!(state_masked & MEM_WRITE_DISABLED_EX)) switch (state_masked) { case MEM_WRITE_ANY: - return !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_SMRAM); + break; /* On external and 0 mappings without ROMCS. */ case MEM_WRITE_EXTERNAL: - return !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_ROMCS) && !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_ROMCS) && !(flags & MEM_MAPPING_SMRAM); + break; /* On external and 0 mappings with ROMCS. */ case MEM_WRITE_ROMCS: - return !(flags & MEM_MAPPING_INTERNAL) && (flags & MEM_MAPPING_ROMCS) && !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_INTERNAL) && (flags & MEM_MAPPING_ROMCS) && !(flags & MEM_MAPPING_SMRAM); + break; /* On any external mappings. */ case MEM_WRITE_EXTANY: - return !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_SMRAM); + break; case MEM_WRITE_INTERNAL: - return !(flags & MEM_MAPPING_EXTERNAL) && !(flags & MEM_MAPPING_SMRAM); + ret = !(flags & MEM_MAPPING_EXTERNAL) && !(flags & MEM_MAPPING_SMRAM); + break; default: fatal("mem_mapping_write_allowed : bad state %x\n", state); + break; } - return 0; + return ret; } @@ -2383,18 +2389,47 @@ mem_mapping_enable(mem_mapping_t *map) void -mem_set_mem_state_common(int smm, uint32_t base, uint32_t size, int state) +mem_set_state(int smm, int mode, uint32_t base, uint32_t size, uint32_t state) { - uint32_t c; + uint32_t c, mask_l, mask_h, smstate = 0x0000; + + if (mode) { + mask_l = 0xffff0f0f; + mask_h = 0x0f0fffff; + } else { + mask_l = 0xfffff0f0; + mask_h = 0xf0f0ffff; + } + + if (mode) { + if (mode == 1) + state = !!state; + + switch (state & 0x03) { + case 0x00: + smstate = 0x0000; + break; + case 0x01: + smstate = (MEM_READ_SMRAM | MEM_WRITE_SMRAM); + break; + case 0x02: + smstate = MEM_READ_SMRAM_EX; + break; + case 0x03: + smstate = (MEM_READ_DISABLED_EX | MEM_WRITE_DISABLED_EX); + break; + } + } else + smstate = state & 0x0f0f; for (c = 0; c < size; c += MEM_GRANULARITY_SIZE) { - if (smm) - _mem_state[(c + base) >> MEM_GRANULARITY_BITS] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS] & 0xf0f0ffff) | ((state & 0x0f0f) << MEM_STATE_SMM_SHIFT); - else - _mem_state[(c + base) >> MEM_GRANULARITY_BITS] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS] & 0xfffff0f0) | (state & 0x0f0f); + if (smm != 0) + _mem_state[(c + base) >> MEM_GRANULARITY_BITS] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS] & mask_h) | (smstate << MEM_STATE_SMM_SHIFT); + if (smm != 1) + _mem_state[(c + base) >> MEM_GRANULARITY_BITS] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS] & mask_l) | smstate; #ifdef ENABLE_MEM_LOG if (((c + base) >= 0xa0000) && ((c + base) <= 0xbffff)) - mem_log("Set mem state for block at %08X to %02X\n", c + base, state); + mem_log("Set mem state for block at %08X to %02X\n", c + base, smstate); #endif } @@ -2402,85 +2437,6 @@ mem_set_mem_state_common(int smm, uint32_t base, uint32_t size, int state) } -void -mem_set_mem_state_smram(int smm, uint32_t base, uint32_t size, int is_smram) -{ - uint32_t c, smstate = 0x0000; - - smstate = is_smram ? (MEM_READ_SMRAM | MEM_WRITE_SMRAM) : 0x0000; - - for (c = 0; c < size; c += MEM_GRANULARITY_SIZE) { - if (smm) - _mem_state[(c + base) >> MEM_GRANULARITY_BITS] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS] & 0x0f0fffff) | (smstate << MEM_STATE_SMM_SHIFT); - else - _mem_state[(c + base) >> MEM_GRANULARITY_BITS] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS] & 0xffff0f0f) | smstate; -#ifdef ENABLE_MEM_LOG - if (((c + base) >= 0xa0000) && ((c + base) <= 0xbffff)) - mem_log("Set mem state SMRAM flag for block at %08X to %02X\n", c + base, state); -#endif - } - - mem_mapping_recalc(base, size); -} - - -void -mem_set_mem_state_smram_ex(int smm, uint32_t base, uint32_t size, int is_smram) -{ - uint32_t c, smstate = 0x0000; - - switch (is_smram & 0x03) { - case 0x00: - smstate = 0x0000; - break; - case 0x01: - smstate = (MEM_READ_SMRAM | MEM_WRITE_SMRAM); - break; - case 0x02: - smstate = MEM_READ_SMRAM_EX; - break; - case 0x03: - smstate = (MEM_READ_DISABLED_EX | MEM_WRITE_DISABLED_EX); - break; - } - - for (c = 0; c < size; c += MEM_GRANULARITY_SIZE) { - if (smm) - _mem_state[(c + base) >> MEM_GRANULARITY_BITS] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS] & 0x0f0fffff) | (smstate << MEM_STATE_SMM_SHIFT); - else - _mem_state[(c + base) >> MEM_GRANULARITY_BITS] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS] & 0xffff0f0f) | smstate; -#ifdef ENABLE_MEM_LOG - if (((c + base) >= 0xa0000) && ((c + base) <= 0xbffff)) - mem_log("Set mem state SMRAM flag for block at %08X to %02X\n", c + base, state); -#endif - } - - mem_mapping_recalc(base, size); -} - - -void -mem_set_mem_state(uint32_t base, uint32_t size, int state) -{ - mem_set_mem_state_common(0, base, size, state); -} - - -void -mem_set_mem_state_smm(uint32_t base, uint32_t size, int state) -{ - mem_set_mem_state_common(1, base, size, state); -} - - -void -mem_set_mem_state_both(uint32_t base, uint32_t size, int state) -{ - mem_set_mem_state_common(0, base, size, state); - mem_set_mem_state_common(1, base, size, state); -} - - void mem_add_bios(void) { @@ -2727,11 +2683,6 @@ mem_log("MEM: reset: new pages=%08lx, pages_sz=%i\n", pages, pages_sz); } } - /* if (mem_size > 768) - mem_mapping_add(&ram_mid_mapping, 0xc0000, 0x40000, - mem_read_ram,mem_read_ramw,mem_read_raml, - mem_write_ram,mem_write_ramw,mem_write_raml, - ram + 0xc0000, MEM_MAPPING_INTERNAL, NULL); */ if (mem_size > 768) { mem_mapping_add(&ram_mid_mapping, 0xa0000, 0x60000, mem_read_ram,mem_read_ramw,mem_read_raml, @@ -2744,8 +2695,8 @@ mem_log("MEM: reset: new pages=%08lx, pages_sz=%i\n", pages, pages_sz); mem_write_smram,mem_write_smramw,mem_write_smraml, ram + 0xa0000, MEM_MAPPING_SMRAM, &(smram[0])); mem_mapping_add(&ram_smram_mapping[1], 0xa0000, 0x60000, - mem_read_ram,mem_read_ramw,mem_read_raml, - mem_write_ram,mem_write_ramw,mem_write_raml, + mem_read_smram,mem_read_smramw,mem_read_smraml, + mem_write_smram,mem_write_smramw,mem_write_smraml, ram + 0xa0000, MEM_MAPPING_SMRAM, &(smram[1])); mem_mapping_disable(&ram_smram_mapping[0]); mem_mapping_disable(&ram_smram_mapping[1]); @@ -2758,8 +2709,8 @@ mem_log("MEM: reset: new pages=%08lx, pages_sz=%i\n", pages, pages_sz); mem_a20_init(); - smram[0].host_base = smram[0].ram_base = 0x00000000; - smram[1].host_base = smram[1].ram_base = 0x00000000; + smram[0].host_base = smram[0].ram_base = smram[0].size = 0x00000000; + smram[1].host_base = smram[1].ram_base = smram[1].size = 0x00000000; #ifdef USE_NEW_DYNAREC purgable_page_list_head = 0;