From 66db0f11a48cbea17765b67e932f48c76bdc015c Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 7 Oct 2021 01:15:02 +0200 Subject: [PATCH] Implemented reset handlers for Cirrus, S3, and S3 ViRGE cards. --- src/video/vid_cl54xx.c | 143 ++++++++++++++++++------ src/video/vid_s3.c | 230 +++++++++++++++++++++++++++++++-------- src/video/vid_s3_virge.c | 108 +++++++++++++++--- 3 files changed, 390 insertions(+), 91 deletions(-) diff --git a/src/video/vid_cl54xx.c b/src/video/vid_cl54xx.c index c1eb9ac2d..730bfe503 100644 --- a/src/video/vid_cl54xx.c +++ b/src/video/vid_cl54xx.c @@ -212,7 +212,7 @@ typedef struct gd54xx_t uint8_t fc; /* Feature Connector */ - int card; + int card, id; uint8_t pos_regs[8]; @@ -3727,6 +3727,78 @@ gd5428_mca_feedb(void *p) return 1; } +static void +gd54xx_reset(void *priv) +{ + gd54xx_t *gd54xx = (gd54xx_t *) priv; + svga_t *svga = &gd54xx->svga; + + memset(svga->crtc, 0x00, sizeof(svga->crtc)); + memset(svga->seqregs, 0x00, sizeof(svga->seqregs)); + memset(svga->gdcreg, 0x00, sizeof(svga->gdcreg)); + svga->crtc[0] = 63; + svga->crtc[6] = 255; + svga->dispontime = 1000ull << 32; + svga->dispofftime = 1000ull << 32; + svga->bpp = 8; + + io_removehandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx); + io_sethandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx); + + mem_mapping_disable(&gd54xx->vgablt_mapping); + if (gd54xx->has_bios) + mem_mapping_disable(&gd54xx->bios_rom.mapping); + + memset(gd54xx->pci_regs, 0x00, 256); + + gd543x_recalc_mapping(gd54xx); + + mem_mapping_set_p(&svga->mapping, gd54xx); + mem_mapping_disable(&gd54xx->mmio_mapping); + mem_mapping_disable(&gd54xx->linear_mapping); + mem_mapping_disable(&gd54xx->aperture2_mapping); + mem_mapping_disable(&gd54xx->vgablt_mapping); + + svga->hwcursor.yoff = svga->hwcursor.xoff = 0; + + if (gd54xx->id >= CIRRUS_ID_CLGD5420) { + gd54xx->vclk_n[0] = 0x4a; + gd54xx->vclk_d[0] = 0x2b; + gd54xx->vclk_n[1] = 0x5b; + gd54xx->vclk_d[1] = 0x2f; + gd54xx->vclk_n[2] = 0x45; + gd54xx->vclk_d[2] = 0x30; + gd54xx->vclk_n[3] = 0x7e; + gd54xx->vclk_d[3] = 0x33; + } else { + gd54xx->vclk_n[0] = 0x66; + gd54xx->vclk_d[0] = 0x3b; + gd54xx->vclk_n[1] = 0x5b; + gd54xx->vclk_d[1] = 0x2f; + gd54xx->vclk_n[2] = 0x45; + gd54xx->vclk_d[2] = 0x2c; + gd54xx->vclk_n[3] = 0x7e; + gd54xx->vclk_d[3] = 0x33; + } + + svga->extra_banks[1] = 0x8000; + + gd54xx->pci_regs[PCI_REG_COMMAND] = 7; + + gd54xx->pci_regs[0x30] = 0x00; + gd54xx->pci_regs[0x32] = 0x0c; + gd54xx->pci_regs[0x33] = 0x00; + + svga->crtc[0x27] = gd54xx->id; + + svga->seqregs[6] = 0x0f; + if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5429) + gd54xx->unlocked = 1; + else + gd54xx->unlocked = 0; +} + + static void *gd54xx_init(const device_t *info) { @@ -3745,8 +3817,9 @@ static void gd54xx->rev = 0; gd54xx->has_bios = 1; - switch (id) { - + gd54xx->id = id; + + switch (id) { case CIRRUS_ID_CLGD5401: romfn = BIOS_GD5401_PATH; break; @@ -3921,14 +3994,17 @@ static void gd5480_vgablt_write, gd5480_vgablt_writew, NULL, NULL, MEM_MAPPING_EXTERNAL, gd54xx); } + io_sethandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx); + + if (gd54xx->pci && id >= CIRRUS_ID_CLGD5430) + pci_add_card(PCI_ADD_VIDEO, cl_pci_read, cl_pci_write, gd54xx); + mem_mapping_set_p(&svga->mapping, gd54xx); mem_mapping_disable(&gd54xx->mmio_mapping); mem_mapping_disable(&gd54xx->linear_mapping); mem_mapping_disable(&gd54xx->aperture2_mapping); mem_mapping_disable(&gd54xx->vgablt_mapping); - io_sethandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx); - svga->hwcursor.yoff = svga->hwcursor.xoff = 0; if (id >= CIRRUS_ID_CLGD5420) { @@ -3953,15 +4029,12 @@ static void svga->extra_banks[1] = 0x8000; - if (gd54xx->pci && id >= CIRRUS_ID_CLGD5430) - pci_add_card(PCI_ADD_VIDEO, cl_pci_read, cl_pci_write, gd54xx); - gd54xx->pci_regs[PCI_REG_COMMAND] = 7; gd54xx->pci_regs[0x30] = 0x00; gd54xx->pci_regs[0x32] = 0x0c; gd54xx->pci_regs[0x33] = 0x00; - + svga->crtc[0x27] = id; svga->seqregs[6] = 0x0f; @@ -4260,7 +4333,7 @@ const device_t gd5401_isa_device = DEVICE_ISA, CIRRUS_ID_CLGD5401, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5401_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4273,7 +4346,7 @@ const device_t gd5402_isa_device = DEVICE_ISA, CIRRUS_ID_CLGD5402, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5402_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4286,7 +4359,7 @@ const device_t gd5402_onboard_device = DEVICE_AT | DEVICE_ISA, CIRRUS_ID_CLGD5402 | 0x200, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { NULL }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4299,7 +4372,7 @@ const device_t gd5420_isa_device = DEVICE_AT | DEVICE_ISA, CIRRUS_ID_CLGD5420, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5420_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4311,7 +4384,7 @@ const device_t gd5422_isa_device = { DEVICE_AT | DEVICE_ISA, CIRRUS_ID_CLGD5422, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5422_available }, /* Common BIOS between 5422 and 5424 */ gd54xx_speed_changed, gd54xx_force_redraw, @@ -4323,7 +4396,7 @@ const device_t gd5424_vlb_device = { DEVICE_VLB, CIRRUS_ID_CLGD5424, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5422_available }, /* Common BIOS between 5422 and 5424 */ gd54xx_speed_changed, gd54xx_force_redraw, @@ -4337,7 +4410,7 @@ const device_t gd5426_vlb_device = CIRRUS_ID_CLGD5426, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5426_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4351,7 +4424,7 @@ const device_t gd5426_onboard_device = CIRRUS_ID_CLGD5426 | 0x200, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { NULL }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4365,7 +4438,7 @@ const device_t gd5428_isa_device = CIRRUS_ID_CLGD5428, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5428_isa_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4379,7 +4452,7 @@ const device_t gd5428_vlb_device = CIRRUS_ID_CLGD5428, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5428_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4393,7 +4466,7 @@ const device_t gd5428_mca_device = CIRRUS_ID_CLGD5428, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5428_mca_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4407,7 +4480,7 @@ const device_t gd5428_onboard_device = CIRRUS_ID_CLGD5428, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5428_isa_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4421,7 +4494,7 @@ const device_t gd5429_isa_device = CIRRUS_ID_CLGD5429, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5429_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4435,7 +4508,7 @@ const device_t gd5429_vlb_device = CIRRUS_ID_CLGD5429, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5429_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4449,7 +4522,7 @@ const device_t gd5430_vlb_device = CIRRUS_ID_CLGD5430, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5430_vlb_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4463,7 +4536,7 @@ const device_t gd5430_pci_device = CIRRUS_ID_CLGD5430, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5430_pci_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4477,7 +4550,7 @@ const device_t gd5434_isa_device = CIRRUS_ID_CLGD5434, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5434_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4491,7 +4564,7 @@ const device_t gd5434_onboard_pci_device = CIRRUS_ID_CLGD5434 | 0x200, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { NULL }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4505,7 +4578,7 @@ const device_t gd5434_vlb_device = CIRRUS_ID_CLGD5434, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5434_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4519,7 +4592,7 @@ const device_t gd5434_pci_device = CIRRUS_ID_CLGD5434, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5434_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4533,7 +4606,7 @@ const device_t gd5436_pci_device = CIRRUS_ID_CLGD5436, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5436_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4547,7 +4620,7 @@ const device_t gd5440_onboard_pci_device = CIRRUS_ID_CLGD5440 | 0x600, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { NULL }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4561,7 +4634,7 @@ const device_t gd5440_pci_device = CIRRUS_ID_CLGD5440 | 0x400, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5440_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4575,7 +4648,7 @@ const device_t gd5446_pci_device = CIRRUS_ID_CLGD5446, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5446_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4589,7 +4662,7 @@ const device_t gd5446_stb_pci_device = CIRRUS_ID_CLGD5446 | 0x100, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5446_stb_available }, gd54xx_speed_changed, gd54xx_force_redraw, @@ -4603,7 +4676,7 @@ const device_t gd5480_pci_device = CIRRUS_ID_CLGD5480, gd54xx_init, gd54xx_close, - NULL, + gd54xx_reset, { gd5480_available }, gd54xx_speed_changed, gd54xx_force_redraw, diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c index d516ebe70..84f49425a 100644 --- a/src/video/vid_s3.c +++ b/src/video/vid_s3.c @@ -351,6 +351,8 @@ typedef struct s3_t uint8_t thread_run, serialport; void *i2c, *ddc; + + int vram; } s3_t; #define INT_VSY (1 << 0) @@ -6382,6 +6384,147 @@ static int vram_sizes[] = 3 /*8 MB*/ }; + +static void s3_reset(void *priv) +{ + s3_t *s3 = (s3_t *) priv; + svga_t *svga = &s3->svga; + + memset(svga->crtc, 0x00, sizeof(svga->crtc)); + svga->crtc[0] = 63; + svga->crtc[6] = 255; + svga->dispontime = 1000ull << 32; + svga->dispofftime = 1000ull << 32; + svga->bpp = 8; + + if (s3->pci) + svga->crtc[0x36] = 2 | (3 << 2) | (1 << 4); + else if (s3->vlb) + svga->crtc[0x36] = 1 | (3 << 2) | (1 << 4); + else + svga->crtc[0x36] = 3 | (1 << 4); + + if (s3->chip >= S3_86C928) + svga->crtc[0x36] |= (vram_sizes[s3->vram] << 5); + else + svga->crtc[0x36] |= ((s3->vram == 1) ? 0x00 : 0x20) | 0x80; + + svga->crtc[0x37] = 1 | (7 << 5); + + if (s3->chip >= S3_86C928) + svga->crtc[0x37] |= 0x04; + + s3_io_set(s3); + + memset(s3->pci_regs, 0x00, 256); + + s3->pci_regs[PCI_REG_COMMAND] = 7; + + s3->pci_regs[0x30] = 0x00; + s3->pci_regs[0x32] = 0x0c; + s3->pci_regs[0x33] = 0x00; + + switch(s3->card_type) { + case S3_MIROCRYSTAL8S_805: + case S3_MIROCRYSTAL10SD_805: + svga->crtc[0x5a] = 0x0a; + svga->getclock = sdac_getclock; + break; + + case S3_SPEA_MIRAGE_86C801: + case S3_SPEA_MIRAGE_86C805: + svga->crtc[0x5a] = 0x0a; + break; + + case S3_PHOENIX_86C801: + case S3_PHOENIX_86C805: + svga->crtc[0x5a] = 0x0a; + break; + + case S3_METHEUS_86C928: + svga->crtc[0x5a] = 0x0a; + break; + + case S3_PARADISE_BAHAMAS64: + case S3_PHOENIX_VISION864: + case S3_MIROCRYSTAL20SD_864: + svga->crtc[0x5a] = 0x0a; + break; + + case S3_DIAMOND_STEALTH64_964: + case S3_ELSAWIN2KPROX_964: + case S3_MIROCRYSTAL20SV_964: + svga->crtc[0x5a] = 0x0a; + break; + + case S3_ELSAWIN2KPROX: + case S3_SPEA_MERCURY_P64V: + case S3_MIROVIDEO40SV_ERGO_968: + case S3_PHOENIX_VISION968: + if (s3->pci) { + svga->crtc[0x53] = 0x18; + svga->crtc[0x58] = 0x10; + svga->crtc[0x59] = 0x70; + svga->crtc[0x5a] = 0x00; + svga->crtc[0x6c] = 1; + } else { + svga->crtc[0x53] = 0x00; + svga->crtc[0x59] = 0x00; + svga->crtc[0x5a] = 0x0a; + } + break; + + case S3_PHOENIX_VISION868: + if (s3->pci) { + svga->crtc[0x53] = 0x18; + svga->crtc[0x58] = 0x10; + svga->crtc[0x59] = 0x70; + svga->crtc[0x5a] = 0x00; + svga->crtc[0x6c] = 1; + } else { + svga->crtc[0x53] = 0x00; + svga->crtc[0x59] = 0x00; + svga->crtc[0x5a] = 0x0a; + } + break; + + case S3_PHOENIX_TRIO64: + case S3_PHOENIX_TRIO64_ONBOARD: + case S3_PHOENIX_TRIO64VPLUS: + case S3_PHOENIX_TRIO64VPLUS_ONBOARD: + case S3_DIAMOND_STEALTH64_764: + case S3_SPEA_MIRAGE_P64: + case S3_NUMBER9_9FX: + if (s3->card_type == S3_PHOENIX_TRIO64VPLUS || s3->card_type == S3_PHOENIX_TRIO64VPLUS_ONBOARD) + svga->crtc[0x53] = 0x08; + break; + + case S3_TRIO64V2_DX: + svga->crtc[0x53] = 0x08; + svga->crtc[0x59] = 0x70; + svga->crtc[0x5a] = 0x00; + svga->crtc[0x6c] = 1; + s3->pci_regs[0x05] = 0; + s3->pci_regs[0x06] = 0; + s3->pci_regs[0x07] = 2; + s3->pci_regs[0x3d] = 1; + s3->pci_regs[0x3e] = 4; + s3->pci_regs[0x3f] = 0xff; + break; + } + + if (s3->has_bios) { + if (s3->pci) + mem_mapping_disable(&s3->bios_rom.mapping); + } + + s3_updatemapping(s3); + + mem_mapping_disable(&s3->mmio_mapping); + mem_mapping_disable(&s3->new_mmio_mapping); +} + + static void *s3_init(const device_t *info) { const char *bios_fn; @@ -6608,6 +6751,7 @@ static void *s3_init(const device_t *info) else vram_size = 512 << 10; s3->vram_mask = vram_size - 1; + s3->vram = vram; s3->has_bios = (bios_fn != NULL); if (s3->has_bios) { @@ -7281,7 +7425,7 @@ const device_t s3_orchid_86c911_isa_device = S3_ORCHID_86C911, s3_init, s3_close, - NULL, + s3_reset, { s3_orchid_86c911_available }, s3_speed_changed, s3_force_redraw, @@ -7295,7 +7439,7 @@ const device_t s3_diamond_stealth_vram_isa_device = S3_DIAMOND_STEALTH_VRAM, s3_init, s3_close, - NULL, + s3_reset, { s3_diamond_stealth_vram_available }, s3_speed_changed, s3_force_redraw, @@ -7309,7 +7453,7 @@ const device_t s3_ami_86c924_isa_device = S3_AMI_86C924, s3_init, s3_close, - NULL, + s3_reset, { s3_ami_86c924_available }, s3_speed_changed, s3_force_redraw, @@ -7323,7 +7467,7 @@ const device_t s3_spea_mirage_86c801_isa_device = S3_SPEA_MIRAGE_86C801, s3_init, s3_close, - NULL, + s3_reset, { s3_spea_mirage_86c801_available }, s3_speed_changed, s3_force_redraw, @@ -7337,7 +7481,7 @@ const device_t s3_spea_mirage_86c805_vlb_device = S3_SPEA_MIRAGE_86C805, s3_init, s3_close, - NULL, + s3_reset, { s3_spea_mirage_86c805_available }, s3_speed_changed, s3_force_redraw, @@ -7351,7 +7495,7 @@ const device_t s3_mirocrystal_8s_805_vlb_device = S3_MIROCRYSTAL8S_805, s3_init, s3_close, - NULL, + s3_reset, { s3_mirocrystal_8s_805_available }, s3_speed_changed, s3_force_redraw, @@ -7366,7 +7510,7 @@ const device_t s3_mirocrystal_10sd_805_vlb_device = S3_MIROCRYSTAL10SD_805, s3_init, s3_close, - NULL, + s3_reset, { s3_mirocrystal_10sd_805_available }, s3_speed_changed, s3_force_redraw, @@ -7380,7 +7524,7 @@ const device_t s3_phoenix_86c801_isa_device = S3_PHOENIX_86C801, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_86c80x_available }, s3_speed_changed, s3_force_redraw, @@ -7394,7 +7538,7 @@ const device_t s3_phoenix_86c805_vlb_device = S3_PHOENIX_86C805, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_86c80x_available }, s3_speed_changed, s3_force_redraw, @@ -7408,7 +7552,7 @@ const device_t s3_metheus_86c928_isa_device = S3_METHEUS_86C928, s3_init, s3_close, - NULL, + s3_reset, { s3_metheus_86c928_available }, s3_speed_changed, s3_force_redraw, @@ -7422,7 +7566,7 @@ const device_t s3_metheus_86c928_vlb_device = S3_METHEUS_86C928, s3_init, s3_close, - NULL, + s3_reset, { s3_metheus_86c928_available }, s3_speed_changed, s3_force_redraw, @@ -7436,7 +7580,7 @@ const device_t s3_mirocrystal_20sd_864_vlb_device = S3_MIROCRYSTAL20SD_864, s3_init, s3_close, - NULL, + s3_reset, { s3_mirocrystal_20sd_864_vlb_available }, s3_speed_changed, s3_force_redraw, @@ -7450,7 +7594,7 @@ const device_t s3_bahamas64_vlb_device = S3_PARADISE_BAHAMAS64, s3_init, s3_close, - NULL, + s3_reset, { s3_bahamas64_available }, s3_speed_changed, s3_force_redraw, @@ -7464,7 +7608,7 @@ const device_t s3_bahamas64_pci_device = S3_PARADISE_BAHAMAS64, s3_init, s3_close, - NULL, + s3_reset, { s3_bahamas64_available }, s3_speed_changed, s3_force_redraw, @@ -7478,7 +7622,7 @@ const device_t s3_mirocrystal_20sv_964_vlb_device = S3_MIROCRYSTAL20SV_964, s3_init, s3_close, - NULL, + s3_reset, { s3_mirocrystal_20sv_964_vlb_available }, s3_speed_changed, s3_force_redraw, @@ -7492,7 +7636,7 @@ const device_t s3_mirocrystal_20sv_964_pci_device = S3_MIROCRYSTAL20SV_964, s3_init, s3_close, - NULL, + s3_reset, { s3_mirocrystal_20sv_964_pci_available }, s3_speed_changed, s3_force_redraw, @@ -7507,7 +7651,7 @@ const device_t s3_diamond_stealth64_964_vlb_device = S3_DIAMOND_STEALTH64_964, s3_init, s3_close, - NULL, + s3_reset, { s3_diamond_stealth64_964_available }, s3_speed_changed, s3_force_redraw, @@ -7521,7 +7665,7 @@ const device_t s3_diamond_stealth64_964_pci_device = S3_DIAMOND_STEALTH64_964, s3_init, s3_close, - NULL, + s3_reset, { s3_diamond_stealth64_964_available }, s3_speed_changed, s3_force_redraw, @@ -7535,7 +7679,7 @@ const device_t s3_phoenix_vision968_pci_device = S3_PHOENIX_VISION968, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_vision968_available }, s3_speed_changed, s3_force_redraw, @@ -7549,7 +7693,7 @@ const device_t s3_phoenix_vision968_vlb_device = S3_PHOENIX_VISION968, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_vision968_available }, s3_speed_changed, s3_force_redraw, @@ -7563,7 +7707,7 @@ const device_t s3_mirovideo_40sv_ergo_968_pci_device = S3_MIROVIDEO40SV_ERGO_968, s3_init, s3_close, - NULL, + s3_reset, { s3_mirovideo_40sv_ergo_968_pci_available }, s3_speed_changed, s3_force_redraw, @@ -7577,7 +7721,7 @@ const device_t s3_spea_mercury_p64v_pci_device = S3_SPEA_MERCURY_P64V, s3_init, s3_close, - NULL, + s3_reset, { s3_spea_mercury_p64v_pci_available }, s3_speed_changed, s3_force_redraw, @@ -7591,7 +7735,7 @@ const device_t s3_9fx_vlb_device = S3_NUMBER9_9FX, s3_init, s3_close, - NULL, + s3_reset, { s3_9fx_available }, s3_speed_changed, s3_force_redraw, @@ -7605,7 +7749,7 @@ const device_t s3_9fx_pci_device = S3_NUMBER9_9FX, s3_init, s3_close, - NULL, + s3_reset, { s3_9fx_available }, s3_speed_changed, s3_force_redraw, @@ -7619,7 +7763,7 @@ const device_t s3_phoenix_trio32_vlb_device = S3_PHOENIX_TRIO32, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_trio32_available }, s3_speed_changed, s3_force_redraw, @@ -7633,7 +7777,7 @@ const device_t s3_phoenix_trio32_pci_device = S3_PHOENIX_TRIO32, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_trio32_available }, s3_speed_changed, s3_force_redraw, @@ -7647,7 +7791,7 @@ const device_t s3_diamond_stealth_se_vlb_device = S3_DIAMOND_STEALTH_SE, s3_init, s3_close, - NULL, + s3_reset, { s3_diamond_stealth_se_available }, s3_speed_changed, s3_force_redraw, @@ -7661,7 +7805,7 @@ const device_t s3_diamond_stealth_se_pci_device = S3_DIAMOND_STEALTH_SE, s3_init, s3_close, - NULL, + s3_reset, { s3_diamond_stealth_se_available }, s3_speed_changed, s3_force_redraw, @@ -7676,7 +7820,7 @@ const device_t s3_phoenix_trio64_vlb_device = S3_PHOENIX_TRIO64, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_trio64_available }, s3_speed_changed, s3_force_redraw, @@ -7690,7 +7834,7 @@ const device_t s3_phoenix_trio64_onboard_pci_device = S3_PHOENIX_TRIO64_ONBOARD, s3_init, s3_close, - NULL, + s3_reset, { NULL }, s3_speed_changed, s3_force_redraw, @@ -7704,7 +7848,7 @@ const device_t s3_phoenix_trio64_pci_device = S3_PHOENIX_TRIO64, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_trio64_available }, s3_speed_changed, s3_force_redraw, @@ -7718,7 +7862,7 @@ const device_t s3_phoenix_trio64vplus_onboard_pci_device = S3_PHOENIX_TRIO64VPLUS_ONBOARD, s3_init, s3_close, - NULL, + s3_reset, { NULL }, s3_speed_changed, s3_force_redraw, @@ -7732,7 +7876,7 @@ const device_t s3_phoenix_trio64vplus_pci_device = S3_PHOENIX_TRIO64VPLUS, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_trio64vplus_available }, s3_speed_changed, s3_force_redraw, @@ -7746,7 +7890,7 @@ const device_t s3_phoenix_vision864_vlb_device = S3_PHOENIX_VISION864, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_vision864_available }, s3_speed_changed, s3_force_redraw, @@ -7760,7 +7904,7 @@ const device_t s3_phoenix_vision864_pci_device = S3_PHOENIX_VISION864, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_vision864_available }, s3_speed_changed, s3_force_redraw, @@ -7774,7 +7918,7 @@ const device_t s3_phoenix_vision868_vlb_device = S3_PHOENIX_VISION868, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_vision868_available }, s3_speed_changed, s3_force_redraw, @@ -7788,7 +7932,7 @@ const device_t s3_phoenix_vision868_pci_device = S3_PHOENIX_VISION868, s3_init, s3_close, - NULL, + s3_reset, { s3_phoenix_vision868_available }, s3_speed_changed, s3_force_redraw, @@ -7802,7 +7946,7 @@ const device_t s3_diamond_stealth64_vlb_device = S3_DIAMOND_STEALTH64_764, s3_init, s3_close, - NULL, + s3_reset, { s3_diamond_stealth64_764_available }, s3_speed_changed, s3_force_redraw, @@ -7816,7 +7960,7 @@ const device_t s3_diamond_stealth64_pci_device = S3_DIAMOND_STEALTH64_764, s3_init, s3_close, - NULL, + s3_reset, { s3_diamond_stealth64_764_available }, s3_speed_changed, s3_force_redraw, @@ -7830,7 +7974,7 @@ const device_t s3_spea_mirage_p64_vlb_device = S3_SPEA_MIRAGE_P64, s3_init, s3_close, - NULL, + s3_reset, { s3_spea_mirage_p64_vlb_available }, s3_speed_changed, s3_force_redraw, @@ -7844,7 +7988,7 @@ const device_t s3_elsa_winner2000_pro_x_964_pci_device = S3_ELSAWIN2KPROX_964, s3_init, s3_close, - NULL, + s3_reset, { s3_elsa_winner2000_pro_x_964_available }, s3_speed_changed, s3_force_redraw, @@ -7858,7 +8002,7 @@ const device_t s3_elsa_winner2000_pro_x_pci_device = S3_ELSAWIN2KPROX, s3_init, s3_close, - NULL, + s3_reset, { s3_elsa_winner2000_pro_x_available }, s3_speed_changed, s3_force_redraw, @@ -7872,7 +8016,7 @@ const device_t s3_trio64v2_dx_pci_device = S3_TRIO64V2_DX, s3_init, s3_close, - NULL, + s3_reset, { s3_trio64v2_dx_available }, s3_speed_changed, s3_force_redraw, diff --git a/src/video/vid_s3_virge.c b/src/video/vid_s3_virge.c index 43d26a559..c43a1c55a 100644 --- a/src/video/vid_s3_virge.c +++ b/src/video/vid_s3_virge.c @@ -301,7 +301,7 @@ typedef struct virge_t fifo_entry_t fifo[FIFO_SIZE]; volatile int fifo_read_idx, fifo_write_idx; - int virge_busy; + int virge_busy, local; uint8_t subsys_stat, subsys_cntl, advfunc_cntl; @@ -3785,6 +3785,86 @@ static void s3_virge_pci_write(int func, int addr, uint8_t val, void *p) } } +static void s3_virge_reset(void *priv) +{ + virge_t *virge = (virge_t *) priv; + svga_t *svga = &virge->svga; + + memset(svga->crtc, 0x00, sizeof(svga->crtc)); + svga->crtc[0] = 63; + svga->crtc[6] = 255; + svga->dispontime = 1000ull << 32; + svga->dispofftime = 1000ull << 32; + svga->bpp = 8; + + io_removehandler(0x03c0, 0x0020, s3_virge_in, NULL, NULL, s3_virge_out, NULL, NULL, virge); + io_sethandler(0x03c0, 0x0020, s3_virge_in, NULL, NULL, s3_virge_out, NULL, NULL, virge); + + memset(virge->pci_regs, 0x00, 256); + + virge->pci_regs[PCI_REG_COMMAND] = 3; + virge->pci_regs[0x05] = 0; + virge->pci_regs[0x06] = 0; + virge->pci_regs[0x07] = 2; + virge->pci_regs[0x32] = 0x0c; + virge->pci_regs[0x3d] = 1; + virge->pci_regs[0x3e] = 4; + virge->pci_regs[0x3f] = 0xff; + + switch(virge->local) { + case S3_VIRGE_325: + case S3_DIAMOND_STEALTH3D_2000: + virge->svga.crtc[0x59] = 0x70; + break; + case S3_DIAMOND_STEALTH3D_3000: + virge->svga.crtc[0x59] = 0x70; + break; + case S3_VIRGE_GX2: + case S3_DIAMOND_STEALTH3D_4000: + virge->svga.crtc[0x6c] = 1; + virge->svga.crtc[0x59] = 0x70; + break; + + case S3_TRIO_3D2X: + virge->svga.crtc[0x6c] = 1; + virge->svga.crtc[0x59] = 0x70; + break; + + default: + virge->svga.crtc[0x6c] = 1; + virge->svga.crtc[0x59] = 0x70; + break; + } + + if (virge->chip >= S3_VIRGEGX2) + virge->svga.crtc[0x36] = 2 | (0 << 2) | (1 << 4) | (0 << 5); + else { + switch (virge->memory_size) { + case 2: + virge->svga.crtc[0x36] = 2 | (0 << 2) | (1 << 4) | (4 << 5); + break; + case 8: + virge->svga.crtc[0x36] = 2 | (0 << 2) | (1 << 4) | (3 << 5); + break; + case 4: + virge->svga.crtc[0x36] = 2 | (0 << 2) | (1 << 4) | (0 << 5); + break; + } + } + + virge->svga.crtc[0x37] = 1 | (7 << 5); + virge->svga.crtc[0x53] = 8; + + mem_mapping_disable(&virge->bios_rom.mapping); + + memset(virge->dmabuffer, 0, 65536); + + s3_virge_updatemapping(virge); + + mem_mapping_disable(&virge->mmio_mapping); + mem_mapping_disable(&virge->new_mmio_mapping); +} + static void *s3_virge_init(const device_t *info) { const char *bios_fn; @@ -3990,6 +4070,8 @@ static void *s3_virge_init(const device_t *info) virge->render_thread = thread_create(render_thread, virge); timer_add(&virge->tri_timer, s3_virge_tri_timer, virge, 0); + + virge->local = info->local; return virge; } @@ -4119,7 +4201,7 @@ const device_t s3_virge_325_pci_device = S3_VIRGE_325, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_virge_325_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4133,7 +4215,7 @@ const device_t s3_diamond_stealth_2000_pci_device = S3_DIAMOND_STEALTH3D_2000, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_virge_325_diamond_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4147,7 +4229,7 @@ const device_t s3_diamond_stealth_3000_pci_device = S3_DIAMOND_STEALTH3D_3000, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_virge_988_diamond_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4161,7 +4243,7 @@ const device_t s3_virge_375_pci_device = S3_VIRGE_DX, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_virge_375_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4175,7 +4257,7 @@ const device_t s3_diamond_stealth_2000pro_pci_device = S3_DIAMOND_STEALTH3D_2000PRO, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_virge_375_diamond_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4189,7 +4271,7 @@ const device_t s3_virge_385_pci_device = S3_VIRGE_GX, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_virge_385_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4203,7 +4285,7 @@ const device_t s3_virge_357_pci_device = S3_VIRGE_GX2, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_virge_357_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4217,7 +4299,7 @@ const device_t s3_virge_357_agp_device = S3_VIRGE_GX2, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_virge_357_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4231,7 +4313,7 @@ const device_t s3_diamond_stealth_4000_pci_device = S3_DIAMOND_STEALTH3D_4000, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_virge_357_diamond_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4245,7 +4327,7 @@ const device_t s3_diamond_stealth_4000_agp_device = S3_DIAMOND_STEALTH3D_4000, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_virge_357_diamond_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4259,7 +4341,7 @@ const device_t s3_trio3d2x_pci_device = S3_TRIO_3D2X, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_trio3d2x_available }, s3_virge_speed_changed, s3_virge_force_redraw, @@ -4273,7 +4355,7 @@ const device_t s3_trio3d2x_agp_device = S3_TRIO_3D2X, s3_virge_init, s3_virge_close, - NULL, + s3_virge_reset, { s3_trio3d2x_available }, s3_virge_speed_changed, s3_virge_force_redraw,