From 68e22e0c6de6116ee300d8cd10b098b92a5367d0 Mon Sep 17 00:00:00 2001
From: Panagiotis <58827426+tiseno100@users.noreply.github.com>
Date: Tue, 16 Mar 2021 10:24:36 +0200
Subject: [PATCH] Hardcode cache size of the UMC HB4 to 512KB

Fixes Cache freeze issue on the HOT-433A.
---
 src/chipset/umc_hb4.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/chipset/umc_hb4.c b/src/chipset/umc_hb4.c
index 1bda69cd0..2cc4f5582 100644
--- a/src/chipset/umc_hb4.c
+++ b/src/chipset/umc_hb4.c
@@ -29,7 +29,6 @@ Basic Reverse engineering effort was done personally by me
 TODO:
 - APM, SMM, SMRAM registers(Did some early work. Still quite incomplete)
 - More Appropriate Bitmasking(If it's even possible)
-- Shuttle HOT-433 freezes if cache is enabled! Proper checking must be done.
 
 Warning: Register documentation may be inaccurate!
 
@@ -46,6 +45,7 @@ Bit 5-4 Cache Speed
     1 1 Read 2-1-1-1 Write 2T
 
 Bit 3 Cache Banks (0: 1 Bank / 1: 2 Banks)
+
 Bit 2-1-0 Cache Size
     0 0 0 0KB
     0 0 1 64KB
@@ -203,8 +203,8 @@ um8881_write(int func, int addr, uint8_t val, void *priv)
         switch (addr)
         {
         case 0x50:
-            dev->pci_conf[addr] = val;
-            cpu_cache_ext_enabled = !!(val & 0x80);
+            dev->pci_conf[addr] = ((val & 0xf8) | 4); /* Hardcode Cache Size to 512KB */
+            cpu_cache_ext_enabled = !!(val & 0x80);   /* Fixes freezing issues on the HOT-433A*/
             cpu_update_waitstates();
             break;