Fixed a condition in write to CR0.
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@@ -187,7 +187,7 @@ opMOV_CRx_r_a16(uint32_t fetchdat)
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
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flushmmucache();
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flushmmucache();
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else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
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else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
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if (is_p6 && !cpu_use_dynarec)
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if (is_p6 || cpu_use_dynarec)
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flushmmucache();
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flushmmucache();
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else
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else
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cpu_flush_pending = 1;
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cpu_flush_pending = 1;
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@@ -253,7 +253,7 @@ opMOV_CRx_r_a32(uint32_t fetchdat)
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
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flushmmucache();
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flushmmucache();
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else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
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else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
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if (is_p6 && !cpu_use_dynarec)
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if (is_p6 || cpu_use_dynarec)
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flushmmucache();
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flushmmucache();
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else
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else
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cpu_flush_pending = 1;
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cpu_flush_pending = 1;
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