80486DX2-66/86Box-fork
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The Matrox code now actually uses the DMA bus master API instead of directly accessing the RAM array.

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OBattler
2020-06-07 07:21:27 +02:00
parent c7bce543b0
commit 6b884112fa
1 changed files with 10 additions and 7 deletions
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17
src/video/vid_mga.c
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@@ -25,6 +25,7 @@
#include <86box/pci.h> #include <86box/pci.h>
#include <86box/rom.h> #include <86box/rom.h>
#include <86box/device.h> #include <86box/device.h>
#include <86box/dma.h>
#include <86box/plat.h> #include <86box/plat.h>
#include <86box/video.h> #include <86box/video.h>
#include <86box/vid_svga.h> #include <86box/vid_svga.h>
@@ -2233,14 +2234,14 @@ run_dma(mystique_t *mystique)
switch (mystique->dma.primaddress & DMA_MODE_MASK) { switch (mystique->dma.primaddress & DMA_MODE_MASK) {
case DMA_MODE_REG: case DMA_MODE_REG:
if (mystique->dma.pri_state == 0) { if (mystique->dma.pri_state == 0) {
mystique->dma.pri_header = *(uint32_t *)&ram[mystique->dma.primaddress & DMA_ADDR_MASK]; dma_bm_read(mystique->dma.primaddress & DMA_ADDR_MASK, (uint8_t *) &mystique->dma.pri_header, 4, 4);
mystique->dma.primaddress += 4; mystique->dma.primaddress += 4;
} }
if ((mystique->dma.pri_header & 0xff) != 0x15) { if ((mystique->dma.pri_header & 0xff) != 0x15) {
uint32_t val = *(uint32_t *)&ram[mystique->dma.primaddress & DMA_ADDR_MASK]; uint32_t val, reg_addr;
uint32_t reg_addr;
dma_bm_read(mystique->dma.primaddress & DMA_ADDR_MASK, (uint8_t *) &val, 4, 4);
mystique->dma.primaddress += 4; mystique->dma.primaddress += 4;
reg_addr = (mystique->dma.pri_header & 0x7f) << 2; reg_addr = (mystique->dma.pri_header & 0x7f) << 2;
@@ -2276,13 +2277,13 @@ run_dma(mystique_t *mystique)
switch (mystique->dma.secaddress & DMA_MODE_MASK) { switch (mystique->dma.secaddress & DMA_MODE_MASK) {
case DMA_MODE_REG: case DMA_MODE_REG:
if (mystique->dma.sec_state == 0) { if (mystique->dma.sec_state == 0) {
mystique->dma.sec_header = *(uint32_t *)&ram[mystique->dma.secaddress & DMA_ADDR_MASK]; dma_bm_read(mystique->dma.secaddress & DMA_ADDR_MASK, (uint8_t *) &mystique->dma.sec_header, 4, 4);
mystique->dma.secaddress += 4; mystique->dma.secaddress += 4;
} }
uint32_t val = *(uint32_t *)&ram[mystique->dma.secaddress & DMA_ADDR_MASK]; uint32_t val, reg_addr;
uint32_t reg_addr;
dma_bm_read(mystique->dma.secaddress & DMA_ADDR_MASK, (uint8_t *) &val, 4, 4);
mystique->dma.secaddress += 4; mystique->dma.secaddress += 4;
reg_addr = (mystique->dma.sec_header & 0x7f) << 2; reg_addr = (mystique->dma.sec_header & 0x7f) << 2;
@@ -2310,7 +2311,9 @@ run_dma(mystique_t *mystique)
break; break;
case DMA_MODE_BLIT: { case DMA_MODE_BLIT: {
uint32_t val = *(uint32_t *)&ram[mystique->dma.secaddress & DMA_ADDR_MASK]; uint32_t val;
dma_bm_read(mystique->dma.secaddress & DMA_ADDR_MASK, (uint8_t *) &val, 4, 4);
mystique->dma.secaddress += 4; mystique->dma.secaddress += 4;
if (mystique->busy) if (mystique->busy)