From aa73f2215f94184e32ec891d2854a4f53e6ce290 Mon Sep 17 00:00:00 2001 From: Melissa Goad Date: Sat, 11 Jan 2020 18:06:57 -0600 Subject: [PATCH 1/4] Preliminary port of PCem's FIC VA-503P motherboard --- src/chipset/chipset.h | 5 + src/chipset/via_mvp3.c | 295 +++++++++++++++++++++ src/machine/m_at_socket7_s7.c | 38 ++- src/machine/machine.h | 4 + src/machine/machine_table_new.c | 4 + src/sst_flash.c | 301 ++++++++++++++++++++++ src/sst_flash.h | 19 ++ src/via_mvp3_sb.c | 444 ++++++++++++++++++++++++++++++++ src/via_mvp3_sb.h | 22 ++ src/win/Makefile_ndr.mingw | 11 + 10 files changed, 1141 insertions(+), 2 deletions(-) create mode 100644 src/chipset/via_mvp3.c create mode 100644 src/sst_flash.c create mode 100644 src/sst_flash.h create mode 100644 src/via_mvp3_sb.c create mode 100644 src/via_mvp3_sb.h diff --git a/src/chipset/chipset.h b/src/chipset/chipset.h index bf2cda160..50f3536f7 100644 --- a/src/chipset/chipset.h +++ b/src/chipset/chipset.h @@ -61,6 +61,11 @@ extern const device_t sis_85c496_device; extern const device_t sis_85c50x_device; #endif +#if defined(DEV_BRANCH) && defined(USE_SS7) +/* VIA */ +extern const device_t via_mvp3_device; +#endif + /* WD */ extern const device_t wd76c10_device; diff --git a/src/chipset/via_mvp3.c b/src/chipset/via_mvp3.c new file mode 100644 index 000000000..dfeba12c2 --- /dev/null +++ b/src/chipset/via_mvp3.c @@ -0,0 +1,295 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of the VIA MVP3 chip. + * + * Version: @(#)via_mvp3.c 1.0.1 2019/10/19 + * + * Authors: Sarah Walker, + * Miran Grca, + * Melissa Goad, + * + * Copyright 2020 Miran Grca, Melissa Goad. + */ +#include +#include +#include +#include +#include +#include "../86box.h" +#include "../mem.h" +#include "../io.h" +#include "../rom.h" +#include "../pci.h" +#include "../device.h" +#include "../keyboard.h" +#include "chipset.h" + +typedef struct via_mvp3_t +{ + uint8_t pci_conf[2][256]; +} via_mvp3_t; + +static void +via_mvp3_recalcmapping(via_mvp3_t *dev) +{ + int c, d; + uint32_t base; + + for (c = 0; c < 2; c++) { + for (d = 0; d < 4; d++) { + base = 0xc0000 + (d << 14); + switch (dev->pci_conf[0][0x61 + c] & (3 << (d << 1))) { + case 0x00: + mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 0x01: + mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 0x02: + mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 0x03: + mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + } + } + } + + for(d = 0; d < 2; d++) + { + base = 0xe0000 + (d << 16); + switch (dev->pci_conf[0][0x63] & (3 << (d << 1))) { + case 0x00: + mem_set_mem_state(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 0x01: + mem_set_mem_state(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 0x02: + mem_set_mem_state(base, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 0x03: + mem_set_mem_state(base, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + } + } + + flushmmucache_nopc(); + shadowbios = 1; +} + +static void +via_mvp3_setup(via_mvp3_t *dev) +{ + memset(dev, 0, sizeof(via_mvp3_t)); + + /* Host Bridge */ + dev->pci_conf[0][0x00] = 0x06; /*VIA*/ + dev->pci_conf[0][0x01] = 0x11; + dev->pci_conf[0][0x02] = 0x98; /*VT82C598MVP*/ + dev->pci_conf[0][0x03] = 0x05; + + dev->pci_conf[0][0x04] = 6; + dev->pci_conf[0][0x05] = 0; + + dev->pci_conf[0][0x06] = 0x90; + dev->pci_conf[0][0x07] = 0x02; + + dev->pci_conf[0][0x09] = 0; + dev->pci_conf[0][0x0a] = 0; + dev->pci_conf[0][0x0b] = 6; + dev->pci_conf[0][0x0c] = 0; + dev->pci_conf[0][0x0d] = 0; + dev->pci_conf[0][0x0e] = 0; + dev->pci_conf[0][0x0f] = 0; + dev->pci_conf[0][0x10] = 0x08; + dev->pci_conf[0][0x34] = 0xa0; + + dev->pci_conf[0][0x5a] = 0x01; + dev->pci_conf[0][0x5b] = 0x01; + dev->pci_conf[0][0x5c] = 0x01; + dev->pci_conf[0][0x5d] = 0x01; + dev->pci_conf[0][0x5e] = 0x01; + dev->pci_conf[0][0x5f] = 0x01; + + dev->pci_conf[0][0x64] = 0xec; + dev->pci_conf[0][0x65] = 0xec; + dev->pci_conf[0][0x66] = 0xec; + dev->pci_conf[0][0x6b] = 0x01; + + dev->pci_conf[0][0xa0] = 0x02; + dev->pci_conf[0][0xa2] = 0x10; + dev->pci_conf[0][0xa4] = 0x03; + dev->pci_conf[0][0xa5] = 0x02; + dev->pci_conf[0][0xa7] = 0x07; + + /* PCI-to-PCI Bridge */ + + dev->pci_conf[1][0x00] = 0x06; /*VIA*/ + dev->pci_conf[1][0x01] = 0x11; + dev->pci_conf[1][0x02] = 0x98; /*VT82C598MVP*/ + dev->pci_conf[1][0x03] = 0x85; + + dev->pci_conf[1][0x04] = 7; + dev->pci_conf[1][0x05] = 0; + + dev->pci_conf[1][0x06] = 0x20; + dev->pci_conf[1][0x07] = 0x02; + + dev->pci_conf[1][0x09] = 0; + dev->pci_conf[1][0x0a] = 4; + dev->pci_conf[1][0x0b] = 6; + dev->pci_conf[1][0x0c] = 0; + dev->pci_conf[1][0x0d] = 0; + dev->pci_conf[1][0x0e] = 1; + dev->pci_conf[1][0x0f] = 0; + + dev->pci_conf[1][0x1c] = 0xf0; + + dev->pci_conf[1][0x20] = 0xf0; + dev->pci_conf[1][0x21] = 0xff; + dev->pci_conf[1][0x24] = 0xf0; + dev->pci_conf[1][0x25] = 0xff; +} + +static void +via_mvp3_host_bridge_write(int func, int addr, uint8_t val, void *priv) +{ + via_mvp3_t *dev = (via_mvp3_t *) priv; + + if (func) + return; + + /*Read-only addresses*/ + if ((addr < 4) || (addr >= 5 && addr < 7) + || (addr >= 8 && addr < 0xd) + || (addr >= 0xe && addr < 0x12) + || (addr >= 0x14 && addr < 0x50) + || (addr >= 0x79 && addr < 0x7e) + || (addr >= 0x85 && addr < 0x88) + || (addr >= 0x8c && addr < 0xa8) + || (addr >= 0xad && addr < 0xfd)) + return; + + switch(addr) + { + case 0x04: + dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40); + break; + case 0x07: + dev->pci_conf[0][0x07] &= ~(val & 0xb0); + case 0x61: case 0x62: case 0x63: + dev->pci_conf[0][addr] = val; + via_mvp3_recalcmapping(dev); + break; + default: + dev->pci_conf[0][addr] = val; + break; + } +} + +static void +via_mvp3_pci_bridge_write(int func, int addr, uint8_t val, void *priv) +{ + via_mvp3_t *dev = (via_mvp3_t *) priv; + + if(func != 1) return; + + /*Read-only addresses*/ + + if ((addr < 4) || (addr >= 5 && addr < 7) + || (addr >= 8 && addr < 0x18) + || (addr == 0x1b) + || (addr >= 0x1e && addr < 0x20) + || (addr >= 0x28 && addr < 0x3e) + || (addr >= 0x43)) + return; + + switch(addr) + { + case 0x04: + dev->pci_conf[1][0x04] = (dev->pci_conf[1][0x04] & ~0x47) | (val & 0x47); + break; + case 0x07: + dev->pci_conf[1][0x07] &= ~(val & 0x30); + default: + dev->pci_conf[1][addr] = val; + break; + } +} + +static uint8_t +via_mvp3_read(int func, int addr, void *priv) +{ + via_mvp3_t *dev = (via_mvp3_t *) priv; + + switch(func) + { + case 0: return dev->pci_conf[0][addr]; + case 1: return dev->pci_conf[1][addr]; + default: return 0xff; + } +} + + +static void +via_mvp3_write(int func, int addr, uint8_t val, void *priv) +{ + switch(func) + { + case 0: + via_mvp3_host_bridge_write(func, addr, val, priv); + break; + case 1: + via_mvp3_pci_bridge_write(func, addr, val, priv); + break; + } +} + +static void +via_mvp3_reset(void *priv) +{ + via_mvp3_t *dev = (via_mvp3_t *) priv; + + via_mvp3_setup(dev); +} + +static void * +via_mvp3_init(const device_t *info) +{ + via_mvp3_t *dev = (via_mvp3_t *) malloc(sizeof(via_mvp3_t)); + + pci_add_card(0, via_mvp3_read, via_mvp3_write, dev); + + via_mvp3_setup(dev); + + return dev; +} + +static void +via_mvp3_close(void *priv) +{ + via_mvp3_t *dev = (via_mvp3_t *) priv; + + free(dev); +} + +const device_t via_mvp3_device = +{ + "VIA MVP3", + DEVICE_PCI, + 0, + via_mvp3_init, + via_mvp3_close, + via_mvp3_reset, + NULL, + NULL, + NULL, + NULL +}; diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c index 377a37bd5..9dfd1515a 100644 --- a/src/machine/m_at_socket7_s7.c +++ b/src/machine/m_at_socket7_s7.c @@ -12,9 +12,11 @@ * * Authors: Sarah Walker, * Miran Grca, + * Melissa Goad, * - * Copyright 2010-2019 Sarah Walker. - * Copyright 2016-2019 Miran Grca. + * Copyright 2010-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. + * Copyright 2020 Melissa Goad. */ #include #include @@ -35,6 +37,8 @@ #include "../intel_sio.h" #include "../piix.h" #include "../sio.h" +#include "../sst_flash.h" +#include "../via_mvp3_sb.h" #include "../video/video.h" #include "../video/vid_cl54xx.h" #include "../video/vid_s3.h" @@ -451,3 +455,33 @@ machine_at_j656vxd_init(const machine_t *model) return ret; } + +#if defined(DEV_BRANCH) && defined(USE_SS7) +int +machine_at_mvp3_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/ficva503p/je4333.bin", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0a, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0); + device_add(&via_mvp3_device); + device_add(&via_mvp3_sb_device); + device_add(&keyboard_ps2_pci_device); + device_add(&w83877tf_device); + device_add(&sst_flash_39sf010_device); + + return ret; +} +#endif \ No newline at end of file diff --git a/src/machine/machine.h b/src/machine/machine.h index 7d4b52ab7..fdbc4bbe1 100644 --- a/src/machine/machine.h +++ b/src/machine/machine.h @@ -276,6 +276,10 @@ extern int machine_at_i430vx_init(const machine_t *); extern int machine_at_p55va_init(const machine_t *); extern int machine_at_j656vxd_init(const machine_t *); +#if defined(DEV_BRANCH) && defined(USE_SS7) +extern int machine_at_mvp3_init(const machine_t *); +#endif + #ifdef EMU_DEVICE_H extern const device_t *at_pb640_get_device(void); #endif diff --git a/src/machine/machine_table_new.c b/src/machine/machine_table_new.c index a46e7175c..c9ae1d598 100644 --- a/src/machine/machine_table_new.c +++ b/src/machine/machine_table_new.c @@ -192,6 +192,10 @@ const machine_t machines[] = { { "[Socket 7 VX] Jetway J656VXD", "j656vxd", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_j656vxd_init, NULL }, { "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL }, +#if defined(DEV_BRANCH) && defined(USE_SS7) + { "[Super Socket 7] FIC VA503P", "ficva503p", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_mvp3_init, NULL }, +#endif + #if defined(DEV_BRANCH) && defined(USE_I686) { "[Socket 8 FX] Tyan Titan-Pro AT", "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_i440fx_init, NULL }, { "[Socket 8 FX] Tyan Titan-Pro ATX", "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL }, diff --git a/src/sst_flash.c b/src/sst_flash.c new file mode 100644 index 000000000..b5666659f --- /dev/null +++ b/src/sst_flash.c @@ -0,0 +1,301 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of an SST flash chip. + * + * Version: @(#)sst_flash.c 1.0.19 2019/06/25 + * + * Authors: Sarah Walker, + * Miran Grca, + * Melissa Goad, + * + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. + * Copyright 2020 Melissa Goad. + */ +#include +#include +#include +#include +#include +#include "86box.h" +#include "device.h" +#include "mem.h" +#include "machine/machine.h" +#include "timer.h" +#include "nvr.h" +#include "plat.h" + +typedef struct sst_t +{ + int command_state, id_mode, + erase, dirty; + + uint8_t *array; + + mem_mapping_t mapping[2], mapping_h[2]; +} sst_t; + + +static wchar_t flash_path[1024]; + + +#define SST_CHIP_ERASE 0x10 +#define SST_SECTOR_ERASE 0x30 +#define SST_ERASE 0x80 +#define SST_SET_ID_MODE 0x90 +#define SST_BYTE_PROGRAM 0xa0 +#define SST_CLEAR_ID_MODE 0xf0 + + +static void +sst_new_command(sst_t *dev, uint8_t val) +{ + switch (val) { + case SST_CHIP_ERASE: + if (dev->erase) + memset(dev->array, 0xff, 0x20000); + dev->command_state = 0; + dev->erase = 0; + break; + + case SST_ERASE: + dev->command_state = 0; + dev->erase = 1; + break; + + case SST_SET_ID_MODE: + if (!dev->id_mode) + dev->id_mode = 1; + dev->command_state = 0; + dev->erase = 0; + break; + + case SST_BYTE_PROGRAM: + dev->command_state = 3; + dev->erase = 0; + break; + + case SST_CLEAR_ID_MODE: + if (dev->id_mode) + dev->id_mode = 0; + dev->command_state = 0; + dev->erase = 0; + break; + + default: + dev->command_state = 0; + dev->erase = 0; + } +} + + +static void +sst_sector_erase(sst_t *dev, uint32_t addr) +{ + memset(&dev->array[addr & 0x1f000], 0xff, 4096); + dev->dirty = 1; +} + + +static uint8_t +sst_read_id(uint32_t addr, void *p) +{ + if ((addr & 0xffff) == 0) + return 0xbf; /* SST */ + else if ((addr & 0xffff) == 1) + return 0xb5; /* 39SF010 */ + else + return 0xff; +} + + +static void +sst_write(uint32_t addr, uint8_t val, void *p) +{ + sst_t *dev = (sst_t *) p; + + switch (dev->command_state) { + case 0: + if (val == 0xf0) { + if (dev->id_mode) + dev->id_mode = 0; + } else if ((addr & 0xffff) == 0x5555 && val == 0xaa) + dev->command_state = 1; + else + dev->command_state = 0; + break; + case 1: + if ((addr & 0xffff) == 0x2aaa && val == 0x55) + dev->command_state = 2; + else + dev->command_state = 0; + break; + case 2: + if ((addr & 0xffff) == 0x5555) + sst_new_command(dev, val); + else if ((val == SST_SECTOR_ERASE) && dev->erase) { + sst_sector_erase(dev, addr); + dev->command_state = 0; + } else + dev->command_state = 0; + break; + case 3: + dev->array[addr & 0x1ffff] = val; + dev->command_state = 0; + dev->dirty = 1; + break; + } +} + + +static uint8_t +sst_read(uint32_t addr, void *p) +{ + sst_t *dev = (sst_t *) p; + uint8_t ret = 0xff; + + addr &= 0x000fffff; + + if (dev->id_mode) + ret = sst_read_id(addr, p); + else { + if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) + ret = dev->array[addr - biosaddr]; + } + + return ret; +} + + +static uint16_t +sst_readw(uint32_t addr, void *p) +{ + sst_t *dev = (sst_t *) p; + uint16_t ret = 0xffff; + + addr &= 0x000fffff; + + if (dev->id_mode) + ret = sst_read(addr, p) | (sst_read(addr + 1, p) << 8); + else { + if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) + ret = *(uint16_t *)&dev->array[addr - biosaddr]; + } + + return ret; +} + + +static uint32_t +sst_readl(uint32_t addr, void *p) +{ + sst_t *dev = (sst_t *) p; + uint32_t ret = 0xffffffff; + + addr &= 0x000fffff; + + if (dev->id_mode) + ret = sst_readw(addr, p) | (sst_readw(addr + 2, p) << 16); + else { + if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask))) + ret = *(uint32_t *)&dev->array[addr - biosaddr]; + } + + return ret; +} + + +static void +sst_add_mappings(sst_t *dev) +{ + int max = 2, i = 0; + uint32_t base, fbase; + + for (i = 0; i < 2; i++) { + base = 0xe0000 + (i << 16); + fbase = base & biosmask; + + memcpy(&dev->array[fbase], &rom[base & biosmask], 0x10000); + + mem_mapping_add(&(dev->mapping[i]), base, 0x10000, + sst_read, sst_readw, sst_readl, + sst_write, NULL, NULL, + dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROMCS, (void *) dev); + mem_mapping_add(&(dev->mapping_h[i]), (base | 0xfff00000) - 0x40000, 0x10000, + sst_read, sst_readw, sst_readl, + sst_write, NULL, NULL, + dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROMCS, (void *) dev); + } +} + + +static void * +sst_39sf010_init(const device_t *info) +{ + FILE *f; + sst_t *dev = malloc(sizeof(sst_t)); + memset(dev, 0, sizeof(sst_t)); + + size_t l = strlen(machine_get_internal_name_ex(machine))+1; + wchar_t *machine_name = (wchar_t *) malloc(l * sizeof(wchar_t)); + mbstowcs(machine_name, machine_get_internal_name_ex(machine), l); + l = wcslen(machine_name)+5; + wchar_t *flash_name = (wchar_t *)malloc(l*sizeof(wchar_t)); + swprintf(flash_name, l, L"%ls.bin", machine_name); + + wcscpy(flash_path, flash_name); + + mem_mapping_disable(&bios_mapping); + mem_mapping_disable(&bios_high_mapping); + + dev->array = (uint8_t *) malloc(biosmask + 1); + memset(dev->array, 0xff, biosmask + 1); + + sst_add_mappings(dev); + + f = nvr_fopen(flash_path, L"rb"); + if (f) { + fread(&(dev->array[0x00000]), 0x20000, 1, f); + fclose(f); + } + + free(flash_name); + free(machine_name); + + return dev; +} + + +static void +sst_39sf010_close(void *p) +{ + FILE *f; + sst_t *dev = (sst_t *)p; + + f = nvr_fopen(flash_path, L"wb"); + fwrite(&(dev->array[0x00000]), 0x20000, 1, f); + fclose(f); + + free(dev->array); + dev->array = NULL; + + free(dev); +} + + +const device_t sst_flash_39sf010_device = +{ + "SST 39SF010 Flash BIOS", + 0, + 0, + sst_39sf010_init, + sst_39sf010_close, + NULL, + NULL, NULL, NULL, NULL +}; \ No newline at end of file diff --git a/src/sst_flash.h b/src/sst_flash.h new file mode 100644 index 000000000..f919e73d1 --- /dev/null +++ b/src/sst_flash.h @@ -0,0 +1,19 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of an SST flash chip. + * + * Version: @(#)sst_flash.h 1.0.2 2019/06/25 + * + * Author: Melissa Goad, + * Copyright 2020 Melissa Goad. + */ + +#if defined(DEV_BRANCH) && defined(USE_SS7) +extern const device_t sst_flash_39sf010_device; +#endif \ No newline at end of file diff --git a/src/via_mvp3_sb.c b/src/via_mvp3_sb.c new file mode 100644 index 000000000..1fa42889c --- /dev/null +++ b/src/via_mvp3_sb.c @@ -0,0 +1,444 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * Emulation of the VIA Apollo MVP3 southbridge + * + * Version: @(#)via_mvp3_sb.c 1.0.22 2018/10/31 + * + * Authors: Sarah Walker, + * Miran Grca, + * Melissa Goad, + * + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. + * Copyright 2020 Melissa Goad. + */ + +#include +#include +#include +#include +#include +#include +#define HAVE_STDARG_H +#include "86box.h" +#include "cdrom/cdrom.h" +#include "cpu/cpu.h" +#include "scsi/scsi_device.h" +#include "scsi/scsi_cdrom.h" +#include "dma.h" +#include "io.h" +#include "device.h" +#include "apm.h" +#include "keyboard.h" +#include "mem.h" +#include "pci.h" +#include "pic.h" +#include "port_92.h" +#include "disk/hdc.h" +#include "disk/hdc_ide.h" +#include "disk/hdc_ide_sff8038i.h" +#include "disk/zip.h" +#include "machine/machine.h" +#include "via_mvp3_sb.h" + +typedef struct +{ + uint8_t pci_isa_regs[256]; + uint8_t ide_regs[256]; + uint8_t usb_regs[256]; + uint8_t power_regs[256]; + sff8038i_t *bm[2]; +} via_mvp3_sb_t; + +static void +via_mvp3_sb_reset_hard(void *priv) +{ + via_mvp3_sb_t *via_mvp3_sb = (via_mvp3_sb_t *) priv; + + uint16_t old_base = (via_mvp3_sb->ide_regs[0x20] & 0xf0) | (via_mvp3_sb->ide_regs[0x21] << 8); + + sff_bus_master_reset(via_mvp3_sb->bm[0], old_base); + sff_bus_master_reset(via_mvp3_sb->bm[1], old_base + 8); + + memset(via_mvp3_sb->pci_isa_regs, 0, 256); + memset(via_mvp3_sb->ide_regs, 0, 256); + memset(via_mvp3_sb->usb_regs, 0, 256); + memset(via_mvp3_sb->power_regs, 0, 256); + + via_mvp3_sb->pci_isa_regs[0x00] = 0x06; via_mvp3_sb->pci_isa_regs[0x01] = 0x11; /*VIA*/ + via_mvp3_sb->pci_isa_regs[0x02] = 0x86; via_mvp3_sb->pci_isa_regs[0x03] = 0x05; /*VT82C586B*/ + via_mvp3_sb->pci_isa_regs[0x04] = 0x0f; + via_mvp3_sb->pci_isa_regs[0x07] = 0x02; + via_mvp3_sb->pci_isa_regs[0x0a] = 0x01; + via_mvp3_sb->pci_isa_regs[0x0b] = 0x06; + via_mvp3_sb->pci_isa_regs[0x0e] = 0x80; + + via_mvp3_sb->pci_isa_regs[0x48] = 0x01; + via_mvp3_sb->pci_isa_regs[0x4a] = 0x04; + via_mvp3_sb->pci_isa_regs[0x4f] = 0x03; + + via_mvp3_sb->pci_isa_regs[0x50] = 0x24; + via_mvp3_sb->pci_isa_regs[0x59] = 0x04; + + //IDE registers + via_mvp3_sb->ide_regs[0x00] = 0x06; via_mvp3_sb->ide_regs[0x01] = 0x11; /*VIA*/ + via_mvp3_sb->ide_regs[0x02] = 0x71; via_mvp3_sb->ide_regs[0x03] = 0x05; /*VT82C586B*/ + via_mvp3_sb->ide_regs[0x04] = 0x80; + via_mvp3_sb->ide_regs[0x06] = 0x80; via_mvp3_sb->ide_regs[0x07] = 0x02; + via_mvp3_sb->ide_regs[0x09] = 0x85; + via_mvp3_sb->ide_regs[0x0a] = 0x01; + via_mvp3_sb->ide_regs[0x0b] = 0x01; + + via_mvp3_sb->ide_regs[0x10] = 0xf0; via_mvp3_sb->ide_regs[0x11] = 0x01; + via_mvp3_sb->ide_regs[0x14] = 0xf4; via_mvp3_sb->ide_regs[0x15] = 0x03; + via_mvp3_sb->ide_regs[0x18] = 0x70; via_mvp3_sb->ide_regs[0x19] = 0x01; + via_mvp3_sb->ide_regs[0x1c] = 0x74; via_mvp3_sb->ide_regs[0x1d] = 0x03; + via_mvp3_sb->ide_regs[0x20] = 0x01; via_mvp3_sb->ide_regs[0x21] = 0xcc; + + via_mvp3_sb->ide_regs[0x3c] = 0x0e; + + via_mvp3_sb->ide_regs[0x40] = 0x08; + via_mvp3_sb->ide_regs[0x41] = 0x02; + via_mvp3_sb->ide_regs[0x42] = 0x09; + via_mvp3_sb->ide_regs[0x43] = 0x3a; + via_mvp3_sb->ide_regs[0x44] = 0x68; + via_mvp3_sb->ide_regs[0x46] = 0xc0; + via_mvp3_sb->ide_regs[0x48] = 0xa8; via_mvp3_sb->ide_regs[0x49] = 0xa8; + via_mvp3_sb->ide_regs[0x4a] = 0xa8; via_mvp3_sb->ide_regs[0x4b] = 0xa8; + via_mvp3_sb->ide_regs[0x4c] = 0xff; + via_mvp3_sb->ide_regs[0x4e] = 0xff; + via_mvp3_sb->ide_regs[0x4f] = 0xff; + via_mvp3_sb->ide_regs[0x50] = 0x03; via_mvp3_sb->ide_regs[0x51] = 0x03; + via_mvp3_sb->ide_regs[0x52] = 0x03; via_mvp3_sb->ide_regs[0x53] = 0x03; + + via_mvp3_sb->ide_regs[0x61] = 0x02; + via_mvp3_sb->ide_regs[0x69] = 0x02; + + via_mvp3_sb->usb_regs[0x00] = 0x06; via_mvp3_sb->usb_regs[0x01] = 0x11; /*VIA*/ + via_mvp3_sb->usb_regs[0x02] = 0x38; via_mvp3_sb->usb_regs[0x03] = 0x30; + via_mvp3_sb->usb_regs[0x04] = 0x00; via_mvp3_sb->usb_regs[0x05] = 0x00; + via_mvp3_sb->usb_regs[0x06] = 0x00; via_mvp3_sb->usb_regs[0x07] = 0x02; + via_mvp3_sb->usb_regs[0x0a] = 0x03; + via_mvp3_sb->usb_regs[0x0b] = 0x0c; + via_mvp3_sb->usb_regs[0x0d] = 0x16; + via_mvp3_sb->usb_regs[0x20] = 0x01; + via_mvp3_sb->usb_regs[0x21] = 0x03; + via_mvp3_sb->usb_regs[0x3d] = 0x04; + + via_mvp3_sb->usb_regs[0x60] = 0x10; + via_mvp3_sb->usb_regs[0xc1] = 0x20; + + via_mvp3_sb->power_regs[0x00] = 0x06; via_mvp3_sb->power_regs[0x01] = 0x11; /*VIA*/ + via_mvp3_sb->power_regs[0x02] = 0x40; via_mvp3_sb->power_regs[0x03] = 0x30; + via_mvp3_sb->power_regs[0x04] = 0x00; via_mvp3_sb->power_regs[0x05] = 0x00; + via_mvp3_sb->power_regs[0x06] = 0x80; via_mvp3_sb->power_regs[0x07] = 0x02; + via_mvp3_sb->power_regs[0x08] = 0x10; /*Production version (3041)*/ + via_mvp3_sb->power_regs[0x48] = 0x01; + + pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); + + pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED); + pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED); + pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED); + + ide_pri_disable(); + ide_sec_disable(); +} + +static void +via_mvp3_sb_bus_master_handlers(via_mvp3_sb_t *dev, uint16_t old_base) +{ + uint16_t base; + + base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8); + + sff_bus_master_handlers(dev->bm[0], old_base, base, (dev->ide_regs[0x04] & 1)); + sff_bus_master_handlers(dev->bm[1], old_base + 8, base + 8, (dev->ide_regs[0x04] & 1)); +} + +static uint8_t +via_mvp3_sb_read(int func, int addr, void *priv) +{ + via_mvp3_sb_t *dev = (via_mvp3_sb_t *) priv; + + switch(func) + { + case 0: + { + return dev->pci_isa_regs[addr]; + } + case 1: + { + return dev->ide_regs[addr]; + } + case 2: + { + return dev->usb_regs[addr]; + } + case 3: + { + return dev->power_regs[addr]; + } + default: + { + return 0xff; + } + } +} + +static void +via_mvp3_sb_write(int func, int addr, uint8_t val, void *priv) +{ + via_mvp3_sb_t *dev = (via_mvp3_sb_t *) priv; + uint16_t old_base; + + if(func > 3) return; + + old_base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8); + + switch(func) + { + case 0: //PCI-ISA bridge + { + /*Read-only addresses*/ + if ((addr < 4) || (addr == 5) || (addr == 6) + || (addr >= 8 && addr < 0x40) + || (addr == 0x49) + || (addr == 0x4b) + || (addr >= 0x51 && addr < 0x54) + || (addr >= 0x5d && addr < 0x60) + || (addr >= 0x68 && addr < 0x6a) + || (addr >= 0x71)) + return; + + switch(addr) + { + case 0x04: + dev->pci_isa_regs[0x04] = (val & 8) | 7; + break; + case 0x06: + dev->pci_isa_regs[0x06] &= ~(val & 0xb0); + break; + + case 0x47: + if((val & 0x81) == 0x81) resetx86(); + if(val & 0x20) pci_elcr_set_enabled(1); + else pci_elcr_set_enabled(0); + dev->pci_isa_regs[0x47] = val & 0xfe; + break; + + case 0x54: + if(val & 8) pci_set_irq_level(PCI_INTA, 0); + else pci_set_irq_level(PCI_INTA, 1); + if(val & 4) pci_set_irq_level(PCI_INTB, 0); + else pci_set_irq_level(PCI_INTB, 1); + if(val & 2) pci_set_irq_level(PCI_INTC, 0); + else pci_set_irq_level(PCI_INTC, 1); + if(val & 1) pci_set_irq_level(PCI_INTD, 0); + else pci_set_irq_level(PCI_INTD, 1); + break; + + case 0x55: + if(!(val & 0xf0)) pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); + else pci_set_irq_routing(PCI_INTD, val >> 4); + + if(!(val & 0x0f)) pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED); + else pci_set_mirq_routing(PCI_MIRQ0, val & 0xf); + dev->pci_isa_regs[0x55] = val; + break; + + case 0x56: + if(!(val & 0xf0)) pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); + else pci_set_irq_routing(PCI_INTA, val >> 4); + + if(!(val & 0x0f)) pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); + else pci_set_irq_routing(PCI_INTB, val & 0xf); + dev->pci_isa_regs[0x56] = val; + break; + + case 0x57: + if(!(val & 0xf0)) pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED); + else pci_set_irq_routing(PCI_INTC, val >> 4); + + if(!(val & 0x0f)) pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED); + else pci_set_mirq_routing(PCI_MIRQ1, val & 0xf); + dev->pci_isa_regs[0x57] = val; + break; + + case 0x58: + if(!(val & 0x0f)) pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED); + else pci_set_mirq_routing(PCI_MIRQ2, val & 0xf); + dev->pci_isa_regs[0x58] = val; + } + break; + } + case 1: /*IDE regs*/ + { + /*Read-only addresses*/ + if ((addr < 4) || (addr == 5) || (addr == 8) + || (addr >= 0xa && addr < 0x0d) + || (addr >= 0x0e && addr < 0x20) + || (addr >= 0x22 && addr < 0x3c) + || (addr >= 0x3d && addr < 0x40) + || (addr >= 0x54 && addr < 0x60) + || (addr >= 0x52 && addr < 0x68) + || (addr >= 0x62)) + return; + + switch(addr) + { + case 0x04: + { + uint16_t base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8); + ide_pri_disable(); + ide_sec_disable(); + if(val & PCI_COMMAND_IO) + { + if(dev->ide_regs[0x40] & 0x02) ide_pri_enable(); + if(dev->ide_regs[0x40] & 0x01) ide_sec_enable(); + } + via_mvp3_sb_bus_master_handlers(dev, base); + dev->ide_regs[0x04] = val & 0x85; + break; + } + case 0x06: + dev->ide_regs[0x06] &= ~(val & 0xb0); + break; + + case 0x09: + dev->ide_regs[0x09] = (dev->pci_isa_regs[0x09] & ~0x70) | 0x8a; + break; + + case 0x20: + { + dev->ide_regs[0x20] = (val & 0xf0) | 1; + via_mvp3_sb_bus_master_handlers(dev, old_base); + break; + } + + case 0x21: + { + dev->ide_regs[0x21] = val; + via_mvp3_sb_bus_master_handlers(dev, old_base); + break; + } + + case 0x40: + { + dev->ide_regs[0x40] = val; + ide_pri_disable(); + ide_sec_disable(); + if(val & PCI_COMMAND_IO) + { + if(dev->ide_regs[0x40] & 0x02) ide_pri_enable(); + if(dev->ide_regs[0x40] & 0x01) ide_sec_enable(); + } + break; + } + + default: + dev->ide_regs[addr] = val; + break; + } + break; + } + case 2: + { + /*Read-only addresses*/ + if ((addr < 4) || (addr == 5) || (addr == 6) + || (addr >= 8 && addr < 0xd) + || (addr >= 0xe && addr < 0x20) + || (addr >= 0x22 && addr < 0x3c) + || (addr >= 0x3e && addr < 0x40) + || (addr >= 0x42 && addr < 0x44) + || (addr >= 0x46 && addr < 0xc0) + || (addr >= 0xc2)) + return; + + switch(addr) + { + case 0x04: + dev->usb_regs[0x04] = val & 0x97; + break; + case 0x07: + dev->usb_regs[0x07] = val & 0x7f; + break; + + case 0x20: + dev->usb_regs[0x20] = (val & ~0x1f) | 1; + break; + + default: + dev->usb_regs[addr] = val; + break; + } + break; + } + case 3: + { + /*Read-only addresses*/ + if ((addr < 0xd) || (addr >= 0xe && addr < 0x40) + || (addr == 0x43) + || (addr == 0x48) + || (addr >= 0x4a && addr < 0x50) + || (addr >= 0x54)) + return; + + dev->power_regs[addr] = val; + break; + } + } +} + +static void +*via_mvp3_sb_init(const device_t *info) +{ + via_mvp3_sb_t *via_mvp3_sb = (via_mvp3_sb_t *) malloc(sizeof(via_mvp3_sb_t)); + memset(via_mvp3_sb, 0, sizeof(via_mvp3_sb_t)); + + pci_add_card(7, via_mvp3_sb_read, via_mvp3_sb_write, via_mvp3_sb); + + via_mvp3_sb->bm[0] = device_add_inst(&sff8038i_device, 1); + via_mvp3_sb->bm[1] = device_add_inst(&sff8038i_device, 2); + + via_mvp3_sb_reset_hard(via_mvp3_sb); + + device_add(&port_92_pci_device); + + dma_alias_set(); + + pci_enable_mirq(0); + pci_enable_mirq(1); + pci_enable_mirq(2); + + return via_mvp3_sb; +} + +static void +via_mvp3_sb_close(void *p) +{ + via_mvp3_sb_t *via_mvp3_sb = (via_mvp3_sb_t *)p; + + free(via_mvp3_sb); +} + +const device_t via_mvp3_sb_device = +{ + "VIA VT82C586B", + DEVICE_PCI, + 0, + via_mvp3_sb_init, + via_mvp3_sb_close, + NULL, + NULL, + NULL, + NULL, + NULL +}; \ No newline at end of file diff --git a/src/via_mvp3_sb.h b/src/via_mvp3_sb.h new file mode 100644 index 000000000..2e9ab7967 --- /dev/null +++ b/src/via_mvp3_sb.h @@ -0,0 +1,22 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * Emulation of the VIA Apollo MVP3 southbridge + * + * Version: @(#)via_mvp3_sb.c 1.0.22 2018/10/31 + * + * Authors: Sarah Walker, + * Miran Grca, + * Melissa Goad, + * + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. + * Copyright 2020 Melissa Goad. + */ + +#if defined(DEV_BRANCH) && defined(USE_SS7) +extern const device_t via_mvp3_sb_device; +#endif \ No newline at end of file diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index facc55327..3ee85ba09 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -74,6 +74,9 @@ ifeq ($(DEV_BUILD), y) ifndef PS2M70T4 PS2M70T4 := y endif + ifndef SS7 + SS7 := y + endif ifndef TI TI := y endif @@ -138,6 +141,9 @@ else ifndef PS2M70T4 PS2M70T4 := n endif + ifndef SS7 + SS7 := n + endif ifndef TI TI := n endif @@ -500,6 +506,11 @@ ifeq ($(PS2M70T4), y) OPTS += -DUSE_PS2M70T4 endif +ifeq ($(SS7),y) +OPTS += -DUSE_SS7 +DEVBROBJ += via_mvp3.o via_mvp3_sb.o sst_flash.o +endif + ifeq ($(TI), y) OPTS += -DUSE_TI endif From 199db4acbe54cf6610d354f12b14133350e66b02 Mon Sep 17 00:00:00 2001 From: Melissa Goad Date: Sun, 12 Jan 2020 20:36:38 -0600 Subject: [PATCH 2/4] Fixes from OBattler --- src/chipset/via_mvp3.c | 231 +++++++++++++++++++++++------------------ 1 file changed, 130 insertions(+), 101 deletions(-) diff --git a/src/chipset/via_mvp3.c b/src/chipset/via_mvp3.c index dfeba12c2..d9ffc01a6 100644 --- a/src/chipset/via_mvp3.c +++ b/src/chipset/via_mvp3.c @@ -30,60 +30,35 @@ #include "../keyboard.h" #include "chipset.h" + typedef struct via_mvp3_t { uint8_t pci_conf[2][256]; } via_mvp3_t; + static void -via_mvp3_recalcmapping(via_mvp3_t *dev) +mvp3_map(uint32_t addr, uint32_t size, int state) { - int c, d; - uint32_t base; - - for (c = 0; c < 2; c++) { - for (d = 0; d < 4; d++) { - base = 0xc0000 + (d << 14); - switch (dev->pci_conf[0][0x61 + c] & (3 << (d << 1))) { - case 0x00: - mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 0x01: - mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 0x02: - mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 0x03: - mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - } - } - } - - for(d = 0; d < 2; d++) - { - base = 0xe0000 + (d << 16); - switch (dev->pci_conf[0][0x63] & (3 << (d << 1))) { - case 0x00: - mem_set_mem_state(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 0x01: - mem_set_mem_state(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 0x02: - mem_set_mem_state(base, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 0x03: - mem_set_mem_state(base, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - } + switch (state & 3) { + case 0: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 1: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 2: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 3: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; } flushmmucache_nopc(); - shadowbios = 1; } + static void via_mvp3_setup(via_mvp3_t *dev) { @@ -158,108 +133,160 @@ via_mvp3_setup(via_mvp3_t *dev) dev->pci_conf[1][0x25] = 0xff; } + static void via_mvp3_host_bridge_write(int func, int addr, uint8_t val, void *priv) { via_mvp3_t *dev = (via_mvp3_t *) priv; if (func) - return; + return; /*Read-only addresses*/ - if ((addr < 4) || (addr >= 5 && addr < 7) - || (addr >= 8 && addr < 0xd) - || (addr >= 0xe && addr < 0x12) - || (addr >= 0x14 && addr < 0x50) - || (addr >= 0x79 && addr < 0x7e) - || (addr >= 0x85 && addr < 0x88) - || (addr >= 0x8c && addr < 0xa8) - || (addr >= 0xad && addr < 0xfd)) - return; + if ((addr < 4) || ((addr >= 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) || + ((addr >= 0xe) && (addr < 0x12)) || ((addr >= 0x14) && (addr < 0x50)) || + ((addr >= 0x79) && (addr < 0x7e)) || ((addr >= 0x85) && (addr < 0x88)) || + ((addr >= 0x8c) && (addr < 0xa8)) || ((addr >= 0xad) && (addr < 0xfd))) + return; - switch(addr) - { - case 0x04: - dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40); - break; - case 0x07: - dev->pci_conf[0][0x07] &= ~(val & 0xb0); - case 0x61: case 0x62: case 0x63: - dev->pci_conf[0][addr] = val; - via_mvp3_recalcmapping(dev); - break; - default: - dev->pci_conf[0][addr] = val; - break; + switch(addr) { + case 0x04: + dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40); + break; + case 0x07: + dev->pci_conf[0][0x07] &= ~(val & 0xb0); + break; + + case 0x12: /* Graphics Aperture Base */ + dev->pci_conf[0][0x12] = (val & 0xf0); + break; + case 0x13: /* Graphics Aperture Base */ + dev->pci_conf[0][0x13] = val; + break; + + case 0x61: /* Shadow RAM Control 1 */ + if ((dev->pci_conf[0][0x61] ^ val) & 0x03) + mvp3_map(0xc0000, 0x04000, val & 0x03); + if ((dev->pci_conf[0][0x61] ^ val) & 0x0c) + mvp3_map(0xc4000, 0x04000, (val & 0x0c) >> 2); + if ((dev->pci_conf[0][0x61] ^ val) & 0x30) + mvp3_map(0xc8000, 0x04000, (val & 0x30) >> 4); + if ((dev->pci_conf[0][0x61] ^ val) & 0xc0) + mvp3_map(0xcc000, 0x04000, (val & 0xc0) >> 6); + dev->pci_conf[0][0x61] = val; + return; + case 0x62: /* Shadow RAM Control 2 */ + if ((dev->pci_conf[0][0x62] ^ val) & 0x03) + mvp3_map(0xd0000, 0x04000, val & 0x03); + if ((dev->pci_conf[0][0x62] ^ val) & 0x0c) + mvp3_map(0xd4000, 0x04000, (val & 0x0c) >> 2); + if ((dev->pci_conf[0][0x62] ^ val) & 0x30) + mvp3_map(0xd8000, 0x04000, (val & 0x30) >> 4); + if ((dev->pci_conf[0][0x62] ^ val) & 0xc0) + mvp3_map(0xdc000, 0x04000, (val & 0xc0) >> 6); + dev->pci_conf[0][0x62] = val; + return; + case 0x63: /* Shadow RAM Control 3 */ + if ((dev->pci_conf[0][0x63] ^ val) & 0x30) { + mvp3_map(0xf0000, 0x10000, (val & 0x30) >> 4); + shadowbios = (((val & 0x30) >> 4) & 0x02); + } + if ((dev->pci_conf[0][0x63] ^ val) & 0xc0) + mvp3_map(0xe0000, 0x10000, (val & 0xc0) >> 6); + dev->pci_conf[0][0x63] = val; + return; + + default: + dev->pci_conf[0][addr] = val; + break; } } + static void via_mvp3_pci_bridge_write(int func, int addr, uint8_t val, void *priv) { via_mvp3_t *dev = (via_mvp3_t *) priv; - if(func != 1) return; + if (func != 1) + return; /*Read-only addresses*/ - if ((addr < 4) || (addr >= 5 && addr < 7) - || (addr >= 8 && addr < 0x18) - || (addr == 0x1b) - || (addr >= 0x1e && addr < 0x20) - || (addr >= 0x28 && addr < 0x3e) - || (addr >= 0x43)) - return; - - switch(addr) - { - case 0x04: - dev->pci_conf[1][0x04] = (dev->pci_conf[1][0x04] & ~0x47) | (val & 0x47); - break; - case 0x07: - dev->pci_conf[1][0x07] &= ~(val & 0x30); - default: - dev->pci_conf[1][addr] = val; - break; + if ((addr < 4) || ((addr >= 5) && (addr < 7)) || + ((addr >= 8) && (addr < 0x18)) || (addr == 0x1b) || + ((addr >= 0x1e) && (addr < 0x20)) || ((addr >= 0x28) && (addr < 0x3e)) || + (addr >= 0x43)) + return; + + switch(addr) { + case 0x04: + dev->pci_conf[1][0x04] = (dev->pci_conf[1][0x04] & ~0x47) | (val & 0x47); + break; + case 0x07: + dev->pci_conf[1][0x07] &= ~(val & 0x30); + break; + + case 0x20: /* Memory Base */ + dev->pci_conf[1][0x20] = val & 0xf0; + break; + case 0x22: /* Memory Limit */ + dev->pci_conf[1][0x22] = val & 0xf0; + break; + case 0x24: /* Prefetchable Memory Base */ + dev->pci_conf[1][0x24] = val & 0xf0; + break; + case 0x26: /* Prefetchable Memory Limit */ + dev->pci_conf[1][0x26] = val & 0xf0; + break; + + default: + dev->pci_conf[1][addr] = val; + break; } } + static uint8_t via_mvp3_read(int func, int addr, void *priv) { via_mvp3_t *dev = (via_mvp3_t *) priv; + uint8_t ret = 0xff; - switch(func) - { - case 0: return dev->pci_conf[0][addr]; - case 1: return dev->pci_conf[1][addr]; - default: return 0xff; + switch(func) { + case 0: + ret = dev->pci_conf[0][addr]; + break; + case 1: + ret = dev->pci_conf[1][addr]; + break; } + + return ret; } static void via_mvp3_write(int func, int addr, uint8_t val, void *priv) { - switch(func) - { - case 0: - via_mvp3_host_bridge_write(func, addr, val, priv); - break; - case 1: - via_mvp3_pci_bridge_write(func, addr, val, priv); - break; + switch(func) { + case 0: + via_mvp3_host_bridge_write(func, addr, val, priv); + break; + case 1: + via_mvp3_pci_bridge_write(func, addr, val, priv); + break; } } + static void via_mvp3_reset(void *priv) { - via_mvp3_t *dev = (via_mvp3_t *) priv; - - via_mvp3_setup(dev); + via_mvp3_write(0, 0x63, via_mvp3_read(0, 0x63, priv) & 0xcf, priv); } + static void * via_mvp3_init(const device_t *info) { @@ -272,6 +299,7 @@ via_mvp3_init(const device_t *info) return dev; } + static void via_mvp3_close(void *priv) { @@ -280,6 +308,7 @@ via_mvp3_close(void *priv) free(dev); } + const device_t via_mvp3_device = { "VIA MVP3", From 426bf8c46e93794e03966ace25476f9a4a5663c2 Mon Sep 17 00:00:00 2001 From: Melissa Goad Date: Mon, 13 Jan 2020 11:56:24 -0600 Subject: [PATCH 3/4] Fix the name of the VT82C586B southbridge --- src/machine/m_at_socket7_s7.c | 4 +- src/{via_mvp3_sb.c => vt82c586b.c} | 186 ++++++++++++++--------------- src/{via_mvp3_sb.h => vt82c586b.h} | 2 +- src/win/Makefile_ndr.mingw | 2 +- 4 files changed, 97 insertions(+), 97 deletions(-) rename src/{via_mvp3_sb.c => vt82c586b.c} (63%) rename src/{via_mvp3_sb.h => vt82c586b.h} (91%) diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c index 9dfd1515a..36960af3e 100644 --- a/src/machine/m_at_socket7_s7.c +++ b/src/machine/m_at_socket7_s7.c @@ -38,7 +38,7 @@ #include "../piix.h" #include "../sio.h" #include "../sst_flash.h" -#include "../via_mvp3_sb.h" +#include "../vt82c586b.h" #include "../video/video.h" #include "../video/vid_cl54xx.h" #include "../video/vid_s3.h" @@ -477,7 +477,7 @@ machine_at_mvp3_init(const machine_t *model) pci_register_slot(0x0a, PCI_CARD_NORMAL, 3, 4, 1, 2); pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0); device_add(&via_mvp3_device); - device_add(&via_mvp3_sb_device); + device_add(&vt82c586b_device); device_add(&keyboard_ps2_pci_device); device_add(&w83877tf_device); device_add(&sst_flash_39sf010_device); diff --git a/src/via_mvp3_sb.c b/src/vt82c586b.c similarity index 63% rename from src/via_mvp3_sb.c rename to src/vt82c586b.c index 1fa42889c..f53e1ed61 100644 --- a/src/via_mvp3_sb.c +++ b/src/vt82c586b.c @@ -4,9 +4,9 @@ * PC systems and compatibles from 1981 through fairly recent * system designs based on the PCI bus. * - * Emulation of the VIA Apollo MVP3 southbridge + * Emulation of the VIA VT82C586B southbridge * - * Version: @(#)via_mvp3_sb.c 1.0.22 2018/10/31 + * Version: @(#)vt82c586b.c 1.0.22 2018/10/31 * * Authors: Sarah Walker, * Miran Grca, @@ -43,7 +43,7 @@ #include "disk/hdc_ide_sff8038i.h" #include "disk/zip.h" #include "machine/machine.h" -#include "via_mvp3_sb.h" +#include "vt82c586b.h" typedef struct { @@ -52,92 +52,92 @@ typedef struct uint8_t usb_regs[256]; uint8_t power_regs[256]; sff8038i_t *bm[2]; -} via_mvp3_sb_t; +} vt82c586b_t; static void -via_mvp3_sb_reset_hard(void *priv) +vt82c586b_reset_hard(void *priv) { - via_mvp3_sb_t *via_mvp3_sb = (via_mvp3_sb_t *) priv; + vt82c586b_t *vt82c586b = (vt82c586b_t *) priv; - uint16_t old_base = (via_mvp3_sb->ide_regs[0x20] & 0xf0) | (via_mvp3_sb->ide_regs[0x21] << 8); + uint16_t old_base = (vt82c586b->ide_regs[0x20] & 0xf0) | (vt82c586b->ide_regs[0x21] << 8); - sff_bus_master_reset(via_mvp3_sb->bm[0], old_base); - sff_bus_master_reset(via_mvp3_sb->bm[1], old_base + 8); + sff_bus_master_reset(vt82c586b->bm[0], old_base); + sff_bus_master_reset(vt82c586b->bm[1], old_base + 8); - memset(via_mvp3_sb->pci_isa_regs, 0, 256); - memset(via_mvp3_sb->ide_regs, 0, 256); - memset(via_mvp3_sb->usb_regs, 0, 256); - memset(via_mvp3_sb->power_regs, 0, 256); + memset(vt82c586b->pci_isa_regs, 0, 256); + memset(vt82c586b->ide_regs, 0, 256); + memset(vt82c586b->usb_regs, 0, 256); + memset(vt82c586b->power_regs, 0, 256); - via_mvp3_sb->pci_isa_regs[0x00] = 0x06; via_mvp3_sb->pci_isa_regs[0x01] = 0x11; /*VIA*/ - via_mvp3_sb->pci_isa_regs[0x02] = 0x86; via_mvp3_sb->pci_isa_regs[0x03] = 0x05; /*VT82C586B*/ - via_mvp3_sb->pci_isa_regs[0x04] = 0x0f; - via_mvp3_sb->pci_isa_regs[0x07] = 0x02; - via_mvp3_sb->pci_isa_regs[0x0a] = 0x01; - via_mvp3_sb->pci_isa_regs[0x0b] = 0x06; - via_mvp3_sb->pci_isa_regs[0x0e] = 0x80; + vt82c586b->pci_isa_regs[0x00] = 0x06; vt82c586b->pci_isa_regs[0x01] = 0x11; /*VIA*/ + vt82c586b->pci_isa_regs[0x02] = 0x86; vt82c586b->pci_isa_regs[0x03] = 0x05; /*VT82C586B*/ + vt82c586b->pci_isa_regs[0x04] = 0x0f; + vt82c586b->pci_isa_regs[0x07] = 0x02; + vt82c586b->pci_isa_regs[0x0a] = 0x01; + vt82c586b->pci_isa_regs[0x0b] = 0x06; + vt82c586b->pci_isa_regs[0x0e] = 0x80; - via_mvp3_sb->pci_isa_regs[0x48] = 0x01; - via_mvp3_sb->pci_isa_regs[0x4a] = 0x04; - via_mvp3_sb->pci_isa_regs[0x4f] = 0x03; + vt82c586b->pci_isa_regs[0x48] = 0x01; + vt82c586b->pci_isa_regs[0x4a] = 0x04; + vt82c586b->pci_isa_regs[0x4f] = 0x03; - via_mvp3_sb->pci_isa_regs[0x50] = 0x24; - via_mvp3_sb->pci_isa_regs[0x59] = 0x04; + vt82c586b->pci_isa_regs[0x50] = 0x24; + vt82c586b->pci_isa_regs[0x59] = 0x04; //IDE registers - via_mvp3_sb->ide_regs[0x00] = 0x06; via_mvp3_sb->ide_regs[0x01] = 0x11; /*VIA*/ - via_mvp3_sb->ide_regs[0x02] = 0x71; via_mvp3_sb->ide_regs[0x03] = 0x05; /*VT82C586B*/ - via_mvp3_sb->ide_regs[0x04] = 0x80; - via_mvp3_sb->ide_regs[0x06] = 0x80; via_mvp3_sb->ide_regs[0x07] = 0x02; - via_mvp3_sb->ide_regs[0x09] = 0x85; - via_mvp3_sb->ide_regs[0x0a] = 0x01; - via_mvp3_sb->ide_regs[0x0b] = 0x01; + vt82c586b->ide_regs[0x00] = 0x06; vt82c586b->ide_regs[0x01] = 0x11; /*VIA*/ + vt82c586b->ide_regs[0x02] = 0x71; vt82c586b->ide_regs[0x03] = 0x05; /*VT82C586B*/ + vt82c586b->ide_regs[0x04] = 0x80; + vt82c586b->ide_regs[0x06] = 0x80; vt82c586b->ide_regs[0x07] = 0x02; + vt82c586b->ide_regs[0x09] = 0x85; + vt82c586b->ide_regs[0x0a] = 0x01; + vt82c586b->ide_regs[0x0b] = 0x01; - via_mvp3_sb->ide_regs[0x10] = 0xf0; via_mvp3_sb->ide_regs[0x11] = 0x01; - via_mvp3_sb->ide_regs[0x14] = 0xf4; via_mvp3_sb->ide_regs[0x15] = 0x03; - via_mvp3_sb->ide_regs[0x18] = 0x70; via_mvp3_sb->ide_regs[0x19] = 0x01; - via_mvp3_sb->ide_regs[0x1c] = 0x74; via_mvp3_sb->ide_regs[0x1d] = 0x03; - via_mvp3_sb->ide_regs[0x20] = 0x01; via_mvp3_sb->ide_regs[0x21] = 0xcc; + vt82c586b->ide_regs[0x10] = 0xf0; vt82c586b->ide_regs[0x11] = 0x01; + vt82c586b->ide_regs[0x14] = 0xf4; vt82c586b->ide_regs[0x15] = 0x03; + vt82c586b->ide_regs[0x18] = 0x70; vt82c586b->ide_regs[0x19] = 0x01; + vt82c586b->ide_regs[0x1c] = 0x74; vt82c586b->ide_regs[0x1d] = 0x03; + vt82c586b->ide_regs[0x20] = 0x01; vt82c586b->ide_regs[0x21] = 0xcc; - via_mvp3_sb->ide_regs[0x3c] = 0x0e; + vt82c586b->ide_regs[0x3c] = 0x0e; - via_mvp3_sb->ide_regs[0x40] = 0x08; - via_mvp3_sb->ide_regs[0x41] = 0x02; - via_mvp3_sb->ide_regs[0x42] = 0x09; - via_mvp3_sb->ide_regs[0x43] = 0x3a; - via_mvp3_sb->ide_regs[0x44] = 0x68; - via_mvp3_sb->ide_regs[0x46] = 0xc0; - via_mvp3_sb->ide_regs[0x48] = 0xa8; via_mvp3_sb->ide_regs[0x49] = 0xa8; - via_mvp3_sb->ide_regs[0x4a] = 0xa8; via_mvp3_sb->ide_regs[0x4b] = 0xa8; - via_mvp3_sb->ide_regs[0x4c] = 0xff; - via_mvp3_sb->ide_regs[0x4e] = 0xff; - via_mvp3_sb->ide_regs[0x4f] = 0xff; - via_mvp3_sb->ide_regs[0x50] = 0x03; via_mvp3_sb->ide_regs[0x51] = 0x03; - via_mvp3_sb->ide_regs[0x52] = 0x03; via_mvp3_sb->ide_regs[0x53] = 0x03; + vt82c586b->ide_regs[0x40] = 0x08; + vt82c586b->ide_regs[0x41] = 0x02; + vt82c586b->ide_regs[0x42] = 0x09; + vt82c586b->ide_regs[0x43] = 0x3a; + vt82c586b->ide_regs[0x44] = 0x68; + vt82c586b->ide_regs[0x46] = 0xc0; + vt82c586b->ide_regs[0x48] = 0xa8; vt82c586b->ide_regs[0x49] = 0xa8; + vt82c586b->ide_regs[0x4a] = 0xa8; vt82c586b->ide_regs[0x4b] = 0xa8; + vt82c586b->ide_regs[0x4c] = 0xff; + vt82c586b->ide_regs[0x4e] = 0xff; + vt82c586b->ide_regs[0x4f] = 0xff; + vt82c586b->ide_regs[0x50] = 0x03; vt82c586b->ide_regs[0x51] = 0x03; + vt82c586b->ide_regs[0x52] = 0x03; vt82c586b->ide_regs[0x53] = 0x03; - via_mvp3_sb->ide_regs[0x61] = 0x02; - via_mvp3_sb->ide_regs[0x69] = 0x02; + vt82c586b->ide_regs[0x61] = 0x02; + vt82c586b->ide_regs[0x69] = 0x02; - via_mvp3_sb->usb_regs[0x00] = 0x06; via_mvp3_sb->usb_regs[0x01] = 0x11; /*VIA*/ - via_mvp3_sb->usb_regs[0x02] = 0x38; via_mvp3_sb->usb_regs[0x03] = 0x30; - via_mvp3_sb->usb_regs[0x04] = 0x00; via_mvp3_sb->usb_regs[0x05] = 0x00; - via_mvp3_sb->usb_regs[0x06] = 0x00; via_mvp3_sb->usb_regs[0x07] = 0x02; - via_mvp3_sb->usb_regs[0x0a] = 0x03; - via_mvp3_sb->usb_regs[0x0b] = 0x0c; - via_mvp3_sb->usb_regs[0x0d] = 0x16; - via_mvp3_sb->usb_regs[0x20] = 0x01; - via_mvp3_sb->usb_regs[0x21] = 0x03; - via_mvp3_sb->usb_regs[0x3d] = 0x04; + vt82c586b->usb_regs[0x00] = 0x06; vt82c586b->usb_regs[0x01] = 0x11; /*VIA*/ + vt82c586b->usb_regs[0x02] = 0x38; vt82c586b->usb_regs[0x03] = 0x30; + vt82c586b->usb_regs[0x04] = 0x00; vt82c586b->usb_regs[0x05] = 0x00; + vt82c586b->usb_regs[0x06] = 0x00; vt82c586b->usb_regs[0x07] = 0x02; + vt82c586b->usb_regs[0x0a] = 0x03; + vt82c586b->usb_regs[0x0b] = 0x0c; + vt82c586b->usb_regs[0x0d] = 0x16; + vt82c586b->usb_regs[0x20] = 0x01; + vt82c586b->usb_regs[0x21] = 0x03; + vt82c586b->usb_regs[0x3d] = 0x04; - via_mvp3_sb->usb_regs[0x60] = 0x10; - via_mvp3_sb->usb_regs[0xc1] = 0x20; + vt82c586b->usb_regs[0x60] = 0x10; + vt82c586b->usb_regs[0xc1] = 0x20; - via_mvp3_sb->power_regs[0x00] = 0x06; via_mvp3_sb->power_regs[0x01] = 0x11; /*VIA*/ - via_mvp3_sb->power_regs[0x02] = 0x40; via_mvp3_sb->power_regs[0x03] = 0x30; - via_mvp3_sb->power_regs[0x04] = 0x00; via_mvp3_sb->power_regs[0x05] = 0x00; - via_mvp3_sb->power_regs[0x06] = 0x80; via_mvp3_sb->power_regs[0x07] = 0x02; - via_mvp3_sb->power_regs[0x08] = 0x10; /*Production version (3041)*/ - via_mvp3_sb->power_regs[0x48] = 0x01; + vt82c586b->power_regs[0x00] = 0x06; vt82c586b->power_regs[0x01] = 0x11; /*VIA*/ + vt82c586b->power_regs[0x02] = 0x40; vt82c586b->power_regs[0x03] = 0x30; + vt82c586b->power_regs[0x04] = 0x00; vt82c586b->power_regs[0x05] = 0x00; + vt82c586b->power_regs[0x06] = 0x80; vt82c586b->power_regs[0x07] = 0x02; + vt82c586b->power_regs[0x08] = 0x10; /*Production version (3041)*/ + vt82c586b->power_regs[0x48] = 0x01; pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); @@ -153,7 +153,7 @@ via_mvp3_sb_reset_hard(void *priv) } static void -via_mvp3_sb_bus_master_handlers(via_mvp3_sb_t *dev, uint16_t old_base) +vt82c586b_bus_master_handlers(vt82c586b_t *dev, uint16_t old_base) { uint16_t base; @@ -164,9 +164,9 @@ via_mvp3_sb_bus_master_handlers(via_mvp3_sb_t *dev, uint16_t old_base) } static uint8_t -via_mvp3_sb_read(int func, int addr, void *priv) +vt82c586b_read(int func, int addr, void *priv) { - via_mvp3_sb_t *dev = (via_mvp3_sb_t *) priv; + vt82c586b_t *dev = (vt82c586b_t *) priv; switch(func) { @@ -194,9 +194,9 @@ via_mvp3_sb_read(int func, int addr, void *priv) } static void -via_mvp3_sb_write(int func, int addr, uint8_t val, void *priv) +vt82c586b_write(int func, int addr, uint8_t val, void *priv) { - via_mvp3_sb_t *dev = (via_mvp3_sb_t *) priv; + vt82c586b_t *dev = (vt82c586b_t *) priv; uint16_t old_base; if(func > 3) return; @@ -304,7 +304,7 @@ via_mvp3_sb_write(int func, int addr, uint8_t val, void *priv) if(dev->ide_regs[0x40] & 0x02) ide_pri_enable(); if(dev->ide_regs[0x40] & 0x01) ide_sec_enable(); } - via_mvp3_sb_bus_master_handlers(dev, base); + vt82c586b_bus_master_handlers(dev, base); dev->ide_regs[0x04] = val & 0x85; break; } @@ -319,14 +319,14 @@ via_mvp3_sb_write(int func, int addr, uint8_t val, void *priv) case 0x20: { dev->ide_regs[0x20] = (val & 0xf0) | 1; - via_mvp3_sb_bus_master_handlers(dev, old_base); + vt82c586b_bus_master_handlers(dev, old_base); break; } case 0x21: { dev->ide_regs[0x21] = val; - via_mvp3_sb_bus_master_handlers(dev, old_base); + vt82c586b_bus_master_handlers(dev, old_base); break; } @@ -398,17 +398,17 @@ via_mvp3_sb_write(int func, int addr, uint8_t val, void *priv) } static void -*via_mvp3_sb_init(const device_t *info) +*vt82c586b_init(const device_t *info) { - via_mvp3_sb_t *via_mvp3_sb = (via_mvp3_sb_t *) malloc(sizeof(via_mvp3_sb_t)); - memset(via_mvp3_sb, 0, sizeof(via_mvp3_sb_t)); + vt82c586b_t *vt82c586b = (vt82c586b_t *) malloc(sizeof(vt82c586b_t)); + memset(vt82c586b, 0, sizeof(vt82c586b_t)); - pci_add_card(7, via_mvp3_sb_read, via_mvp3_sb_write, via_mvp3_sb); + pci_add_card(7, vt82c586b_read, vt82c586b_write, vt82c586b); - via_mvp3_sb->bm[0] = device_add_inst(&sff8038i_device, 1); - via_mvp3_sb->bm[1] = device_add_inst(&sff8038i_device, 2); + vt82c586b->bm[0] = device_add_inst(&sff8038i_device, 1); + vt82c586b->bm[1] = device_add_inst(&sff8038i_device, 2); - via_mvp3_sb_reset_hard(via_mvp3_sb); + vt82c586b_reset_hard(vt82c586b); device_add(&port_92_pci_device); @@ -418,24 +418,24 @@ static void pci_enable_mirq(1); pci_enable_mirq(2); - return via_mvp3_sb; + return vt82c586b; } static void -via_mvp3_sb_close(void *p) +vt82c586b_close(void *p) { - via_mvp3_sb_t *via_mvp3_sb = (via_mvp3_sb_t *)p; + vt82c586b_t *vt82c586b = (vt82c586b_t *)p; - free(via_mvp3_sb); + free(vt82c586b); } -const device_t via_mvp3_sb_device = +const device_t vt82c586b_device = { "VIA VT82C586B", DEVICE_PCI, 0, - via_mvp3_sb_init, - via_mvp3_sb_close, + vt82c586b_init, + vt82c586b_close, NULL, NULL, NULL, diff --git a/src/via_mvp3_sb.h b/src/vt82c586b.h similarity index 91% rename from src/via_mvp3_sb.h rename to src/vt82c586b.h index 2e9ab7967..cfec19e9f 100644 --- a/src/via_mvp3_sb.h +++ b/src/vt82c586b.h @@ -18,5 +18,5 @@ */ #if defined(DEV_BRANCH) && defined(USE_SS7) -extern const device_t via_mvp3_sb_device; +extern const device_t vt82c586b_device; #endif \ No newline at end of file diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index 3ee85ba09..10d6aa481 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -508,7 +508,7 @@ endif ifeq ($(SS7),y) OPTS += -DUSE_SS7 -DEVBROBJ += via_mvp3.o via_mvp3_sb.o sst_flash.o +DEVBROBJ += via_mvp3.o vt82c586b.o sst_flash.o endif ifeq ($(TI), y) From da82e6a5eb416496f962014ad5380cf1a8234d3a Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 14 Jan 2020 02:14:39 +0100 Subject: [PATCH 4/4] Finished the VIA machine. --- src/chipset/chipset.h | 6 +- src/disk/hdc_ide.c | 56 +-- src/disk/hdc_ide_sff8038i.c | 38 +- src/disk/hdc_ide_sff8038i.h | 15 +- src/dma.c | 15 +- src/dma.h | 9 +- src/machine/m_at.c | 14 +- src/machine/m_at_socket7_s7.c | 11 +- src/machine/machine.h | 12 +- src/machine/machine_table.c | 10 +- src/machine/machine_table_new.c | 19 +- src/nvr.h | 9 +- src/nvr_at.c | 84 +++- src/sst_flash.c | 2 +- src/sst_flash.h | 4 +- src/via_vt82c586b.c | 639 +++++++++++++++++++++++++++ src/{vt82c586b.h => via_vt82c586b.h} | 42 +- src/vt82c586b.c | 444 ------------------- src/win/Makefile.mingw | 6 +- src/win/Makefile_ndr.mingw | 17 +- 20 files changed, 863 insertions(+), 589 deletions(-) create mode 100644 src/via_vt82c586b.c rename src/{vt82c586b.h => via_vt82c586b.h} (65%) delete mode 100644 src/vt82c586b.c diff --git a/src/chipset/chipset.h b/src/chipset/chipset.h index 50f3536f7..f61cdcd3e 100644 --- a/src/chipset/chipset.h +++ b/src/chipset/chipset.h @@ -8,11 +8,11 @@ * * Handling of the emulated chipsets. * - * Version: @(#)machine.h 1.0.0 2019/05/13 + * Version: @(#)machine.h 1.0.1 2020/01/14 * * Authors: Miran Grca, * - * Copyright 2019 Miran Grca. + * Copyright 2019,2020 Miran Grca. */ #ifndef EMU_CHIPSET_H # define EMU_CHIPSET_H @@ -61,10 +61,8 @@ extern const device_t sis_85c496_device; extern const device_t sis_85c50x_device; #endif -#if defined(DEV_BRANCH) && defined(USE_SS7) /* VIA */ extern const device_t via_mvp3_device; -#endif /* WD */ extern const device_t wd76c10_device; diff --git a/src/disk/hdc_ide.c b/src/disk/hdc_ide.c index a9d1e8e59..6dba893c2 100644 --- a/src/disk/hdc_ide.c +++ b/src/disk/hdc_ide.c @@ -9,13 +9,13 @@ * Implementation of the IDE emulation for hard disks and ATAPI * CD-ROM devices. * - * Version: @(#)hdc_ide.c 1.0.65 2019/11/19 + * Version: @(#)hdc_ide.c 1.0.66 2020/01/14 * * Authors: Sarah Walker, * Miran Grca, * - * Copyright 2008-2019 Sarah Walker. - * Copyright 2016-2019 Miran Grca. + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. */ #define __USE_LARGEFILE64 #define _LARGEFILE_SOURCE @@ -2315,7 +2315,7 @@ ide_set_handlers(uint8_t board) if (ide_boards[board] == NULL) return; - if (ide_boards[board]->base_main & 0x300) { + if (ide_boards[board]->base_main) { if (ide_boards[board]->bit32) { io_sethandler(ide_boards[board]->base_main, 1, ide_readb, ide_readw, ide_readl, @@ -2332,7 +2332,7 @@ ide_set_handlers(uint8_t board) ide_writeb, NULL, NULL, ide_boards[board]); } - if (ide_boards[board]->side_main & 0x300) { + if (ide_boards[board]->side_main) { io_sethandler(ide_boards[board]->side_main, 1, ide_read_alt_status, NULL, NULL, ide_write_devctl, NULL, NULL, @@ -2347,25 +2347,29 @@ ide_remove_handlers(uint8_t board) if (ide_boards[board] == NULL) return; - if (ide_boards[board]->bit32) { - io_removehandler(ide_boards[board]->base_main, 1, - ide_readb, ide_readw, ide_readl, - ide_writeb, ide_writew, ide_writel, - ide_boards[board]); - } else { - io_removehandler(ide_boards[board]->base_main, 1, - ide_readb, ide_readw, NULL, - ide_writeb, ide_writew, NULL, + if (ide_boards[board]->base_main) { + if (ide_boards[board]->bit32) { + io_removehandler(ide_boards[board]->base_main, 1, + ide_readb, ide_readw, ide_readl, + ide_writeb, ide_writew, ide_writel, + ide_boards[board]); + } else { + io_removehandler(ide_boards[board]->base_main, 1, + ide_readb, ide_readw, NULL, + ide_writeb, ide_writew, NULL, + ide_boards[board]); + } + io_removehandler(ide_boards[board]->base_main + 1, 7, + ide_readb, NULL, NULL, + ide_writeb, NULL, NULL, + ide_boards[board]); + } + if (ide_boards[board]->side_main) { + io_removehandler(ide_boards[board]->side_main, 1, + ide_read_alt_status, NULL, NULL, + ide_write_devctl, NULL, NULL, ide_boards[board]); } - io_removehandler(ide_boards[board]->base_main + 1, 7, - ide_readb, NULL, NULL, - ide_writeb, NULL, NULL, - ide_boards[board]); - io_removehandler(ide_boards[board]->side_main, 1, - ide_read_alt_status, NULL, NULL, - ide_write_devctl, NULL, NULL, - ide_boards[board]); } @@ -2556,10 +2560,8 @@ ide_board_init(int board, int irq, int base_main, int side_main, int type) ide_boards[board]->cur_dev = board << 1; if (type & 6) ide_boards[board]->bit32 = 1; - if (base_main != -1) - ide_boards[board]->base_main = base_main; - if (side_main != -1) - ide_boards[board]->side_main = side_main; + ide_boards[board]->base_main = base_main; + ide_boards[board]->side_main = side_main; ide_set_handlers(board); timer_add(&ide_boards[board]->timer, ide_callback, ide_boards[board], 0); @@ -2607,7 +2609,7 @@ ide_qua_close(void *priv) void * ide_xtide_init(void) { - ide_board_init(0, -1, -1, -1, 0); + ide_board_init(0, -1, 0, 0, 0); return ide_boards[0]; } diff --git a/src/disk/hdc_ide_sff8038i.c b/src/disk/hdc_ide_sff8038i.c index bf712bcc8..96d6bb0fc 100644 --- a/src/disk/hdc_ide_sff8038i.c +++ b/src/disk/hdc_ide_sff8038i.c @@ -10,13 +10,13 @@ * word 0 - base address * word 1 - bits 1-15 = byte count, bit 31 = end of transfer * - * Version: @(#)hdc_ide_sff8038i.c 1.0.1 2019/10/30 + * Version: @(#)hdc_ide_sff8038i.c 1.0.1 2020/01/14 * * Authors: Sarah Walker, * Miran Grca, * - * Copyright 2008-2019 Sarah Walker. - * Copyright 2016-2019 Miran Grca. + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. */ #include #include @@ -370,13 +370,17 @@ sff_bus_master_set_irq(int channel, void *priv) channel &= 0x01; if (dev->status & 0x04) { - if (channel && pci_use_mirq(0)) + if ((dev->irq_mode == 2) && (channel & 1) && pci_use_mirq(0)) pci_set_mirq(0, 0); + else if (dev->irq_mode == 1) + pci_set_irq(dev->slot, dev->irq_pin); else picint(1 << (14 + channel)); } else { - if ((channel & 1) && pci_use_mirq(0)) + if ((dev->irq_mode == 2) && (channel & 1) && pci_use_mirq(0)) pci_clear_mirq(0, 0); + else if (dev->irq_mode == 1) + pci_clear_irq(dev->slot, dev->irq_pin); else picintc(1 << (14 + channel)); } @@ -401,6 +405,9 @@ sff_bus_master_reset(sff8038i_t *dev, uint16_t old_base) dev->addr = 0x00000000; dev->ptr0 = 0x00; dev->count = dev->eot = 0x00000000; + dev->slot = 7; + dev->irq_mode = 2; + dev->irq_pin = PCI_INTA; ide_pri_disable(); ide_sec_disable(); @@ -425,6 +432,27 @@ sff_reset(void *p) } +void +sff_set_slot(sff8038i_t *dev, int slot) +{ + dev->slot = slot; +} + + +void +sff_set_irq_mode(sff8038i_t *dev, int irq_mode) +{ + dev->irq_mode = irq_mode; +} + + +void +sff_set_irq_pin(sff8038i_t *dev, int irq_pin) +{ + dev->irq_pin = irq_pin; +} + + static void sff_close(void *p) { diff --git a/src/disk/hdc_ide_sff8038i.h b/src/disk/hdc_ide_sff8038i.h index 0be341eff..16b6ce524 100644 --- a/src/disk/hdc_ide_sff8038i.h +++ b/src/disk/hdc_ide_sff8038i.h @@ -8,12 +8,12 @@ * * Emulation core dispatcher. * - * Version: @(#)hdc_ide_sff8038i.h 1.0.0 2019/05/12 + * Version: @(#)hdc_ide_sff8038i.h 1.0.1 2020/01/14 * * Authors: Sarah Walker, * Miran Grca, - * Copyright 2008-2018 Sarah Walker. - * Copyright 2016-2018 Miran Grca. + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. */ typedef struct @@ -22,7 +22,9 @@ typedef struct ptr0, enabled; uint32_t ptr, ptr_cur, addr; - int count, eot; + int count, eot, + slot, + irq_mode, irq_pin; } sff8038i_t; @@ -36,3 +38,8 @@ extern int sff_bus_master_dma_write(int channel, uint8_t *data, int transfer_len extern void sff_bus_master_set_irq(int channel, void *priv); extern void sff_bus_master_reset(sff8038i_t *dev, uint16_t old_base); + +extern void sff_set_slot(sff8038i_t *dev, int slot); + +extern void sff_set_irq_mode(sff8038i_t *dev, int irq_mode); +extern void sff_set_irq_pin(sff8038i_t *dev, int irq_pin); diff --git a/src/dma.c b/src/dma.c index 7322f471e..f9a02f365 100644 --- a/src/dma.c +++ b/src/dma.c @@ -8,15 +8,15 @@ * * Implementation of the Intel DMA controllers. * - * Version: @(#)dma.c 1.0.7 2019/09/28 + * Version: @(#)dma.c 1.0.8 2020/01/14 * * Authors: Sarah Walker, * Miran Grca, * Fred N. van Kempen, * - * Copyright 2008-2019 Sarah Walker. - * Copyright 2016-2019 Miran Grca. - * Copyright 2017-2019 Fred N. van Kempen. + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. + * Copyright 2017-2020 Fred N. van Kempen. */ #include #include @@ -38,6 +38,7 @@ dma_t dma[8]; +uint8_t dma_e; static uint8_t dmaregs[16]; @@ -615,6 +616,8 @@ dma_reset(void) dma_wp = dma16_wp = 0; dma_m = 0; + dma_e = 0xff; + for (c = 0; c < 16; c++) dmaregs[c] = dma16regs[c] = 0; for (c = 0; c < 8; c++) { @@ -736,6 +739,8 @@ dma_channel_read(int channel) return(DMA_NODATA); } + if (!(dma_e & (1 << channel))) + return(DMA_NODATA); if ((dma_m & (1 << channel)) && !dma_req_is_soft) return(DMA_NODATA); if ((dma_c->mode & 0xC) != 8) @@ -809,6 +814,8 @@ dma_channel_write(int channel, uint16_t val) return(DMA_NODATA); } + if (!(dma_e & (1 << channel))) + return(DMA_NODATA); if ((dma_m & (1 << channel)) && !dma_req_is_soft) return(DMA_NODATA); if ((dma_c->mode & 0xC) != 4) diff --git a/src/dma.h b/src/dma.h index 75f923e66..5340ba2ea 100644 --- a/src/dma.h +++ b/src/dma.h @@ -8,15 +8,15 @@ * * Definitions for the Intel DMA controller. * - * Version: @(#)dma.h 1.0.2 2018/03/12 + * Version: @(#)dma.h 1.0.3 2020/01/14 * * Authors: Fred N. van Kempen, * Miran Grca, * Sarah Walker, * - * Copyright 2017,2018 Fred N. van Kempen. - * Copyright 2016-2018 Miran Grca. - * Copyright 2008-2018 Sarah Walker. + * Copyright 2017-2020 Fred N. van Kempen. + * Copyright 2016-2020 Miran Grca. + * Copyright 2008-2020 Sarah Walker. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -63,6 +63,7 @@ typedef struct { extern dma_t dma[8]; +extern uint8_t dma_e; extern void dma_init(void); diff --git a/src/machine/m_at.c b/src/machine/m_at.c index 773ac6126..2697bbf24 100644 --- a/src/machine/m_at.c +++ b/src/machine/m_at.c @@ -8,15 +8,15 @@ * * Standard PC/AT implementation. * - * Version: @(#)m_at.c 1.0.11 2019/11/15 + * Version: @(#)m_at.c 1.0.12 2020/01/13 * * Authors: Fred N. van Kempen, * Miran Grca, * Sarah Walker, * - * Copyright 2017-2019 Fred N. van Kempen. - * Copyright 2016-2019 Miran Grca. - * Copyright 2008-2019 Sarah Walker. + * Copyright 2017-2020 Fred N. van Kempen. + * Copyright 2016-2020 Miran Grca. + * Copyright 2008-2020 Sarah Walker. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -59,7 +59,7 @@ void -machine_at_common_init_ex(const machine_t *model, int is_ibm) +machine_at_common_init_ex(const machine_t *model, int type) { machine_common_init(model); @@ -67,9 +67,9 @@ machine_at_common_init_ex(const machine_t *model, int is_ibm) pic2_init(); dma16_init(); - if (is_ibm) + if (type == 1) device_add(&ibmat_nvr_device); - else + else if (type == 0) device_add(&at_nvr_device); if (joystick_type != 7) diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c index 36960af3e..e0a221104 100644 --- a/src/machine/m_at_socket7_s7.c +++ b/src/machine/m_at_socket7_s7.c @@ -38,7 +38,7 @@ #include "../piix.h" #include "../sio.h" #include "../sst_flash.h" -#include "../vt82c586b.h" +#include "../via_vt82c586b.h" #include "../video/video.h" #include "../video/vid_cl54xx.h" #include "../video/vid_s3.h" @@ -456,7 +456,6 @@ machine_at_j656vxd_init(const machine_t *model) return ret; } -#if defined(DEV_BRANCH) && defined(USE_SS7) int machine_at_mvp3_init(const machine_t *model) { @@ -468,20 +467,20 @@ machine_at_mvp3_init(const machine_t *model) if (bios_only || !ret) return ret; - machine_at_common_init(model); + machine_at_common_init_ex(model, 2); pci_init(PCI_CONFIG_TYPE_1); pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x01, PCI_CARD_ONBOARD, 1, 2, 3, 4); pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); pci_register_slot(0x0a, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x07, PCI_CARD_SPECIAL, 1, 2, 3, 4); device_add(&via_mvp3_device); - device_add(&vt82c586b_device); + device_add(&via_vt82c586b_device); device_add(&keyboard_ps2_pci_device); device_add(&w83877tf_device); device_add(&sst_flash_39sf010_device); return ret; } -#endif \ No newline at end of file diff --git a/src/machine/machine.h b/src/machine/machine.h index fdbc4bbe1..689ec98c9 100644 --- a/src/machine/machine.h +++ b/src/machine/machine.h @@ -8,15 +8,15 @@ * * Handling of the emulated machines. * - * Version: @(#)machine.h 1.0.34 2019/03/08 + * Version: @(#)machine.h 1.0.35 2020/01/13 * * Authors: Sarah Walker, * Miran Grca, * Fred N. van Kempen, * - * Copyright 2008-2019 Sarah Walker. - * Copyright 2016-2019 Miran Grca. - * Copyright 2017-2019 Fred N. van Kempen. + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. + * Copyright 2017-2020 Fred N. van Kempen. */ #ifndef EMU_MACHINE_H # define EMU_MACHINE_H @@ -151,7 +151,7 @@ extern const device_t *pc3086_get_device(void); #endif /* m_at.c */ -extern void machine_at_common_init_ex(const machine_t *, int is_ibm); +extern void machine_at_common_init_ex(const machine_t *, int type); extern void machine_at_common_init(const machine_t *); extern void machine_at_init(const machine_t *); extern void machine_at_ps2_init(const machine_t *); @@ -276,9 +276,7 @@ extern int machine_at_i430vx_init(const machine_t *); extern int machine_at_p55va_init(const machine_t *); extern int machine_at_j656vxd_init(const machine_t *); -#if defined(DEV_BRANCH) && defined(USE_SS7) extern int machine_at_mvp3_init(const machine_t *); -#endif #ifdef EMU_DEVICE_H extern const device_t *at_pb640_get_device(void); diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 893b37e7a..457d4da3d 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -11,15 +11,15 @@ * NOTES: OpenAT wip for 286-class machine with open BIOS. * PS2_M80-486 wip, pending receipt of TRM's for machine. * - * Version: @(#)machine_table.c 1.0.50 2019/11/19 + * Version: @(#)machine_table.c 1.0.51 2020/01/14 * * Authors: Sarah Walker, * Miran Grca, * Fred N. van Kempen, * - * Copyright 2008-2019 Sarah Walker. - * Copyright 2016-2019 Miran Grca. - * Copyright 2017-2019 Fred N. van Kempen. + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. + * Copyright 2017-2020 Fred N. van Kempen. */ #include #include @@ -208,6 +208,8 @@ const machine_t machines[] = { { "[Socket 7 VX] Jetway J656VXD", "j656vxd", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_j656vxd_init, NULL }, { "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL }, + { "[Super Socket 7] FIC VA503P", "ficva503p", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_mvp3_init, NULL }, + #if defined(DEV_BRANCH) && defined(USE_I686) { "[Socket 8 FX] Tyan Titan-Pro AT", "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_i440fx_init, NULL }, { "[Socket 8 FX] Tyan Titan-Pro ATX", "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL }, diff --git a/src/machine/machine_table_new.c b/src/machine/machine_table_new.c index c9ae1d598..d072a92c6 100644 --- a/src/machine/machine_table_new.c +++ b/src/machine/machine_table_new.c @@ -11,15 +11,15 @@ * NOTES: OpenAT wip for 286-class machine with open BIOS. * PS2_M80-486 wip, pending receipt of TRM's for machine. * - * Version: @(#)machine_table.c 1.0.50 2019/11/19 + * Version: @(#)machine_table.c 1.0.51 2020/01/14 * * Authors: Sarah Walker, * Miran Grca, * Fred N. van Kempen, * - * Copyright 2008-2019 Sarah Walker. - * Copyright 2016-2019 Miran Grca. - * Copyright 2017-2019 Fred N. van Kempen. + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. + * Copyright 2017-2020 Fred N. van Kempen. */ #include #include @@ -33,9 +33,10 @@ #include "machine.h" -#define MACHINE_CPUS_PENTIUM_S5 {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}} -#define MACHINE_CPUS_PENTIUM_S73V {{ "Intel", cpus_Pentium3V}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"Cyrix", cpus_6x863V},{"", NULL}} -#define MACHINE_CPUS_PENTIUM_S7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86}, {"", NULL}} +#define MACHINE_CPUS_PENTIUM_S5 {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}} +#define MACHINE_CPUS_PENTIUM_S73V {{ "Intel", cpus_Pentium3V}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"Cyrix", cpus_6x863V}, {"", NULL}} +#define MACHINE_CPUS_PENTIUM_S7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86}, {"", NULL}} +#define MACHINE_CPUS_PENTIUM_SS7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip_SS7}, {"AMD", cpus_K56_SS7}, {"Cyrix", cpus_6x86SS7}, {"", NULL}} const machine_t machines[] = { { "[8088] AMI XT clone", "amixt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_amixt_init, NULL }, @@ -192,9 +193,7 @@ const machine_t machines[] = { { "[Socket 7 VX] Jetway J656VXD", "j656vxd", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_j656vxd_init, NULL }, { "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL }, -#if defined(DEV_BRANCH) && defined(USE_SS7) - { "[Super Socket 7] FIC VA503P", "ficva503p", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_mvp3_init, NULL }, -#endif + { "[Super Socket 7] FIC VA503P", "ficva503p", MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_mvp3_init, NULL }, #if defined(DEV_BRANCH) && defined(USE_I686) { "[Socket 8 FX] Tyan Titan-Pro AT", "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_i440fx_init, NULL }, diff --git a/src/nvr.h b/src/nvr.h index f315b7a51..7929ce642 100644 --- a/src/nvr.h +++ b/src/nvr.h @@ -8,13 +8,13 @@ * * Definitions for the generic NVRAM/CMOS driver. * - * Version: @(#)nvr.h 1.0.11 2019/03/16 + * Version: @(#)nvr.h 1.0.12 2020/01/13 * * Author: Fred N. van Kempen, , * David Hrdlička, * - * Copyright 2017-2019 Fred N. van Kempen. - * Copyright 2018,2019 David Hrdlička. + * Copyright 2017-2020 Fred N. van Kempen. + * Copyright 2018-2020 David Hrdlička. * * Redistribution and use in source and binary forms, with * or without modification, are permitted provided that the @@ -91,6 +91,7 @@ extern const device_t at_nvr_device; extern const device_t ps_nvr_device; extern const device_t amstrad_nvr_device; extern const device_t ibmat_nvr_device; +extern const device_t via_nvr_device; #endif @@ -109,5 +110,7 @@ extern int nvr_get_days(int month, int year); extern void nvr_time_get(struct tm *); extern void nvr_time_set(struct tm *); +extern void nvr_at_handler(int set, uint16_t base, nvr_t *nvr); + #endif /*EMU_NVR_H*/ diff --git a/src/nvr_at.c b/src/nvr_at.c index 967f14018..d4b1cfde1 100644 --- a/src/nvr_at.c +++ b/src/nvr_at.c @@ -189,16 +189,16 @@ * including the later update (DS12887A) which implemented a * "century" register to be compatible with Y2K. * - * Version: @(#)nvr_at.c 1.0.16 2019/11/19 + * Version: @(#)nvr_at.c 1.0.17 2020/01/13 * * Authors: Fred N. van Kempen, * Miran Grca, * Mahod, * Sarah Walker, * - * Copyright 2017-2019 Fred N. van Kempen. - * Copyright 2016-2019 Miran Grca. - * Copyright 2008-2019 Sarah Walker. + * Copyright 2017-2020 Fred N. van Kempen. + * Copyright 2016-2020 Miran Grca. + * Copyright 2008-2020 Sarah Walker. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -281,6 +281,9 @@ # define REGD_VRT 0x80 #define RTC_CENTURY_AT 0x32 /* century register for AT etc */ #define RTC_CENTURY_PS 0x37 /* century register for PS/1 PS/2 */ +#define RTC_ALDAY 0x7D /* VIA VT82C586B - alarm day */ +#define RTC_ALMONTH 0x7E /* VIA VT82C586B - alarm month */ +#define RTC_CENTURY_VIA 0x7F /* century register for VIA VT82C586B */ #define RTC_REGS 14 /* number of registers */ @@ -290,7 +293,7 @@ typedef struct { uint8_t cent; uint8_t def; - uint8_t addr; + uint8_t addr[8]; int16_t count, state; @@ -402,6 +405,20 @@ check_alarm(nvr_t *nvr, int8_t addr) } +/* Check for VIA stuff. */ +static int8_t +check_alarm_via(nvr_t *nvr, int8_t addr, int8_t addr_2) +{ + local_t *local = (local_t *)nvr->data; + + if (local->cent == RTC_CENTURY_VIA) { + return((nvr->regs[addr_2] == nvr->regs[addr]) || + ((nvr->regs[addr_2] & AL_DONTCARE) == AL_DONTCARE)); + } else + return 0; +} + + /* Update the NVR registers from the internal clock. */ static void timer_update(void *priv) @@ -425,7 +442,9 @@ timer_update(void *priv) /* Check for any alarms we need to handle. */ if (check_alarm(nvr, RTC_SECONDS) && check_alarm(nvr, RTC_MINUTES) && - check_alarm(nvr, RTC_HOURS)) { + check_alarm(nvr, RTC_HOURS) && + check_alarm_via(nvr, RTC_DOM, RTC_ALDAY) && + check_alarm_via(nvr, RTC_MONTH, RTC_ALMONTH)) { nvr->regs[RTC_REGC] |= REGC_AF; if (nvr->regs[RTC_REGB] & REGB_AIE) { nvr->regs[RTC_REGC] |= REGC_IRQF; @@ -535,12 +554,13 @@ nvr_write(uint16_t addr, uint8_t val, void *priv) local_t *local = (local_t *)nvr->data; struct tm tm; uint8_t old; + uint8_t addr_id = (addr & 0x0e) >> 1; sub_cycles(ISA_CYCLES(8)); if (addr & 1) { - old = nvr->regs[local->addr]; - switch(local->addr) { + old = nvr->regs[local->addr[addr_id]]; + switch(local->addr[addr_id]) { case RTC_REGA: nvr->regs[RTC_REGA] = val; timer_load_count(nvr); @@ -560,15 +580,15 @@ nvr_write(uint16_t addr, uint8_t val, void *priv) break; default: /* non-RTC registers are just NVRAM */ - if (nvr->regs[local->addr] != val) { - nvr->regs[local->addr] = val; + if (nvr->regs[local->addr[addr_id]] != val) { + nvr->regs[local->addr[addr_id]] = val; nvr_dosave = 1; } break; } - if ((local->addr < RTC_REGA) || ((local->cent != 0xff) && (local->addr == local->cent))) { - if ((local->addr != 1) && (local->addr != 3) && (local->addr != 5)) { + if ((local->addr[addr_id] < RTC_REGA) || ((local->cent != 0xff) && (local->addr[addr_id] == local->cent))) { + if ((local->addr[addr_id] != 1) && (local->addr[addr_id] != 3) && (local->addr[addr_id] != 5)) { if ((old != val) && !(time_sync & TIME_SYNC_ENABLED)) { /* Update internal clock. */ time_get(nvr, &tm); @@ -578,7 +598,10 @@ nvr_write(uint16_t addr, uint8_t val, void *priv) } } } else { - local->addr = (val & (nvr->size - 1)); + local->addr[addr_id] = (val & (nvr->size - 1)); + /* Some chipsets use a 256 byte NVRAM but ports 70h and 71h always access only 128 bytes. */ + if (addr_id == 0x0) + local->addr[addr_id] &= 0x7f; if (!(machines[machine].flags & MACHINE_MCA) && !(machines[machine].flags & MACHINE_NONMI)) nmi_mask = (~val & 0x80); @@ -593,10 +616,11 @@ nvr_read(uint16_t addr, void *priv) nvr_t *nvr = (nvr_t *)priv; local_t *local = (local_t *)nvr->data; uint8_t ret; + uint8_t addr_id = (addr & 0x0e) >> 1; sub_cycles(ISA_CYCLES(8)); - if (addr & 1) switch(local->addr) { + if (addr & 1) switch(local->addr[addr_id]) { case RTC_REGA: ret = (nvr->regs[RTC_REGA] & 0x7f) | local->stat; break; @@ -613,10 +637,10 @@ nvr_read(uint16_t addr, void *priv) break; default: - ret = nvr->regs[local->addr]; + ret = nvr->regs[local->addr[addr_id]]; break; } else - ret = local->addr; + ret = local->addr[addr_id]; return(ret); } @@ -692,6 +716,14 @@ nvr_at_speed_changed(void *priv) } +void +nvr_at_handler(int set, uint16_t base, nvr_t *nvr) +{ + io_handler(set, base, 2, + nvr_read,NULL,NULL, nvr_write,NULL,NULL, nvr); +} + + static void * nvr_at_init(const device_t *info) { @@ -710,7 +742,7 @@ nvr_at_init(const device_t *info) /* This is machine specific. */ nvr->size = machines[machine].nvrmask + 1; local->def = 0x00; - switch(info->local) { + switch(info->local & 7) { case 0: /* standard AT, no century register */ nvr->irq = 8; local->cent = 0xff; @@ -738,6 +770,10 @@ nvr_at_init(const device_t *info) local->def = 0xff; break; + case 5: /* VIA VT82C586B */ + nvr->irq = 8; + local->cent = RTC_CENTURY_VIA; + break; } /* Set up any local handlers here. */ @@ -758,6 +794,10 @@ nvr_at_init(const device_t *info) /* Set up the I/O handler for this device. */ io_sethandler(0x0070, 2, nvr_read,NULL,NULL, nvr_write,NULL,NULL, nvr); + if (info->local & 8) { + io_sethandler(0x0072, 2, + nvr_read,NULL,NULL, nvr_write,NULL,NULL, nvr); + } return(nvr); } @@ -829,3 +869,13 @@ const device_t ibmat_nvr_device = { NULL, nvr_at_speed_changed, NULL }; + +const device_t via_nvr_device = { + "VIA PC/AT NVRAM", + DEVICE_ISA | DEVICE_AT, + 9, + nvr_at_init, nvr_at_close, NULL, + NULL, nvr_at_speed_changed, + NULL +}; + diff --git a/src/sst_flash.c b/src/sst_flash.c index b5666659f..7dfc26f1b 100644 --- a/src/sst_flash.c +++ b/src/sst_flash.c @@ -214,7 +214,7 @@ sst_readl(uint32_t addr, void *p) static void sst_add_mappings(sst_t *dev) { - int max = 2, i = 0; + int i = 0; uint32_t base, fbase; for (i = 0; i < 2; i++) { diff --git a/src/sst_flash.h b/src/sst_flash.h index f919e73d1..809fc0c44 100644 --- a/src/sst_flash.h +++ b/src/sst_flash.h @@ -8,12 +8,10 @@ * * Implementation of an SST flash chip. * - * Version: @(#)sst_flash.h 1.0.2 2019/06/25 + * Version: @(#)sst_flash.h 1.0.3 2020/01/14 * * Author: Melissa Goad, * Copyright 2020 Melissa Goad. */ -#if defined(DEV_BRANCH) && defined(USE_SS7) extern const device_t sst_flash_39sf010_device; -#endif \ No newline at end of file diff --git a/src/via_vt82c586b.c b/src/via_vt82c586b.c new file mode 100644 index 000000000..501175d23 --- /dev/null +++ b/src/via_vt82c586b.c @@ -0,0 +1,639 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * Emulation of the VIA Apollo MVP3 southbridge + * + * Version: @(#)via_vt82c586b.c 1.0.0 2020/01/14 + * + * Authors: Sarah Walker, + * Miran Grca, + * Melissa Goad, + * + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. + * Copyright 2020 Melissa Goad. + */ + +#include +#include +#include +#include +#include +#include +#define HAVE_STDARG_H +#include "86box.h" +#include "cdrom/cdrom.h" +#include "cpu/cpu.h" +#include "scsi/scsi_device.h" +#include "scsi/scsi_cdrom.h" +#include "dma.h" +#include "io.h" +#include "device.h" +#include "apm.h" +#include "keyboard.h" +#include "mem.h" +#include "timer.h" +#include "nvr.h" +#include "pci.h" +#include "pic.h" +#include "port_92.h" +#include "disk/hdc.h" +#include "disk/hdc_ide.h" +#include "disk/hdc_ide_sff8038i.h" +#include "disk/zip.h" +#include "machine/machine.h" +#include "via_vt82c586b.h" + + +#define ACPI_TIMER_FREQ 3579545 + +#define ACPI_IO_ENABLE (1 << 7) +#define ACPI_TIMER_32BIT (1 << 3) + + +typedef struct +{ + uint8_t pci_isa_regs[256]; + uint8_t ide_regs[256]; + uint8_t usb_regs[256]; + uint8_t power_regs[256]; + sff8038i_t * bm[2]; + nvr_t * nvr; + int nvr_enabled; + + struct + { + uint16_t io_base; + } usb; + + struct + { + uint16_t io_base; + } power; +} via_vt82c586b_t; + + +static void +via_vt82c586b_reset_hard(void *priv) +{ + int i; + + via_vt82c586b_t *via_vt82c586b = (via_vt82c586b_t *) priv; + uint16_t old_base = (via_vt82c586b->ide_regs[0x20] & 0xf0) | (via_vt82c586b->ide_regs[0x21] << 8); + + sff_bus_master_reset(via_vt82c586b->bm[0], old_base); + sff_bus_master_reset(via_vt82c586b->bm[1], old_base + 8); + + memset(via_vt82c586b->pci_isa_regs, 0, 256); + memset(via_vt82c586b->ide_regs, 0, 256); + memset(via_vt82c586b->usb_regs, 0, 256); + memset(via_vt82c586b->power_regs, 0, 256); + + via_vt82c586b->pci_isa_regs[0x00] = 0x06; via_vt82c586b->pci_isa_regs[0x01] = 0x11; /*VIA*/ + via_vt82c586b->pci_isa_regs[0x02] = 0x86; via_vt82c586b->pci_isa_regs[0x03] = 0x05; /*VT82C586B*/ + via_vt82c586b->pci_isa_regs[0x04] = 0x0f; + via_vt82c586b->pci_isa_regs[0x07] = 0x02; + via_vt82c586b->pci_isa_regs[0x0a] = 0x01; + via_vt82c586b->pci_isa_regs[0x0b] = 0x06; + via_vt82c586b->pci_isa_regs[0x0e] = 0x80; + + via_vt82c586b->pci_isa_regs[0x48] = 0x01; + via_vt82c586b->pci_isa_regs[0x4a] = 0x04; + via_vt82c586b->pci_isa_regs[0x4f] = 0x03; + + via_vt82c586b->pci_isa_regs[0x50] = 0x24; + via_vt82c586b->pci_isa_regs[0x59] = 0x04; + + dma_e = 0x00; + for (i = 0; i < 8; i++) { + dma[i].ab &= 0xffff000f; + dma[i].ac &= 0xffff000f; + } + + /* IDE registers */ + via_vt82c586b->ide_regs[0x00] = 0x06; via_vt82c586b->ide_regs[0x01] = 0x11; /*VIA*/ + via_vt82c586b->ide_regs[0x02] = 0x71; via_vt82c586b->ide_regs[0x03] = 0x05; /*VT82C586B*/ + via_vt82c586b->ide_regs[0x04] = 0x80; + via_vt82c586b->ide_regs[0x06] = 0x80; via_vt82c586b->ide_regs[0x07] = 0x02; + via_vt82c586b->ide_regs[0x09] = 0x85; + via_vt82c586b->ide_regs[0x0a] = 0x01; + via_vt82c586b->ide_regs[0x0b] = 0x01; + + via_vt82c586b->ide_regs[0x10] = 0xf1; via_vt82c586b->ide_regs[0x11] = 0x01; + via_vt82c586b->ide_regs[0x14] = 0xf5; via_vt82c586b->ide_regs[0x15] = 0x03; + via_vt82c586b->ide_regs[0x18] = 0x71; via_vt82c586b->ide_regs[0x19] = 0x01; + via_vt82c586b->ide_regs[0x1c] = 0x75; via_vt82c586b->ide_regs[0x1d] = 0x03; + via_vt82c586b->ide_regs[0x20] = 0x01; via_vt82c586b->ide_regs[0x21] = 0xcc; + via_vt82c586b->ide_regs[0x3c] = 0x0e; + + via_vt82c586b->ide_regs[0x40] = 0x08; + via_vt82c586b->ide_regs[0x41] = 0x02; + via_vt82c586b->ide_regs[0x42] = 0x09; + via_vt82c586b->ide_regs[0x43] = 0x3a; + via_vt82c586b->ide_regs[0x44] = 0x68; + via_vt82c586b->ide_regs[0x46] = 0xc0; + via_vt82c586b->ide_regs[0x48] = 0xa8; via_vt82c586b->ide_regs[0x49] = 0xa8; + via_vt82c586b->ide_regs[0x4a] = 0xa8; via_vt82c586b->ide_regs[0x4b] = 0xa8; + via_vt82c586b->ide_regs[0x4c] = 0xff; + via_vt82c586b->ide_regs[0x4e] = 0xff; + via_vt82c586b->ide_regs[0x4f] = 0xff; + via_vt82c586b->ide_regs[0x50] = 0x03; via_vt82c586b->ide_regs[0x51] = 0x03; + via_vt82c586b->ide_regs[0x52] = 0x03; via_vt82c586b->ide_regs[0x53] = 0x03; + + via_vt82c586b->ide_regs[0x61] = 0x02; + via_vt82c586b->ide_regs[0x69] = 0x02; + + via_vt82c586b->usb_regs[0x00] = 0x06; via_vt82c586b->usb_regs[0x01] = 0x11; /*VIA*/ + via_vt82c586b->usb_regs[0x02] = 0x38; via_vt82c586b->usb_regs[0x03] = 0x30; + via_vt82c586b->usb_regs[0x04] = 0x00; via_vt82c586b->usb_regs[0x05] = 0x00; + via_vt82c586b->usb_regs[0x06] = 0x00; via_vt82c586b->usb_regs[0x07] = 0x02; + via_vt82c586b->usb_regs[0x0a] = 0x03; + via_vt82c586b->usb_regs[0x0b] = 0x0c; + via_vt82c586b->usb_regs[0x0d] = 0x16; + via_vt82c586b->usb_regs[0x20] = 0x01; + via_vt82c586b->usb_regs[0x21] = 0x03; + via_vt82c586b->usb_regs[0x3d] = 0x04; + + via_vt82c586b->usb_regs[0x60] = 0x10; + via_vt82c586b->usb_regs[0xc1] = 0x20; + + via_vt82c586b->power_regs[0x00] = 0x06; via_vt82c586b->power_regs[0x01] = 0x11; /*VIA*/ + via_vt82c586b->power_regs[0x02] = 0x40; via_vt82c586b->power_regs[0x03] = 0x30; + via_vt82c586b->power_regs[0x04] = 0x00; via_vt82c586b->power_regs[0x05] = 0x00; + via_vt82c586b->power_regs[0x06] = 0x80; via_vt82c586b->power_regs[0x07] = 0x02; + via_vt82c586b->power_regs[0x08] = 0x10; /*Production version (3041)*/ + via_vt82c586b->power_regs[0x48] = 0x01; + + pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); + + pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED); + pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED); + pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED); + + ide_pri_disable(); + ide_sec_disable(); +} + + +static void +via_vt82c586b_ide_handlers(via_vt82c586b_t *dev) +{ + uint16_t main, side; + + ide_pri_disable(); + ide_sec_disable(); + + if (dev->ide_regs[0x09] & 0x01) { + main = (dev->ide_regs[0x11] << 8) | (dev->ide_regs[0x10] & 0xf8); + side = ((dev->ide_regs[0x15] << 8) | (dev->ide_regs[0x14] & 0xfc)) + 2; + } else { + main = 0x1f0; + side = 0x3f6; + } + ide_set_base(0, main); + ide_set_side(0, side); + + if (dev->ide_regs[0x09] & 0x04) { + main = (dev->ide_regs[0x19] << 8) | (dev->ide_regs[0x18] & 0xf8); + side = ((dev->ide_regs[0x1d] << 8) | (dev->ide_regs[0x1c] & 0xfc)) + 2; + } else { + main = 0x170; + side = 0x376; + } + ide_set_base(1, main); + ide_set_side(1, side); + + if (dev->ide_regs[0x04] & PCI_COMMAND_IO) { + if (dev->ide_regs[0x40] & 0x02) + ide_pri_enable(); + if (dev->ide_regs[0x40] & 0x01) + ide_sec_enable(); + } +} + + +static void +via_vt82c586b_bus_master_handlers(via_vt82c586b_t *dev, uint16_t old_base) +{ + uint16_t base; + base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8); + + sff_bus_master_handlers(dev->bm[0], old_base, base, (dev->ide_regs[0x04] & 1)); + sff_bus_master_handlers(dev->bm[1], old_base + 8, base + 8, (dev->ide_regs[0x04] & 1)); +} + + +static uint8_t +via_vt82c586b_read(int func, int addr, void *priv) +{ + via_vt82c586b_t *dev = (via_vt82c586b_t *) priv; + + uint8_t ret = 0xff; + int c; + + switch(func) { + case 0: + if ((addr >= 0x60) && (addr <= 0x6f)) { + c = (addr & 0x0e) >> 1; + if (addr & 0x01) + ret = (dma[c].ab & 0x0000ff00) >> 8; + else { + ret = (dma[c].ab & 0x000000f0); + ret |= (!!(dma_e & (1 << c)) << 3); + } + } else + ret = dev->pci_isa_regs[addr]; + break; + case 1: + ret = dev->ide_regs[addr]; + break; + case 2: + ret = dev->usb_regs[addr]; + break; + case 3: + ret = dev->power_regs[addr]; + break; + } + + return ret; +} + + +static uint8_t +usb_reg_read(uint16_t addr, void *p) +{ + uint8_t ret = 0xff; + + switch (addr & 0x1f) { + case 0x10: case 0x11: case 0x12: case 0x13: + /* Port status */ + ret = 0x00; + break; + } + + return ret; +} + + +static void +usb_reg_write(uint16_t addr, uint8_t val, void *p) +{ +} + + +static void +nvr_update_io_mapping(via_vt82c586b_t *dev) +{ + if (dev->nvr_enabled) + nvr_at_handler(0, 0x0074, dev->nvr); + + if ((dev->pci_isa_regs[0x5b] & 0x02) && (dev->pci_isa_regs[0x48] & 0x08)) + nvr_at_handler(1, 0x0074, dev->nvr); +} + + +static void +usb_update_io_mapping(via_vt82c586b_t *dev) +{ + if (dev->usb.io_base != 0x0000) + io_removehandler(dev->usb.io_base, 0x20, usb_reg_read, NULL, NULL, usb_reg_write, NULL, NULL, dev); + + dev->usb.io_base = (dev->usb_regs[0x20] & ~0x1f) | (dev->usb_regs[0x21] << 8); + + if ((dev->usb_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) && (dev->usb.io_base != 0x0000)) + io_sethandler(dev->usb.io_base, 0x20, usb_reg_read, NULL, NULL, usb_reg_write, NULL, NULL, dev); +} + + +static uint8_t +power_reg_read(uint16_t addr, void *p) +{ + via_vt82c586b_t *dev = (via_vt82c586b_t *) p; + + uint32_t timer; + uint8_t ret = 0xff; + + switch (addr & 0xff) { + case 0x08: case 0x09: case 0x0a: case 0x0b: + /* ACPI timer */ + timer = (tsc * ACPI_TIMER_FREQ) / machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed; + if (!(dev->power_regs[0x41] & ACPI_TIMER_32BIT)) + timer &= 0x00ffffff; + ret = (timer >> (8 * (addr & 3))) & 0xff; + break; + } + + return ret; +} + + +static void +power_reg_write(uint16_t addr, uint8_t val, void *p) +{ +} + + +static void +power_update_io_mapping(via_vt82c586b_t *dev) +{ + if (dev->power.io_base != 0x0000) + io_removehandler(dev->power.io_base, 0x100, power_reg_read, NULL, NULL, power_reg_write, NULL, NULL, dev); + + dev->power.io_base = dev->power_regs[0x41] | (dev->power_regs[0x49] << 8); + + if ((dev->power_regs[0x41] & ACPI_IO_ENABLE) && (dev->power.io_base != 0x0000)) + io_sethandler(dev->power.io_base, 0x100, power_reg_read, NULL, NULL, power_reg_write, NULL, NULL, dev); +} + + +static void +via_vt82c586b_write(int func, int addr, uint8_t val, void *priv) +{ + via_vt82c586b_t *dev = (via_vt82c586b_t *) priv; + + uint16_t old_base, base; + int c; + + if (func > 3) + return; + + old_base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8); + + switch(func) { + case 0: /* PCI-ISA bridge */ + /* Read-only addresses */ + if ((addr < 4) || (addr == 5) || (addr == 6) || ((addr >= 8) && (addr < 0x40)) || + (addr == 0x49) || (addr == 0x4b) || ((addr >= 0x51) && (addr < 0x54)) || ((addr >= 0x5d) && (addr < 0x60)) || + ((addr >= 0x68) && (addr < 0x6a)) || (addr >= 0x73)) + return; + + switch (addr) { + case 0x04: + dev->pci_isa_regs[0x04] = (val & 8) | 7; + break; + case 0x06: + dev->pci_isa_regs[0x06] &= ~(val & 0xb0); + break; + + case 0x47: + if ((val & 0x81) == 0x81) + resetx86(); + pci_elcr_set_enabled(!!(val & 0x20)); + dev->pci_isa_regs[0x47] = val & 0xfe; + break; + case 0x48: + dev->pci_isa_regs[0x48] = val; + nvr_update_io_mapping(dev); + break; + + case 0x54: + pci_set_irq_level(PCI_INTA, !(val & 8)); + pci_set_irq_level(PCI_INTB, !(val & 4)); + pci_set_irq_level(PCI_INTC, !(val & 2)); + pci_set_irq_level(PCI_INTD, !(val & 1)); + break; + case 0x55: + pci_set_irq_routing(PCI_INTD, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED); + pci_set_mirq_routing(PCI_MIRQ0, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); + dev->pci_isa_regs[0x55] = val; + break; + case 0x56: + pci_set_irq_routing(PCI_INTA, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTB, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); + dev->pci_isa_regs[0x56] = val; + break; + case 0x57: + pci_set_irq_routing(PCI_INTC, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED); + pci_set_mirq_routing(PCI_MIRQ1, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); + dev->pci_isa_regs[0x57] = val; + break; + case 0x58: + pci_set_mirq_routing(PCI_MIRQ2, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); + dev->pci_isa_regs[0x58] = val; + break; + case 0x5b: + dev->pci_isa_regs[0x5b] = val; + nvr_update_io_mapping(dev); + break; + + case 0x60: case 0x62: case 0x64: case 0x66: + case 0x68: case 0x6a: case 0x6c: case 0x6e: + c = (addr & 0x0e) >> 1; + dma[c].ab = (dma[c].ab & 0xffffff0f) | (val & 0xf0); + dma[c].ac = (dma[c].ac & 0xffffff0f) | (val & 0xf0); + if (val & 0x08) + dma_e |= (1 << c); + else + dma_e &= ~(1 << c); + break; + case 0x61: case 0x63: case 0x65: case 0x67: + case 0x69: case 0x6b: case 0x6d: case 0x6f: + c = (addr & 0x0e) >> 1; + dma[c].ab = (dma[c].ab & 0xffff00ff) | (val << 8); + dma[c].ac = (dma[c].ac & 0xffff00ff) | (val << 8); + break; + + case 0x70: case 0x71: case 0x72: case 0x73: + dev->pci_isa_regs[(addr - 0x44)] = val; + break; + } + break; + + case 1: /* IDE regs */ + /* Read-only addresses */ + if ((addr < 4) || (addr == 5) || (addr == 8) || ((addr >= 0xa) && (addr < 0x0d)) || + ((addr >= 0x0e) && (addr < 0x10)) || ((addr >= 0x12) && (addr < 0x13)) || + ((addr >= 0x16) && (addr < 0x17)) || ((addr >= 0x1a) && (addr < 0x1b)) || + ((addr >= 0x1e) && (addr < 0x1f)) || ((addr >= 0x22) && (addr < 0x3c)) || + ((addr >= 0x3e) && (addr < 0x40)) || ((addr >= 0x54) && (addr < 0x60)) || + ((addr >= 0x52) && (addr < 0x68)) || (addr >= 0x62)) + return; + + switch (addr) { + case 0x04: + base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8); + dev->ide_regs[0x04] = val & 0x85; + via_vt82c586b_ide_handlers(dev); + via_vt82c586b_bus_master_handlers(dev, base); + break; + case 0x06: + dev->ide_regs[0x06] &= ~(val & 0xb0); + break; + + case 0x09: + dev->ide_regs[0x09] = (val & 0x05) | 0x8a; + via_vt82c586b_ide_handlers(dev); + break; + + case 0x10: + dev->ide_regs[0x10] = (val & 0xf8) | 1; + via_vt82c586b_ide_handlers(dev); + break; + case 0x11: + dev->ide_regs[0x11] = val; + via_vt82c586b_ide_handlers(dev); + break; + + case 0x14: + dev->ide_regs[0x14] = (val & 0xfc) | 1; + via_vt82c586b_ide_handlers(dev); + break; + case 0x15: + dev->ide_regs[0x15] = val; + via_vt82c586b_ide_handlers(dev); + break; + + case 0x18: + dev->ide_regs[0x18] = (val & 0xf8) | 1; + via_vt82c586b_ide_handlers(dev); + break; + case 0x19: + dev->ide_regs[0x19] = val; + via_vt82c586b_ide_handlers(dev); + break; + + case 0x1c: + dev->ide_regs[0x1c] = (val & 0xfc) | 1; + via_vt82c586b_ide_handlers(dev); + break; + case 0x1d: + dev->ide_regs[0x1d] = val; + via_vt82c586b_ide_handlers(dev); + break; + + case 0x20: + dev->ide_regs[0x20] = (val & 0xf0) | 1; + via_vt82c586b_bus_master_handlers(dev, old_base); + break; + case 0x21: + dev->ide_regs[0x21] = val; + via_vt82c586b_bus_master_handlers(dev, old_base); + break; + + case 0x3d: + sff_set_irq_mode(dev->bm[0], val); + sff_set_irq_mode(dev->bm[1], val); + break; + + case 0x40: + dev->ide_regs[0x40] = val; + via_vt82c586b_ide_handlers(dev); + break; + + default: + dev->ide_regs[addr] = val; + break; + } + break; + + case 2: + /* Read-only addresses */ + if ((addr < 4) || (addr == 5) || (addr == 6) || ((addr >= 8) && (addr < 0xd)) || + ((addr >= 0xe) && (addr < 0x20)) || ((addr >= 0x22) && (addr < 0x3c)) || + ((addr >= 0x3e) && (addr < 0x40)) || ((addr >= 0x42) && (addr < 0x44)) || + ((addr >= 0x46) && (addr < 0xc0)) || (addr >= 0xc2)) + return; + + switch (addr) { + case 0x04: + dev->usb_regs[0x04] = val & 0x97; + break; + case 0x07: + dev->usb_regs[0x07] = val & 0x7f; + break; + + case 0x20: + dev->usb_regs[0x20] = (val & ~0x1f) | 1; + usb_update_io_mapping(dev); + break; + case 0x21: + dev->usb_regs[0x21] = val; + usb_update_io_mapping(dev); + break; + + default: + dev->usb_regs[addr] = val; + break; + } + break; + + case 3: + /* Read-only addresses */ + if ((addr < 0xd) || ((addr >= 0xe && addr < 0x40)) || (addr == 0x43) || (addr == 0x48) || + ((addr >= 0x4a) && (addr < 0x50)) || (addr >= 0x54)) + return; + + switch (addr) { + case 0x41: case 0x49: + dev->power_regs[addr] = val; + power_update_io_mapping(dev); + break; + + default: + dev->power_regs[addr] = val; + break; + } + } +} + + +static void +*via_vt82c586b_init(const device_t *info) +{ + via_vt82c586b_t *dev = (via_vt82c586b_t *) malloc(sizeof(via_vt82c586b_t)); + memset(dev, 0, sizeof(via_vt82c586b_t)); + + pci_add_card(7, via_vt82c586b_read, via_vt82c586b_write, dev); + + dev->bm[0] = device_add_inst(&sff8038i_device, 1); + sff_set_slot(dev->bm[0], 7); + sff_set_irq_mode(dev->bm[0], 0); + sff_set_irq_pin(dev->bm[0], PCI_INTA); + + dev->bm[1] = device_add_inst(&sff8038i_device, 2); + sff_set_slot(dev->bm[1], 7); + sff_set_irq_mode(dev->bm[1], 0); + sff_set_irq_pin(dev->bm[1], PCI_INTA); + + dev->nvr = device_add(&via_nvr_device); + + via_vt82c586b_reset_hard(dev); + + device_add(&port_92_pci_device); + + dma_alias_set(); + + pci_enable_mirq(0); + pci_enable_mirq(1); + pci_enable_mirq(2); + + return dev; +} + +static void +via_vt82c586b_close(void *p) +{ + via_vt82c586b_t *via_vt82c586b = (via_vt82c586b_t *)p; + + free(via_vt82c586b); +} + +const device_t via_vt82c586b_device = +{ + "VIA VT82C586B", + DEVICE_PCI, + 0, + via_vt82c586b_init, + via_vt82c586b_close, + NULL, + NULL, + NULL, + NULL, + NULL +}; diff --git a/src/vt82c586b.h b/src/via_vt82c586b.h similarity index 65% rename from src/vt82c586b.h rename to src/via_vt82c586b.h index cfec19e9f..c2fd06a57 100644 --- a/src/vt82c586b.h +++ b/src/via_vt82c586b.h @@ -1,22 +1,20 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * Emulation of the VIA Apollo MVP3 southbridge - * - * Version: @(#)via_mvp3_sb.c 1.0.22 2018/10/31 - * - * Authors: Sarah Walker, - * Miran Grca, - * Melissa Goad, - * - * Copyright 2008-2020 Sarah Walker. - * Copyright 2016-2020 Miran Grca. - * Copyright 2020 Melissa Goad. - */ - -#if defined(DEV_BRANCH) && defined(USE_SS7) -extern const device_t vt82c586b_device; -#endif \ No newline at end of file +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * Emulation of the VIA Apollo MVP3 southbridge + * + * Version: @(#)via_vt82c586b.c 1.0.0 2020/01/14 + * + * Authors: Sarah Walker, + * Miran Grca, + * Melissa Goad, + * + * Copyright 2008-2020 Sarah Walker. + * Copyright 2016-2020 Miran Grca. + * Copyright 2020 Melissa Goad. + */ + +extern const device_t via_vt82c586b_device; diff --git a/src/vt82c586b.c b/src/vt82c586b.c deleted file mode 100644 index f53e1ed61..000000000 --- a/src/vt82c586b.c +++ /dev/null @@ -1,444 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * Emulation of the VIA VT82C586B southbridge - * - * Version: @(#)vt82c586b.c 1.0.22 2018/10/31 - * - * Authors: Sarah Walker, - * Miran Grca, - * Melissa Goad, - * - * Copyright 2008-2020 Sarah Walker. - * Copyright 2016-2020 Miran Grca. - * Copyright 2020 Melissa Goad. - */ - -#include -#include -#include -#include -#include -#include -#define HAVE_STDARG_H -#include "86box.h" -#include "cdrom/cdrom.h" -#include "cpu/cpu.h" -#include "scsi/scsi_device.h" -#include "scsi/scsi_cdrom.h" -#include "dma.h" -#include "io.h" -#include "device.h" -#include "apm.h" -#include "keyboard.h" -#include "mem.h" -#include "pci.h" -#include "pic.h" -#include "port_92.h" -#include "disk/hdc.h" -#include "disk/hdc_ide.h" -#include "disk/hdc_ide_sff8038i.h" -#include "disk/zip.h" -#include "machine/machine.h" -#include "vt82c586b.h" - -typedef struct -{ - uint8_t pci_isa_regs[256]; - uint8_t ide_regs[256]; - uint8_t usb_regs[256]; - uint8_t power_regs[256]; - sff8038i_t *bm[2]; -} vt82c586b_t; - -static void -vt82c586b_reset_hard(void *priv) -{ - vt82c586b_t *vt82c586b = (vt82c586b_t *) priv; - - uint16_t old_base = (vt82c586b->ide_regs[0x20] & 0xf0) | (vt82c586b->ide_regs[0x21] << 8); - - sff_bus_master_reset(vt82c586b->bm[0], old_base); - sff_bus_master_reset(vt82c586b->bm[1], old_base + 8); - - memset(vt82c586b->pci_isa_regs, 0, 256); - memset(vt82c586b->ide_regs, 0, 256); - memset(vt82c586b->usb_regs, 0, 256); - memset(vt82c586b->power_regs, 0, 256); - - vt82c586b->pci_isa_regs[0x00] = 0x06; vt82c586b->pci_isa_regs[0x01] = 0x11; /*VIA*/ - vt82c586b->pci_isa_regs[0x02] = 0x86; vt82c586b->pci_isa_regs[0x03] = 0x05; /*VT82C586B*/ - vt82c586b->pci_isa_regs[0x04] = 0x0f; - vt82c586b->pci_isa_regs[0x07] = 0x02; - vt82c586b->pci_isa_regs[0x0a] = 0x01; - vt82c586b->pci_isa_regs[0x0b] = 0x06; - vt82c586b->pci_isa_regs[0x0e] = 0x80; - - vt82c586b->pci_isa_regs[0x48] = 0x01; - vt82c586b->pci_isa_regs[0x4a] = 0x04; - vt82c586b->pci_isa_regs[0x4f] = 0x03; - - vt82c586b->pci_isa_regs[0x50] = 0x24; - vt82c586b->pci_isa_regs[0x59] = 0x04; - - //IDE registers - vt82c586b->ide_regs[0x00] = 0x06; vt82c586b->ide_regs[0x01] = 0x11; /*VIA*/ - vt82c586b->ide_regs[0x02] = 0x71; vt82c586b->ide_regs[0x03] = 0x05; /*VT82C586B*/ - vt82c586b->ide_regs[0x04] = 0x80; - vt82c586b->ide_regs[0x06] = 0x80; vt82c586b->ide_regs[0x07] = 0x02; - vt82c586b->ide_regs[0x09] = 0x85; - vt82c586b->ide_regs[0x0a] = 0x01; - vt82c586b->ide_regs[0x0b] = 0x01; - - vt82c586b->ide_regs[0x10] = 0xf0; vt82c586b->ide_regs[0x11] = 0x01; - vt82c586b->ide_regs[0x14] = 0xf4; vt82c586b->ide_regs[0x15] = 0x03; - vt82c586b->ide_regs[0x18] = 0x70; vt82c586b->ide_regs[0x19] = 0x01; - vt82c586b->ide_regs[0x1c] = 0x74; vt82c586b->ide_regs[0x1d] = 0x03; - vt82c586b->ide_regs[0x20] = 0x01; vt82c586b->ide_regs[0x21] = 0xcc; - - vt82c586b->ide_regs[0x3c] = 0x0e; - - vt82c586b->ide_regs[0x40] = 0x08; - vt82c586b->ide_regs[0x41] = 0x02; - vt82c586b->ide_regs[0x42] = 0x09; - vt82c586b->ide_regs[0x43] = 0x3a; - vt82c586b->ide_regs[0x44] = 0x68; - vt82c586b->ide_regs[0x46] = 0xc0; - vt82c586b->ide_regs[0x48] = 0xa8; vt82c586b->ide_regs[0x49] = 0xa8; - vt82c586b->ide_regs[0x4a] = 0xa8; vt82c586b->ide_regs[0x4b] = 0xa8; - vt82c586b->ide_regs[0x4c] = 0xff; - vt82c586b->ide_regs[0x4e] = 0xff; - vt82c586b->ide_regs[0x4f] = 0xff; - vt82c586b->ide_regs[0x50] = 0x03; vt82c586b->ide_regs[0x51] = 0x03; - vt82c586b->ide_regs[0x52] = 0x03; vt82c586b->ide_regs[0x53] = 0x03; - - vt82c586b->ide_regs[0x61] = 0x02; - vt82c586b->ide_regs[0x69] = 0x02; - - vt82c586b->usb_regs[0x00] = 0x06; vt82c586b->usb_regs[0x01] = 0x11; /*VIA*/ - vt82c586b->usb_regs[0x02] = 0x38; vt82c586b->usb_regs[0x03] = 0x30; - vt82c586b->usb_regs[0x04] = 0x00; vt82c586b->usb_regs[0x05] = 0x00; - vt82c586b->usb_regs[0x06] = 0x00; vt82c586b->usb_regs[0x07] = 0x02; - vt82c586b->usb_regs[0x0a] = 0x03; - vt82c586b->usb_regs[0x0b] = 0x0c; - vt82c586b->usb_regs[0x0d] = 0x16; - vt82c586b->usb_regs[0x20] = 0x01; - vt82c586b->usb_regs[0x21] = 0x03; - vt82c586b->usb_regs[0x3d] = 0x04; - - vt82c586b->usb_regs[0x60] = 0x10; - vt82c586b->usb_regs[0xc1] = 0x20; - - vt82c586b->power_regs[0x00] = 0x06; vt82c586b->power_regs[0x01] = 0x11; /*VIA*/ - vt82c586b->power_regs[0x02] = 0x40; vt82c586b->power_regs[0x03] = 0x30; - vt82c586b->power_regs[0x04] = 0x00; vt82c586b->power_regs[0x05] = 0x00; - vt82c586b->power_regs[0x06] = 0x80; vt82c586b->power_regs[0x07] = 0x02; - vt82c586b->power_regs[0x08] = 0x10; /*Production version (3041)*/ - vt82c586b->power_regs[0x48] = 0x01; - - pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); - pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); - pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED); - pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); - - pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED); - pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED); - pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED); - - ide_pri_disable(); - ide_sec_disable(); -} - -static void -vt82c586b_bus_master_handlers(vt82c586b_t *dev, uint16_t old_base) -{ - uint16_t base; - - base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8); - - sff_bus_master_handlers(dev->bm[0], old_base, base, (dev->ide_regs[0x04] & 1)); - sff_bus_master_handlers(dev->bm[1], old_base + 8, base + 8, (dev->ide_regs[0x04] & 1)); -} - -static uint8_t -vt82c586b_read(int func, int addr, void *priv) -{ - vt82c586b_t *dev = (vt82c586b_t *) priv; - - switch(func) - { - case 0: - { - return dev->pci_isa_regs[addr]; - } - case 1: - { - return dev->ide_regs[addr]; - } - case 2: - { - return dev->usb_regs[addr]; - } - case 3: - { - return dev->power_regs[addr]; - } - default: - { - return 0xff; - } - } -} - -static void -vt82c586b_write(int func, int addr, uint8_t val, void *priv) -{ - vt82c586b_t *dev = (vt82c586b_t *) priv; - uint16_t old_base; - - if(func > 3) return; - - old_base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8); - - switch(func) - { - case 0: //PCI-ISA bridge - { - /*Read-only addresses*/ - if ((addr < 4) || (addr == 5) || (addr == 6) - || (addr >= 8 && addr < 0x40) - || (addr == 0x49) - || (addr == 0x4b) - || (addr >= 0x51 && addr < 0x54) - || (addr >= 0x5d && addr < 0x60) - || (addr >= 0x68 && addr < 0x6a) - || (addr >= 0x71)) - return; - - switch(addr) - { - case 0x04: - dev->pci_isa_regs[0x04] = (val & 8) | 7; - break; - case 0x06: - dev->pci_isa_regs[0x06] &= ~(val & 0xb0); - break; - - case 0x47: - if((val & 0x81) == 0x81) resetx86(); - if(val & 0x20) pci_elcr_set_enabled(1); - else pci_elcr_set_enabled(0); - dev->pci_isa_regs[0x47] = val & 0xfe; - break; - - case 0x54: - if(val & 8) pci_set_irq_level(PCI_INTA, 0); - else pci_set_irq_level(PCI_INTA, 1); - if(val & 4) pci_set_irq_level(PCI_INTB, 0); - else pci_set_irq_level(PCI_INTB, 1); - if(val & 2) pci_set_irq_level(PCI_INTC, 0); - else pci_set_irq_level(PCI_INTC, 1); - if(val & 1) pci_set_irq_level(PCI_INTD, 0); - else pci_set_irq_level(PCI_INTD, 1); - break; - - case 0x55: - if(!(val & 0xf0)) pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); - else pci_set_irq_routing(PCI_INTD, val >> 4); - - if(!(val & 0x0f)) pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED); - else pci_set_mirq_routing(PCI_MIRQ0, val & 0xf); - dev->pci_isa_regs[0x55] = val; - break; - - case 0x56: - if(!(val & 0xf0)) pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); - else pci_set_irq_routing(PCI_INTA, val >> 4); - - if(!(val & 0x0f)) pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); - else pci_set_irq_routing(PCI_INTB, val & 0xf); - dev->pci_isa_regs[0x56] = val; - break; - - case 0x57: - if(!(val & 0xf0)) pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED); - else pci_set_irq_routing(PCI_INTC, val >> 4); - - if(!(val & 0x0f)) pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED); - else pci_set_mirq_routing(PCI_MIRQ1, val & 0xf); - dev->pci_isa_regs[0x57] = val; - break; - - case 0x58: - if(!(val & 0x0f)) pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED); - else pci_set_mirq_routing(PCI_MIRQ2, val & 0xf); - dev->pci_isa_regs[0x58] = val; - } - break; - } - case 1: /*IDE regs*/ - { - /*Read-only addresses*/ - if ((addr < 4) || (addr == 5) || (addr == 8) - || (addr >= 0xa && addr < 0x0d) - || (addr >= 0x0e && addr < 0x20) - || (addr >= 0x22 && addr < 0x3c) - || (addr >= 0x3d && addr < 0x40) - || (addr >= 0x54 && addr < 0x60) - || (addr >= 0x52 && addr < 0x68) - || (addr >= 0x62)) - return; - - switch(addr) - { - case 0x04: - { - uint16_t base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8); - ide_pri_disable(); - ide_sec_disable(); - if(val & PCI_COMMAND_IO) - { - if(dev->ide_regs[0x40] & 0x02) ide_pri_enable(); - if(dev->ide_regs[0x40] & 0x01) ide_sec_enable(); - } - vt82c586b_bus_master_handlers(dev, base); - dev->ide_regs[0x04] = val & 0x85; - break; - } - case 0x06: - dev->ide_regs[0x06] &= ~(val & 0xb0); - break; - - case 0x09: - dev->ide_regs[0x09] = (dev->pci_isa_regs[0x09] & ~0x70) | 0x8a; - break; - - case 0x20: - { - dev->ide_regs[0x20] = (val & 0xf0) | 1; - vt82c586b_bus_master_handlers(dev, old_base); - break; - } - - case 0x21: - { - dev->ide_regs[0x21] = val; - vt82c586b_bus_master_handlers(dev, old_base); - break; - } - - case 0x40: - { - dev->ide_regs[0x40] = val; - ide_pri_disable(); - ide_sec_disable(); - if(val & PCI_COMMAND_IO) - { - if(dev->ide_regs[0x40] & 0x02) ide_pri_enable(); - if(dev->ide_regs[0x40] & 0x01) ide_sec_enable(); - } - break; - } - - default: - dev->ide_regs[addr] = val; - break; - } - break; - } - case 2: - { - /*Read-only addresses*/ - if ((addr < 4) || (addr == 5) || (addr == 6) - || (addr >= 8 && addr < 0xd) - || (addr >= 0xe && addr < 0x20) - || (addr >= 0x22 && addr < 0x3c) - || (addr >= 0x3e && addr < 0x40) - || (addr >= 0x42 && addr < 0x44) - || (addr >= 0x46 && addr < 0xc0) - || (addr >= 0xc2)) - return; - - switch(addr) - { - case 0x04: - dev->usb_regs[0x04] = val & 0x97; - break; - case 0x07: - dev->usb_regs[0x07] = val & 0x7f; - break; - - case 0x20: - dev->usb_regs[0x20] = (val & ~0x1f) | 1; - break; - - default: - dev->usb_regs[addr] = val; - break; - } - break; - } - case 3: - { - /*Read-only addresses*/ - if ((addr < 0xd) || (addr >= 0xe && addr < 0x40) - || (addr == 0x43) - || (addr == 0x48) - || (addr >= 0x4a && addr < 0x50) - || (addr >= 0x54)) - return; - - dev->power_regs[addr] = val; - break; - } - } -} - -static void -*vt82c586b_init(const device_t *info) -{ - vt82c586b_t *vt82c586b = (vt82c586b_t *) malloc(sizeof(vt82c586b_t)); - memset(vt82c586b, 0, sizeof(vt82c586b_t)); - - pci_add_card(7, vt82c586b_read, vt82c586b_write, vt82c586b); - - vt82c586b->bm[0] = device_add_inst(&sff8038i_device, 1); - vt82c586b->bm[1] = device_add_inst(&sff8038i_device, 2); - - vt82c586b_reset_hard(vt82c586b); - - device_add(&port_92_pci_device); - - dma_alias_set(); - - pci_enable_mirq(0); - pci_enable_mirq(1); - pci_enable_mirq(2); - - return vt82c586b; -} - -static void -vt82c586b_close(void *p) -{ - vt82c586b_t *vt82c586b = (vt82c586b_t *)p; - - free(vt82c586b); -} - -const device_t vt82c586b_device = -{ - "VIA VT82C586B", - DEVICE_PCI, - 0, - vt82c586b_init, - vt82c586b_close, - NULL, - NULL, - NULL, - NULL, - NULL -}; \ No newline at end of file diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index 901ac9215..a2f5b3329 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -8,7 +8,7 @@ # # Makefile for Win32 (MinGW32) environment. # -# Version: @(#)Makefile.mingw 1.0.140 2019/12/21 +# Version: @(#)Makefile.mingw 1.0.141 2020/01/14 # # Authors: Miran Grca, # Fred N. van Kempen, @@ -543,7 +543,7 @@ CXXFLAGS := $(CFLAGS) ######################################################################### MAINOBJ := pc.o config.o random.o timer.o io.o apm_new.o dma.o nmi.o \ pic.o pit.o port_92.o ppi.o pci.o mca.o mcr.o mem.o \ - rom.o device.o nvr.o nvr_at.o nvr_ps2.o $(VNCOBJ) $(RDPOBJ) + rom.o device.o nvr.o nvr_at.o nvr_ps2.o sst_flash.o via_vt82c586b.o $(VNCOBJ) $(RDPOBJ) INTELOBJ := intel_flash.o \ intel_sio.o intel_piix.o @@ -557,7 +557,7 @@ CPUOBJ := cpu.o cpu_table.o \ CHIPSETOBJ := acc2168.o acer_m3a.o ali1429.o headland.o \ intel_4x0.o neat.o opti495.o scat.o \ sis_85c471.o sis_85c496.o \ - wd76c10.o + via_mvp3.o wd76c10.o MCHOBJ := machine.o machine_table.o \ m_xt.o m_xt_compaq.o \ diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index 10d6aa481..fee58bd0c 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -8,7 +8,7 @@ # # Makefile for Win32 (MinGW32) environment. # -# Version: @(#)Makefile.mingw 1.0.140 2019/12/21 +# Version: @(#)Makefile.mingw 1.0.141 2020/01/14 # # Authors: Miran Grca, # Fred N. van Kempen, @@ -74,9 +74,6 @@ ifeq ($(DEV_BUILD), y) ifndef PS2M70T4 PS2M70T4 := y endif - ifndef SS7 - SS7 := y - endif ifndef TI TI := y endif @@ -141,9 +138,6 @@ else ifndef PS2M70T4 PS2M70T4 := n endif - ifndef SS7 - SS7 := n - endif ifndef TI TI := n endif @@ -506,11 +500,6 @@ ifeq ($(PS2M70T4), y) OPTS += -DUSE_PS2M70T4 endif -ifeq ($(SS7),y) -OPTS += -DUSE_SS7 -DEVBROBJ += via_mvp3.o vt82c586b.o sst_flash.o -endif - ifeq ($(TI), y) OPTS += -DUSE_TI endif @@ -560,7 +549,7 @@ CXXFLAGS := $(CFLAGS) ######################################################################### MAINOBJ := pc.o config.o random.o timer.o io.o apm_new.o dma.o nmi.o \ pic.o pit.o port_92.o ppi.o pci.o mca.o mcr.o mem_new.o \ - rom.o device.o nvr.o nvr_at.o nvr_ps2.o $(VNCOBJ) $(RDPOBJ) + rom.o device.o nvr.o nvr_at.o nvr_ps2.o sst_flash.o via_vt82c586b.o $(VNCOBJ) $(RDPOBJ) INTELOBJ := intel_flash.o \ intel_sio.o intel_piix.o @@ -574,7 +563,7 @@ CPUOBJ := cpu.o cpu_table.o \ CHIPSETOBJ := acc2168.o acer_m3a.o ali1429.o headland.o \ intel_4x0.o neat.o opti495.o scat.o \ sis_85c471.o sis_85c496.o \ - wd76c10.o + via_mvp3.o wd76c10.o MCHOBJ := machine.o machine_table_new.o \ m_xt.o m_xt_compaq.o \