80486DX2-66/86Box-fork
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Fixed a number of bug sin various modules, VS440FX mostly works now (one bug on soft reset is missing which is left to be debugged).

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This commit is contained in:
OBattler
2020-06-15 17:08:42 +02:00
parent 1d27587182
commit 6c6cae0965
10 changed files with 55 additions and 36 deletions
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6
src/chipset/intel_420ex.c
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@@ -353,8 +353,10 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
dev->regs[addr] = val & 0xff; dev->regs[addr] = val & 0xff;
apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80)); apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80));
break; break;
case 0xaa: case 0xac: case 0xae: case 0xaa:
if (dev->id == 0x03) dev->regs[addr] &= (val & 0xff);
break;
case 0xac: case 0xae:
dev->regs[addr] = val & 0xff; dev->regs[addr] = val & 0xff;
break; break;
case 0xa4: case 0xa4:

29
src/chipset/intel_piix.c
View File

@@ -478,11 +478,11 @@ piix_write(int func, int addr, uint8_t val, void *priv)
apm_set_do_smi(dev->apm, !!(fregs[0xa0] & 0x01) && !!(val & 0x80)); apm_set_do_smi(dev->apm, !!(fregs[0xa0] & 0x01) && !!(val & 0x80));
} }
break; break;
case 0xaa: case 0xac: case 0xae: case 0xac: case 0xae:
if (dev->type < 4) if (dev->type < 4)
fregs[addr] = val & 0xff; fregs[addr] = val & 0xff;
break; break;
case 0xa3: case 0xab: case 0xa3:
if (dev->type == 3) if (dev->type == 3)
fregs[addr] = val & 0x01; fregs[addr] = val & 0x01;
break; break;
@@ -522,6 +522,14 @@ piix_write(int func, int addr, uint8_t val, void *priv)
timer_on_auto(&dev->fast_off_timer, dev->fast_off_period); timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
} }
break; break;
case 0xaa:
if (dev->type < 4)
fregs[addr] &= val;
break;
case 0xab:
if (dev->type == 3)
fregs[addr] &= (val & 0x01);
break;
case 0xb0: case 0xb0:
if (dev->type == 4) if (dev->type == 4)
fregs[addr] = (fregs[addr] & 0x8c) | (val & 0x73); fregs[addr] = (fregs[addr] & 0x8c) | (val & 0x73);
@@ -753,16 +761,16 @@ piix_write(int func, int addr, uint8_t val, void *priv)
fregs[addr] = val & 0x01; fregs[addr] = val & 0x01;
break; break;
case 0x6a: case 0x6a:
if (dev->type == 4) if (dev->type <= 4)
fregs[0x6a] = val & 0x01; fregs[0x6a] = val & 0x01;
break; break;
case 0xc0: case 0xc0:
if (dev->type == 4) if (dev->type <= 4)
fregs[0xc0] = val; fregs[0xc0] = (fregs[0xc0] & ~(val & 0xbf)) | (val & 0x20);
break; break;
case 0xc1: case 0xc1:
if (dev->type == 4) if (dev->type <= 4)
fregs[0xc1] = val & 0xbf; fregs[0xc1] &= ~val;
break; break;
case 0xff: case 0xff:
if (dev->type == 4) { if (dev->type == 4) {
@@ -871,6 +879,9 @@ piix_read(int func, int addr, void *priv)
piix_t *dev = (piix_t *) priv; piix_t *dev = (piix_t *) priv;
uint8_t ret = 0xff, *fregs; uint8_t ret = 0xff, *fregs;
if ((dev->type == 3) && (func == 2) && (dev->max_func == 1) && (addr >= 0x40))
ret = 0x00;
/* Return on unsupported function. */ /* Return on unsupported function. */
if ((func <= dev->max_func) || ((func == 1) && (dev->max_func == 0))) { if ((func <= dev->max_func) || ((func == 1) && (dev->max_func == 0))) {
fregs = (uint8_t *) dev->regs[func]; fregs = (uint8_t *) dev->regs[func];
@@ -993,6 +1004,8 @@ piix_reset_hard(piix_t *dev)
fregs[0x69] = 0x02; fregs[0x69] = 0x02;
if ((dev->type == 1) && (dev->rev != 2)) if ((dev->type == 1) && (dev->rev != 2))
fregs[0x6a] = 0x04; fregs[0x6a] = 0x04;
else if (dev->type == 3)
fregs[0x6a] = 0x10;
fregs[0x70] = (dev->type < 4) ? 0x80 : 0x00; fregs[0x70] = (dev->type < 4) ? 0x80 : 0x00;
fregs[0x71] = (dev->type < 3) ? 0x80 : 0x00; fregs[0x71] = (dev->type < 3) ? 0x80 : 0x00;
if (dev->type <= 4) { if (dev->type <= 4) {
@@ -1063,7 +1076,7 @@ piix_reset_hard(piix_t *dev)
fregs[0xc1] = 0x20; fregs[0xc1] = 0x20;
fregs[0xff] = (dev->type > 3) ? 0x10 : 0x00; fregs[0xff] = (dev->type > 3) ? 0x10 : 0x00;
} }
dev->max_func = 1; /* It starts with USB disabled, then enables it. */ dev->max_func = 2; /* It starts with USB disabled, then enables it. */
} }
/* Function 3: Power Management */ /* Function 3: Power Management */

6
src/chipset/intel_sio.c
View File

@@ -276,7 +276,11 @@ sio_write(int func, int addr, uint8_t val, void *priv)
apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80)); apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80));
} }
break; break;
case 0xaa: case 0xac: case 0xae: case 0xaa:
if (dev->id == 0x03)
dev->regs[addr] &= (val & 0xff);
break;
case 0xac: case 0xae:
if (dev->id == 0x03) if (dev->id == 0x03)
dev->regs[addr] = val & 0xff; dev->regs[addr] = val & 0xff;
break; break;

4
src/cpu/cpu.c
View File

@@ -2764,7 +2764,7 @@ void cpu_RDMSR()
case 0x1B: case 0x1B:
EAX = apic_base_msr & 0xffffffff; EAX = apic_base_msr & 0xffffffff;
EDX = apic_base_msr >> 32; EDX = apic_base_msr >> 32;
/* pclog("APIC_BASE read : %08X%08X\n", EDX, EAX); */ cpu_log("APIC_BASE read : %08X%08X\n", EDX, EAX);
break; break;
case 0x2A: case 0x2A:
EAX = 0xC4000000; EAX = 0xC4000000;
@@ -3268,7 +3268,7 @@ void cpu_WRMSR()
ecx17_msr = EAX | ((uint64_t)EDX << 32); ecx17_msr = EAX | ((uint64_t)EDX << 32);
break; break;
case 0x1B: case 0x1B:
/* pclog("APIC_BASE write: %08X%08X\n", EDX, EAX); */ cpu_log("APIC_BASE write: %08X%08X\n", EDX, EAX);
// apic_base_msr = EAX | ((uint64_t)EDX << 32); // apic_base_msr = EAX | ((uint64_t)EDX << 32);
break; break;
case 0x2A: case 0x2A:

1
src/device/postcard.c
View File

@@ -79,6 +79,7 @@ postcard_setui(void)
int len = strlen(postcard_str); int len = strlen(postcard_str);
postcard_str[len + 1] = '\0'; postcard_str[len + 1] = '\0';
postcard_str[len] = '\n'; postcard_str[len] = '\n';
postcard_log("[%04X:%08X] ", CS, cpu_state.pc);
postcard_log(postcard_str); postcard_log(postcard_str);
} }
} }

12
src/io.c
View File

@@ -307,7 +307,7 @@ inb(uint16_t port)
if (!found) if (!found)
sub_cycles(io_delay); sub_cycles(io_delay);
io_log("(%i, %i, %04i) in b(%04X) = %02X\n", in_smm, found, qfound, port, ret); io_log("[%04X:%08X] (%i, %i, %04i) in b(%04X) = %02X\n", CS, cpu_state.pc, in_smm, found, qfound, port, ret);
return(ret); return(ret);
} }
@@ -338,7 +338,7 @@ outb(uint16_t port, uint8_t val)
#endif #endif
} }
io_log("(%i, %i, %04i) outb(%04X, %02X)\n", in_smm, found, qfound, port, val); io_log("[%04X:%08X] (%i, %i, %04i) outb(%04X, %02X)\n", CS, cpu_state.pc, in_smm, found, qfound, port, val);
return; return;
} }
@@ -389,7 +389,7 @@ inw(uint16_t port)
if (!found) if (!found)
sub_cycles(io_delay); sub_cycles(io_delay);
io_log("(%i, %i, %04i) in w(%04X) = %04X\n", in_smm, found, qfound, port, ret); io_log("[%04X:%08X] (%i, %i, %04i) in w(%04X) = %04X\n", CS, cpu_state.pc, in_smm, found, qfound, port, ret);
return ret; return ret;
} }
@@ -433,7 +433,7 @@ outw(uint16_t port, uint16_t val)
#endif #endif
} }
io_log("(%i, %i, %04i) outw(%04X, %04X)\n", in_smm, found, qfound, port, val); io_log("[%04X:%08X] (%i, %i, %04i) outw(%04X, %04X)\n", CS, cpu_state.pc, in_smm, found, qfound, port, val);
return; return;
} }
@@ -503,7 +503,7 @@ inl(uint16_t port)
sub_cycles(io_delay); sub_cycles(io_delay);
if (in_smm) if (in_smm)
io_log("(%i, %i, %04i) in l(%04X) = %08X\n", in_smm, found, qfound, port, ret); io_log("[%04X:%08X] (%i, %i, %04i) in l(%04X) = %08X\n", CS, cpu_state.pc, in_smm, found, qfound, port, ret);
return ret; return ret;
} }
@@ -562,7 +562,7 @@ outl(uint16_t port, uint32_t val)
#endif #endif
} }
io_log("(%i, %i, %04i) outl(%04X, %08X)\n", in_smm, found, qfound, port, val); io_log("[%04X:%08X] (%i, %i, %04i) outl(%04X, %08X)\n", CS, cpu_state.pc, in_smm, found, qfound, port, val);
return; return;
} }

11
src/machine/m_at_socket8.c
View File

@@ -148,15 +148,16 @@ machine_at_vs440fx_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1); pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i440fx_device); device_add(&i440fx_device);
device_add(&piix3_device); device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device); device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&pc87307_device); device_add(&pc87307_device);
device_add(&intel_flash_bxt_ami_device); device_add(&intel_flash_bxt_ami_device);
return ret; return ret;

11
src/sio/sio_pc87307.c
View File

@@ -154,10 +154,10 @@ fdc_handler(pc87307_t *dev)
fdc_remove(dev->fdc); fdc_remove(dev->fdc);
active = (dev->ld_regs[0x03][0x00] & 0x01) && (dev->pm[0x00] & 0x08); active = (dev->ld_regs[0x03][0x00] & 0x01) && (dev->pm[0x00] & 0x08);
addr = ((dev->ld_regs[0x03][0x30] << 8) | dev->ld_regs[0x00][0x31]) - 0x0002; addr = ((dev->ld_regs[0x03][0x30] << 8) | dev->ld_regs[0x03][0x31]) - 0x0002;
irq = (dev->ld_regs[0x03][0x40] & 0x0f); irq = (dev->ld_regs[0x03][0x40] & 0x0f);
if (active) { if (active && (addr <= 0xfff2)) {
fdc_set_base(dev->fdc, addr); fdc_set_base(dev->fdc, addr);
fdc_set_irq(dev->fdc, irq); fdc_set_irq(dev->fdc, irq);
} }
@@ -176,7 +176,7 @@ lpt1_handler(pc87307_t *dev)
addr = (dev->ld_regs[0x04][0x30] << 8) | dev->ld_regs[0x04][0x31]; addr = (dev->ld_regs[0x04][0x30] << 8) | dev->ld_regs[0x04][0x31];
irq = (dev->ld_regs[0x04][0x40] & 0x0f); irq = (dev->ld_regs[0x04][0x40] & 0x0f);
if (active) { if (active && (addr <= 0xfffc)) {
lpt1_init(addr); lpt1_init(addr);
lpt1_irq(irq); lpt1_irq(irq);
} }
@@ -195,7 +195,7 @@ serial_handler(pc87307_t *dev, int uart)
addr = (dev->ld_regs[0x06 - uart][0x30] << 8) | dev->ld_regs[0x06 - uart][0x31]; addr = (dev->ld_regs[0x06 - uart][0x30] << 8) | dev->ld_regs[0x06 - uart][0x31];
irq = (dev->ld_regs[0x06 - uart][0x40] & 0x0f); irq = (dev->ld_regs[0x06 - uart][0x40] & 0x0f);
if (active) if (active && (addr <= 0xfff8))
serial_setup(dev->uart[uart], addr, irq); serial_setup(dev->uart[uart], addr, irq);
} }
@@ -355,7 +355,6 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
case 0x74: case 0x75: case 0x74: case 0x75:
switch (dev->regs[0x07]) { switch (dev->regs[0x07]) {
case 0x03: case 0x03:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xfa;
fdc_handler(dev); fdc_handler(dev);
break; break;
case 0x04: case 0x04:
@@ -434,7 +433,7 @@ pc87307_reset(pc87307_t *dev)
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
memset(dev->ld_regs[i], 0x00, 0xd0); memset(dev->ld_regs[i], 0x00, 0xd0);
memset(dev->pcregs, 0x00, 0x10); memset(dev->pcregs, 0x00, 0x10);
memset(dev->gpio, 0x00, 0x08); memset(dev->gpio, 0xff, 0x08);
memset(dev->pm, 0x00, 0x08); memset(dev->pm, 0x00, 0x08);
dev->regs[0x20] = dev->id; dev->regs[0x20] = dev->id;

1
src/sio/sio_pc87309.c
View File

@@ -283,7 +283,6 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
case 0x74: case 0x75: case 0x74: case 0x75:
switch (dev->regs[0x07]) { switch (dev->regs[0x07]) {
case 0x00: case 0x00:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xfa;
fdc_handler(dev); fdc_handler(dev);
break; break;
case 0x01: case 0x01:

4
src/win/Makefile.mingw
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@@ -560,8 +560,8 @@ CPUOBJ := cpu.o cpu_table.o \
$(DYNARECOBJ) $(DYNARECOBJ)
CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \ CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \
intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o neat.o \ intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
opti495.o opti5x7.o scamp.o scat.o \ neat.o opti495.o opti5x7.o scamp.o scat.o \
sis_85c310.o sis_85c471.o sis_85c496.o \ sis_85c310.o sis_85c471.o sis_85c496.o \
via_apollo.o via_vpx.o via_vt82c586b.o via_vt82c596b.o wd76c10.o via_apollo.o via_vpx.o via_vt82c586b.o via_vt82c596b.o wd76c10.o