From 73714e8130f5bfb727f8a49fe8ec32e4fd33c792 Mon Sep 17 00:00:00 2001
From: Alexander Babikov <2708460+lemondrops@users.noreply.github.com>
Date: Sun, 17 Oct 2021 02:38:26 +0500
Subject: [PATCH] Report correct cache info in CPUID on P6-family CPUs

---
 src/cpu/cpu.c | 35 +++++++++++++++++++++++++++++------
 1 file changed, 29 insertions(+), 6 deletions(-)

diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c
index 1ea8b2dde..1f3e1ce58 100644
--- a/src/cpu/cpu.c
+++ b/src/cpu/cpu.c
@@ -2373,9 +2373,14 @@ cpu_CPUID(void)
                 EBX = ECX = 0;
                 EDX       = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_CMOV;
             } else if (EAX == 2) {
-                EAX = 0x00000001;
+                EAX = 0x03020101; /* Instruction TLB: 4 KB pages, 4-way set fully associative, 32 entries
+                                     Instruction TLB: 4 MB pages, fully associative, 2 entries
+                                     Data TLB: 4 KB pages, 4-way set associative, 64 entries */
                 EBX = ECX = 0;
-                EDX       = 0x00000000;
+                EDX       = 0x0C040842; /* Data TLB: 4 MB pages, 4-way set associative, 8 entries
+                                           Level 1 instruction cache: 16 KB, 4-way set associative, 32 byte line size
+                                           Level 1 data cache: 16 KB, 4-way set associative, 32 byte line size
+                                           Level 2 cache: 256 KB, 4-way set associative, 32 byte line size */
             } else
                 EAX = EBX = ECX = EDX = 0;
             break;
@@ -2391,9 +2396,14 @@ cpu_CPUID(void)
                 EBX = ECX = 0;
                 EDX       = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_CMOV;
             } else if (EAX == 2) {
-                EAX = 0x00000001;
+                EAX = 0x03020101; /* Instruction TLB: 4 KB pages, 4-way set fully associative, 32 entries
+                                     Instruction TLB: 4 MB pages, fully associative, 2 entries
+                                     Data TLB: 4 KB pages, 4-way set associative, 64 entries */
                 EBX = ECX = 0;
-                EDX       = 0x00000000;
+                EDX       = 0x0C040843; /* Data TLB: 4 MB pages, 4-way set associative, 8 entries
+                                           Level 1 instruction cache: 16 KB, 4-way set associative, 32 byte line size
+                                           Level 1 data cache: 16 KB, 4-way set associative, 32 byte line size
+                                           Level 2 cache: 512 KB, 4-way set associative, 32 byte line size */
             } else
                 EAX = EBX = ECX = EDX = 0;
             break;
@@ -2409,9 +2419,22 @@ cpu_CPUID(void)
                 EBX = ECX = 0;
                 EDX       = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_FXSR | CPUID_CMOV;
             } else if (EAX == 2) {
-                EAX = 0x00000001;
+                EAX = 0x03020101; /* Instruction TLB: 4 KB pages, 4-way set fully associative, 32 entries
+                                     Instruction TLB: 4 MB pages, fully associative, 2 entries
+                                     Data TLB: 4 KB pages, 4-way set associative, 64 entries */
                 EBX = ECX = 0;
-                EDX       = 0x00000000;
+                if (cpu_f->package == CPU_PKG_SLOT2) /* Pentium II Xeon Drake */
+                    EDX = 0x0C040844; /* Data TLB: 4 MB pages, 4-way set associative, 8 entries
+                                         Level 1 instruction cache: 16 KB, 4-way set associative, 32 byte line size
+                                         Level 1 data cache: 16 KB, 4-way set associative, 32 byte line size
+                                         Level 2 cache: 1 MB, 4-way set associative, 32 byte line size */
+                else if (!strncmp(cpu_f->internal_name, "celeron", 7)) { /* Celeron */
+                    if (CPUID >= 0x660) /* Mendocino */
+                        EDX = 0x0C040841; /* Level 2 cache: 128 KB, 4-way set associative, 32 byte line size */
+                    else /* Covington */
+                        EDX = 0x0C040840; /* No Level 2 cache */
+                } else /* Pentium II Deschutes and OverDrive */
+                    EDX = 0x0C040843; /* Level 2 cache: 512 KB, 4-way set associative, 32 byte line size */
             } else
                 EAX = EBX = ECX = EDX = 0;
             break;