From 73bdd27ba85d508125c3770d012ecc75ac5ea52d Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 10 Jun 2021 05:07:32 +0200
Subject: [PATCH] Fixed PIIX MIRQ routing so MIRQ1 routing is no longer
 incorrectly applied to MIRQ0.

---
 src/chipset/intel_piix.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/chipset/intel_piix.c b/src/chipset/intel_piix.c
index 96d34d7d4..2c3e0fa89 100644
--- a/src/chipset/intel_piix.c
+++ b/src/chipset/intel_piix.c
@@ -396,9 +396,9 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 			else
 				fregs[addr] = val & 0xcf;
 			if (val & 0x80)
-				pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
+				pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), PCI_IRQ_DISABLED);
 			else
-				pci_set_mirq_routing(PCI_MIRQ0, val & 0xf);
+				pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), val & 0xf);
 			piix_log("MIRQ%i is %s\n", addr & 0x01, (val & 0x20) ? "disabled" : "enabled");
 		}
 		break;