From 76f3f08d785597ea00c7f29bc70fb81a22577a87 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Tue, 13 Apr 2021 03:47:46 +0200
Subject: [PATCH] The Intel SIO and PIIX* southbridges now have the
 undocumented (by the datasheets, but fully documented by the Intel
 motherboard technical specifications) second PIT on ports 48h-4Bh.

---
 src/chipset/intel_piix.c |  2 ++
 src/chipset/intel_sio.c  |  2 ++
 src/include/86box/pit.h  |  1 +
 src/pit.c                | 18 ++++++++++++++++--
 4 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/src/chipset/intel_piix.c b/src/chipset/intel_piix.c
index 2c6ed1500..50d345448 100644
--- a/src/chipset/intel_piix.c
+++ b/src/chipset/intel_piix.c
@@ -1374,6 +1374,8 @@ static void
     else
 	dev->board_config[1] |= 0x00;
 
+    device_add(&i8254_sec_device);
+
     return dev;
 }
 
diff --git a/src/chipset/intel_sio.c b/src/chipset/intel_sio.c
index ed1c141b1..91f9128a0 100644
--- a/src/chipset/intel_sio.c
+++ b/src/chipset/intel_sio.c
@@ -539,6 +539,8 @@ sio_init(const device_t *info)
 
     timer_add(&dev->timer, NULL, NULL, 0);
 
+    device_add(&i8254_sec_device);
+
     return dev;
 }
 
diff --git a/src/include/86box/pit.h b/src/include/86box/pit.h
index 027955c69..bf8d71048 100644
--- a/src/include/86box/pit.h
+++ b/src/include/86box/pit.h
@@ -109,6 +109,7 @@ extern void	pit_handler(int set, uint16_t base, int size, void *priv);
 #ifdef EMU_DEVICE_H
 extern const device_t	i8253_device;
 extern const device_t	i8254_device;
+extern const device_t	i8254_sec_device;
 extern const device_t	i8254_ext_io_device;
 extern const device_t	i8254_ps2_device;
 #endif
diff --git a/src/pit.c b/src/pit.c
index a4b865f1c..9db4c45dd 100644
--- a/src/pit.c
+++ b/src/pit.c
@@ -63,6 +63,7 @@ int64_t		firsttime = 1;
 #define PIT_PS2			16	/* The PIT is the PS/2's second PIT. */
 #define PIT_EXT_IO		32	/* The PIT has externally specified port I/O. */
 #define PIT_CUSTOM_CLOCK	64	/* The PIT uses custom clock inputs provided by another provider. */
+#define PIT_SECONDARY		128	/* The PIT is secondary (ports 0048-004B). */
 
 
 enum {
@@ -826,8 +827,10 @@ pit_init(const device_t *info)
 
     dev->flags = info->local;
 
-    if (!(dev->flags & PIT_EXT_IO))
-	io_sethandler(0x0040, 0x0004, pit_read, NULL, NULL, pit_write, NULL, NULL, dev);
+    if (!(dev->flags & PIT_EXT_IO)) {
+	io_sethandler((dev->flags & PIT_SECONDARY) ? 0x0048 : 0x0040, 0x0004,
+		      pit_read, NULL, NULL, pit_write, NULL, NULL, dev);
+    }
 
     return dev;
 }
@@ -855,6 +858,17 @@ const device_t i8254_device =
 };
 
 
+const device_t i8254_sec_device =
+{
+        "Intel 8254 Programmable Interval Timer (Secondary)",
+        DEVICE_ISA,
+	PIT_8254 | PIT_SECONDARY,
+        pit_init, pit_close, NULL,
+        { NULL }, NULL, NULL,
+	NULL
+};
+
+
 const device_t i8254_ext_io_device =
 {
         "Intel 8254 Programmable Interval Timer (External I/O)",