From 78a44d845b70899f7855c5641b1ac111b9e77550 Mon Sep 17 00:00:00 2001 From: OBattler Date: Fri, 4 Nov 2016 22:32:23 +0100 Subject: [PATCH] Fixed a bug regarding 86F images and extra bit cells; Brought the Intel Flash emulation in line with mainline PCem; Removed the Intel Advanced/ML; Reverted the ET4000/W32p code back to the code from mainline PCem, with fixes to PCI and linear frame buffer addresses according to the datasheet; Timer counters are now 32-bit again - fixes quite a few bugs. --- src/disc_86f.c | 2 +- src/ibm.h | 2 - src/intel_flash.c | 257 ++++++----------------------- src/intel_flash.h | 4 - src/model.c | 6 +- src/pic.c | 13 +- src/pic.h | 3 - src/pit.c | 49 +++--- src/pit.h | 4 - src/timer.c | 19 +-- src/timer.h | 23 ++- src/vid_et4000w32.c | 391 +++++++++++--------------------------------- src/vid_et4000w32.h | 5 - src/vid_svga.c | 4 +- src/video.c | 2 - 15 files changed, 192 insertions(+), 592 deletions(-) diff --git a/src/disc_86f.c b/src/disc_86f.c index ef2c450a8..feb0bbe76 100644 --- a/src/disc_86f.c +++ b/src/disc_86f.c @@ -2552,7 +2552,7 @@ void d86f_write_track(int drive, int side, uint16_t *da0, uint16_t *sa0) fwrite(&(d86f[drive].side_flags[side]), 1, 2, d86f[drive].f); - if (d86f_has_surface_desc(drive)) + if (d86f_has_extra_bit_cells(drive)) { fwrite(&(d86f[drive].extra_bit_cells[side]), 1, 4, d86f[drive].f); } diff --git a/src/ibm.h b/src/ibm.h index 516145257..fb5f17985 100644 --- a/src/ibm.h +++ b/src/ibm.h @@ -449,7 +449,6 @@ enum GFX_PHOENIX_TRIO64, /*S3 764/Trio64 (Phoenix)*/ GFX_INCOLOR, /* Hercules InColor */ GFX_COLORPLUS, /* Plantronics ColorPlus */ - GFX_ET4000W32C, /*Tseng ET4000/W32p (Cardex) (STG RAMDAC) */ GFX_COMPAQ_EGA, /*Compaq EGA*/ GFX_SUPER_EGA, /*Using Chips & Technologies SuperEGA BIOS*/ GFX_COMPAQ_VGA, /*Compaq/Paradise VGA*/ @@ -458,7 +457,6 @@ enum GFX_VGAWONDERXL, /*Compaq ATI VGA Wonder XL (28800-5)*/ GFX_WD90C11, /*Paradise WD90C11 Standalone*/ GFX_OTI077, /*Oak OTI-077*/ - GFX_ET4000W32CS, /*Tseng ET4000/W32p (Cardex) (ICS RAMDAC) */ GFX_VGAWONDERXL24, /*Compaq ATI VGA Wonder XL24 (28800-6)*/ GFX_STEALTH64, /*S3 Vision864 (Diamond Stealth 64)*/ GFX_PHOENIX_VISION864, /*S3 Vision864 (Phoenix)*/ diff --git a/src/intel_flash.c b/src/intel_flash.c index f1d78f342..79a6ecc31 100644 --- a/src/intel_flash.c +++ b/src/intel_flash.c @@ -1,18 +1,14 @@ -/* Copyright holders: Sarah Walker, Tenshi - see COPYING for more details -*/ #include #include "ibm.h" #include "device.h" #include "mem.h" -#define FLASH_ALLOW_16 4 #define FLASH_IS_BXB 2 #define FLASH_INVERT 1 #define BLOCK_MAIN 0 -#define BLOCK_DMI 1 -#define BLOCK_ESCD 2 +#define BLOCK_DATA1 1 +#define BLOCK_DATA2 2 #define BLOCK_BOOT 3 enum @@ -24,23 +20,20 @@ enum CMD_ERASE_SETUP = 0x20, CMD_ERASE_CONFIRM = 0xd0, CMD_ERASE_SUSPEND = 0xb0, - CMD_PROGRAM_SETUP = 0x40, - CMD_PROGRAM_SETUP2 = 0x10 + CMD_PROGRAM_SETUP = 0x40 }; typedef struct flash_t { - uint32_t command, status; - uint32_t flash_id; - uint8_t type; /* 0 = BXT, 1 = BXB */ - uint8_t invert_high_pin; /* 0 = no, 1 = yes */ - uint8_t allow_word_write; /* 0 = no, 1 = yes */ + uint8_t command, status; + uint8_t flash_id; + int invert_high_pin; mem_mapping_t mapping[8], mapping_h[8]; uint32_t block_start[4], block_end[4], block_len[4]; uint8_t array[131072]; } flash_t; -char flash_path[1024]; +static char flash_path[1024]; static uint8_t flash_read(uint32_t addr, void *p) { @@ -71,35 +64,10 @@ static uint8_t flash_read(uint32_t addr, void *p) static uint16_t flash_readw(uint32_t addr, void *p) { - // pclog("flash_readw(%08X)\n", addr); flash_t *flash = (flash_t *)p; - if (!flash->allow_word_write) - { - addr &= 0x1ffff; - if (flash->invert_high_pin) addr ^= 0x10000; - return *(uint16_t *)&(flash->array[addr]); - } - if (flash->invert_high_pin) - { - addr ^= 0x10000; - if (addr & 0xfff00000) *(uint16_t *)&(flash->array[addr & 0x1ffff]); - } addr &= 0x1ffff; - switch (flash->command) - { - case CMD_READ_ARRAY: - default: - return *(uint16_t *)&(flash->array[addr]); - - case CMD_IID: - // pclog("Flash Read ID 16: %08X\n", addr); - if (addr & 1) - return 0x2274; - return 0x89; - - case CMD_READ_STATUS: - return flash->status; - } + if (flash->invert_high_pin) addr ^= 0x10000; + return *(uint16_t *)&(flash->array[addr]); } static uint32_t flash_readl(uint32_t addr, void *p) @@ -142,7 +110,6 @@ static void flash_write(uint32_t addr, uint8_t val, void *p) break; case CMD_PROGRAM_SETUP: - case CMD_PROGRAM_SETUP2: // pclog("flash_write: program %05x %02x\n", addr, val); if ((addr & 0x1e000) != (flash->block_start[3] & 0x1e000)) flash->array[addr] = val; @@ -161,93 +128,26 @@ static void flash_write(uint32_t addr, uint8_t val, void *p) } } -static void flash_writew(uint32_t addr, uint16_t val, void *p) -{ - flash_t *flash = (flash_t *)p; - int i; - // pclog("flash_writew : addr=%08x val=%02x command=%02x %04x:%08x\n", addr, val, flash->command, CS, cpu_state.pc); - - if (flash->invert_high_pin) - { - addr ^= 0x10000; - if (addr & 0xfff00000) return; - } - addr &= 0x1ffff; - - switch (flash->command) - { - case CMD_ERASE_SETUP: - if (val == CMD_ERASE_CONFIRM) - { - // pclog("flash_writew: erase %05x\n", addr); - - for (i = 0; i < 3; i++) - { - if ((addr >= flash->block_start[i]) && (addr <= flash->block_end[i])) - memset(&(flash->array[flash->block_start[i]]), 0xff, flash->block_len[i]); - } - - flash->status = 0x80; - } - flash->command = CMD_READ_STATUS; - break; - - case CMD_PROGRAM_SETUP: - case CMD_PROGRAM_SETUP2: - // pclog("flash_writew: program %05x %02x\n", addr, val); - if ((addr & 0x1e000) != (flash->block_start[3] & 0x1e000)) - *(uint16_t *)&(flash->array[addr]) = val; - flash->command = CMD_READ_STATUS; - flash->status = 0x80; - break; - - default: - flash->command = val; - switch (val) - { - case CMD_CLEAR_STATUS: - flash->status = 0; - break; - } - } -} - -void intel_flash_add_mappings(flash_t *flash) +static void intel_flash_add_mappings(flash_t *flash) { int i = 0; for (i = 0; i <= 7; i++) { - if (flash->allow_word_write) - { - mem_mapping_add(&(flash->mapping[i]), 0xe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, flash_writew, mem_write_nulll, flash->array + ((i << 14) & 0x1ffff), MEM_MAPPING_EXTERNAL, (void *)flash); - mem_mapping_add(&(flash->mapping_h[i]), 0xfffe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, flash_writew, mem_write_nulll, flash->array + ((i << 14) & 0x1ffff), 0, (void *)flash); - } - else - { - mem_mapping_add(&(flash->mapping[i]), 0xe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, mem_write_nullw, mem_write_nulll, flash->array + ((i << 14) & 0x1ffff), MEM_MAPPING_EXTERNAL, (void *)flash); - mem_mapping_add(&(flash->mapping_h[i]), 0xfffe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, mem_write_nullw, mem_write_nulll, flash->array + ((i << 14) & 0x1ffff), 0, (void *)flash); - } + mem_mapping_add(&(flash->mapping[i]), 0xe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, mem_write_nullw, mem_write_nulll, flash->array + ((i << 14) & 0x1ffff), MEM_MAPPING_EXTERNAL, (void *)flash); + mem_mapping_add(&(flash->mapping_h[i]), 0xfffe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, mem_write_nullw, mem_write_nulll, flash->array + ((i << 14) & 0x1ffff), 0, (void *)flash); } } /* This is for boards which invert the high pin - the flash->array pointers need to pointer invertedly in order for INTERNAL writes to go to the right part of the array. */ -void intel_flash_add_mappings_inverted(flash_t *flash) +static void intel_flash_add_mappings_inverted(flash_t *flash) { int i = 0; for (i = 0; i <= 7; i++) { - if (flash->allow_word_write) - { - mem_mapping_add(&(flash->mapping[i]), 0xe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, flash_writew, mem_write_nulll, flash->array + (((i << 14) ^ 0x10000) & 0x1ffff), MEM_MAPPING_EXTERNAL, (void *)flash); - mem_mapping_add(&(flash->mapping_h[i]), 0xfffe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, flash_writew, mem_write_nulll, flash->array + (((i << 14) ^ 0x10000) & 0x1ffff), 0, (void *)flash); - } - else - { - mem_mapping_add(&(flash->mapping[i]), 0xe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, mem_write_nullw, mem_write_nulll, flash->array + (((i << 14) ^ 0x10000) & 0x1ffff), MEM_MAPPING_EXTERNAL, (void *)flash); - mem_mapping_add(&(flash->mapping_h[i]), 0xfffe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, mem_write_nullw, mem_write_nulll, flash->array + (((i << 14) ^ 0x10000) & 0x1ffff), 0, (void *)flash); - } + mem_mapping_add(&(flash->mapping[i]), 0xe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, mem_write_nullw, mem_write_nulll, flash->array + (((i << 14) ^ 0x10000) & 0x1ffff), MEM_MAPPING_EXTERNAL, (void *)flash); + mem_mapping_add(&(flash->mapping_h[i]), 0xfffe0000 + (i << 14), 0x04000, flash_read, flash_readw, flash_readl, flash_write, mem_write_nullw, mem_write_nulll, flash->array + (((i << 14) ^ 0x10000) & 0x1ffff), 0, (void *)flash); } } @@ -255,13 +155,9 @@ void *intel_flash_init(uint8_t type) { FILE *f; flash_t *flash = malloc(sizeof(flash_t)); + memset(flash, 0, sizeof(flash_t)); char fpath[1024]; int i; - memset(flash, 0, sizeof(flash_t)); - - // pclog("Initializing Flash (type = %i)\n", type); - - memset(flash_path, 0, 1024); switch(romset) { @@ -301,41 +197,41 @@ void *intel_flash_init(uint8_t type) case ROM_THOR: strcpy(flash_path, "roms/thor/"); break; + default: + fatal("intel_flash_init on unsupported ROM set %i\n", romset); } // pclog("Flash init: Path is: %s\n", flash_path); - flash->type = (type & 2) ? 1 : 0; - flash->flash_id = (!flash->type) ? 0x94 : 0x95; - flash->invert_high_pin = (type & 1); - flash->allow_word_write = (type & 4) ? 1 : 0; + flash->flash_id = (type & FLASH_IS_BXB) ? 0x95 : 0x94; + flash->invert_high_pin = (type & FLASH_INVERT); /* The block lengths are the same both flash types. */ - flash->block_len[0] = 0x1c000; - flash->block_len[1] = 0x01000; - flash->block_len[2] = 0x01000; - flash->block_len[3] = 0x02000; + flash->block_len[BLOCK_MAIN] = 0x1c000; + flash->block_len[BLOCK_DATA1] = 0x01000; + flash->block_len[BLOCK_DATA2] = 0x01000; + flash->block_len[BLOCK_BOOT] = 0x02000; - if(flash->type) /* 28F001BX-B */ + if (type & FLASH_IS_BXB) /* 28F001BX-B */ { - flash->block_start[0] = 0x04000; /* MAIN BLOCK */ - flash->block_end[0] = 0x1ffff; - flash->block_start[1] = 0x03000; /* DMI BLOCK */ - flash->block_end[1] = 0x03fff; - flash->block_start[2] = 0x04000; /* ESCD BLOCK */ - flash->block_end[2] = 0x04fff; - flash->block_start[3] = 0x00000; /* BOOT BLOCK */ - flash->block_end[3] = 0x01fff; + flash->block_start[BLOCK_MAIN] = 0x04000; /* MAIN BLOCK */ + flash->block_end[BLOCK_MAIN] = 0x1ffff; + flash->block_start[BLOCK_DATA1] = 0x03000; /* DATA AREA 1 BLOCK */ + flash->block_end[BLOCK_DATA1] = 0x03fff; + flash->block_start[BLOCK_DATA2] = 0x04000; /* DATA AREA 2 BLOCK */ + flash->block_end[BLOCK_DATA2] = 0x04fff; + flash->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */ + flash->block_end[BLOCK_BOOT] = 0x01fff; } else /* 28F001BX-T */ { - flash->block_start[0] = 0x00000; /* MAIN BLOCK */ - flash->block_end[0] = 0x1bfff; - flash->block_start[1] = 0x1c000; /* DMI BLOCK */ - flash->block_end[1] = 0x1cfff; - flash->block_start[2] = 0x1d000; /* ESCD BLOCK */ - flash->block_end[2] = 0x1dfff; - flash->block_start[3] = 0x1e000; /* BOOT BLOCK */ - flash->block_end[3] = 0x1ffff; + flash->block_start[BLOCK_MAIN] = 0x00000; /* MAIN BLOCK */ + flash->block_end[BLOCK_MAIN] = 0x1bfff; + flash->block_start[BLOCK_DATA1] = 0x1c000; /* DATA AREA 1 BLOCK */ + flash->block_end[BLOCK_DATA1] = 0x1cfff; + flash->block_start[BLOCK_DATA2] = 0x1d000; /* DATA AREA 2 BLOCK */ + flash->block_end[BLOCK_DATA2] = 0x1dfff; + flash->block_start[BLOCK_BOOT] = 0x1e000; /* BOOT BLOCK */ + flash->block_end[BLOCK_BOOT] = 0x1ffff; } for (i = 0; i < 8; i++) @@ -366,34 +262,14 @@ void *intel_flash_init(uint8_t type) flash->command = CMD_READ_ARRAY; flash->status = 0; - /* Load the main block. */ - memset(fpath, 0, 1024); strcpy(fpath, flash_path); - strcat(fpath, "main.bin"); + strcat(fpath, "flash.bin"); f = romfopen(fpath, "rb"); if (f) { fread(&(flash->array[flash->block_start[BLOCK_MAIN]]), flash->block_len[BLOCK_MAIN], 1, f); - fclose(f); - } - - /* Load the DMI block. */ - strcpy(fpath, flash_path); - strcat(fpath, "dmi.bin"); - f = romfopen(fpath, "rb"); - if (f) - { - fread(&(flash->array[flash->block_start[BLOCK_DMI]]), flash->block_len[BLOCK_DMI], 1, f); - fclose(f); - } - - /* Load the ESCD block. */ - strcpy(fpath, flash_path); - strcat(fpath, "escd.bin"); - f = romfopen(fpath, "rb"); - if (f) - { - fread(&(flash->array[flash->block_start[BLOCK_ESCD]]), flash->block_len[BLOCK_ESCD], 1, f); + fread(&(flash->array[flash->block_start[BLOCK_DATA1]]), flash->block_len[BLOCK_DATA1], 1, f); + fread(&(flash->array[flash->block_start[BLOCK_DATA2]]), flash->block_len[BLOCK_DATA2], 1, f); fclose(f); } @@ -406,12 +282,6 @@ void *intel_flash_bxt_ami_init() return intel_flash_init(FLASH_INVERT); } -/* For later AMI BIOS'es - Intel 28F100BXT with high address pin inverted and 16-bit write capability. */ -void *intel_flash_100bxt_ami_init() -{ - return intel_flash_init(FLASH_INVERT | FLASH_ALLOW_16); -} - /* For Award BIOS'es - Intel 28F001BXT with high address pin not inverted. */ void *intel_flash_bxt_init() { @@ -431,30 +301,14 @@ void intel_flash_close(void *p) char fpath[1024]; - // pclog("Flash close: Path is: %s\n", flash_path); - - /* Save the main block. */ - memset(fpath, 0, 1024); strcpy(fpath, flash_path); - strcat(fpath, "main.bin"); + strcat(fpath, "flash.bin"); f = romfopen(fpath, "wb"); fwrite(&(flash->array[flash->block_start[BLOCK_MAIN]]), flash->block_len[BLOCK_MAIN], 1, f); + fwrite(&(flash->array[flash->block_start[BLOCK_DATA1]]), flash->block_len[BLOCK_DATA1], 1, f); + fwrite(&(flash->array[flash->block_start[BLOCK_DATA2]]), flash->block_len[BLOCK_DATA2], 1, f); fclose(f); - - /* Save the DMI block. */ - strcpy(fpath, flash_path); - strcat(fpath, "dmi.bin"); - f = romfopen(fpath, "wb"); - fwrite(&(flash->array[flash->block_start[BLOCK_DMI]]), flash->block_len[BLOCK_DMI], 1, f); - fclose(f); - - /* Save the ESCD block. */ - strcpy(fpath, flash_path); - strcat(fpath, "escd.bin"); - f = romfopen(fpath, "wb"); - fwrite(&(flash->array[flash->block_start[BLOCK_ESCD]]), flash->block_len[BLOCK_ESCD], 1, f); - fclose(f); - + free(flash); } @@ -471,19 +325,6 @@ device_t intel_flash_bxt_ami_device = NULL }; -device_t intel_flash_100bxt_ami_device = -{ - "Intel 28F100BXT Flash BIOS", - 0, - intel_flash_100bxt_ami_init, - intel_flash_close, - NULL, - NULL, - NULL, - NULL, - NULL -}; - device_t intel_flash_bxt_device = { "Intel 28F001BXT Flash BIOS", @@ -499,7 +340,7 @@ device_t intel_flash_bxt_device = device_t intel_flash_bxb_device = { - "Intel 28F001BXT Flash BIOS", + "Intel 28F001BXB Flash BIOS", 0, intel_flash_bxb_init, intel_flash_close, diff --git a/src/intel_flash.h b/src/intel_flash.h index ff8fb372b..e8e0c1bc7 100644 --- a/src/intel_flash.h +++ b/src/intel_flash.h @@ -1,7 +1,3 @@ -/* Copyright holders: Sarah Walker, Tenshi - see COPYING for more details -*/ extern device_t intel_flash_bxt_ami_device; -extern device_t intel_flash_100bxt_ami_device; extern device_t intel_flash_bxt_device; extern device_t intel_flash_bxb_device; diff --git a/src/model.c b/src/model.c index dd226764e..d5e184750 100644 --- a/src/model.c +++ b/src/model.c @@ -157,7 +157,7 @@ MODEL models[] = {"PC Partner MB500N", ROM_MB500N, { "Intel", cpus_PentiumS5,"IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, 1, 1, 128, 1, at_mb500n_init}, {"Intel Advanced/ATX", ROM_THOR, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 256, 1, at_endeavor_init}, // {"ASUS P/I-P54TP4XE", ROM_P54TP4XE, { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, 1, 1, 512, 1, at_p54tp4xe_init}, - {"Intel Advanced/ML", ROM_MARL, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 512, 1, at_marl_init}, + // {"Intel Advanced/ML", ROM_MARL, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 512, 1, at_marl_init}, {"Acer M3a", ROM_ACERM3A, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 512, 1, at_acerm3a_init}, {"Acer V35N", ROM_ACERV35N, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 512, 1, at_acerv35n_init}, // {"ASUS P/I-P55T2P4", ROM_P55T2P4, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 512, 1, at_p55t2p4_init}, @@ -499,11 +499,13 @@ void at_endeavor_init() device_add(&intel_flash_bxt_ami_device); } +#if 0 void at_marl_init() { at_advanced_common_init(); - device_add(&intel_flash_100bxt_ami_device); + // device_add(&intel_flash_100bxt_ami_device); } +#endif void at_mb500n_init() { diff --git a/src/pic.c b/src/pic.c index 1fb4dfda7..66cf5f3fa 100644 --- a/src/pic.c +++ b/src/pic.c @@ -1,6 +1,3 @@ -/* Copyright holders: Sarah Walker, Tenshi - see COPYING for more details -*/ #include "ibm.h" #include "io.h" #include "pic.h" @@ -27,15 +24,13 @@ void pic_updatepending() void pic_reset() { pic.icw=0; - // pic.mask=0xFF; - pic.mask=0; + pic.mask=0xFF; pic.mask2=0; pic.pend=pic.ins=0; pic.vector=8; pic.read=1; pic2.icw=0; - // pic2.mask=0xFF; - pic2.mask=0; + pic2.mask=0xFF; pic.mask2=0; pic2.pend=pic2.ins=0; pic_intpending = 0; @@ -110,7 +105,7 @@ void pic_write(uint16_t addr, uint8_t val, void *priv) { if (val&16) /*ICW1*/ { - pic.mask=0; + pic.mask = 0; pic.mask2=0; pic.icw=1; pic.icw1=val; @@ -227,7 +222,7 @@ void pic2_write(uint16_t addr, uint8_t val, void *priv) { if (val&16) /*ICW1*/ { - pic2.mask=0; + pic2.mask = 0; pic2.mask2=0; pic2.icw=1; pic2.icw1=val; diff --git a/src/pic.h b/src/pic.h index 4652d8516..419315c5f 100644 --- a/src/pic.h +++ b/src/pic.h @@ -1,6 +1,3 @@ -/* Copyright holders: Sarah Walker, Tenshi - see COPYING for more details -*/ void pic_init(); void pic2_init(); void pic_reset(); diff --git a/src/pit.c b/src/pit.c index 34387843c..a74390676 100644 --- a/src/pit.c +++ b/src/pit.c @@ -1,6 +1,3 @@ -/* Copyright holders: Sarah Walker, Tenshi - see COPYING for more details -*/ /*IBM AT - Write B0 Write aa55 @@ -91,7 +88,7 @@ static void pit_set_out(int t, int out) static void pit_load(int t) { - int64_t l = pit.l[t] ? pit.l[t] : 0x10000; + int l = pit.l[t] ? pit.l[t] : 0x10000; timer_process(); pit.newcount[t] = 0; pit.disabled[t] = 0; @@ -100,7 +97,7 @@ static void pit_load(int t) { case 0: /*Interrupt on terminal count*/ pit.count[t] = l; - pit.c[t] = (int64_t)((l << TIMER_SHIFT) * PITCONST); + pit.c[t] = (int)((l << TIMER_SHIFT) * PITCONST); pit_set_out(t, 0); pit.thit[t] = 0; pit.enabled[t] = pit.gate[t]; @@ -112,7 +109,7 @@ static void pit_load(int t) if (pit.initial[t]) { pit.count[t] = l - 1; - pit.c[t] = (int64_t)(((l - 1) << TIMER_SHIFT) * PITCONST); + pit.c[t] = (int)(((l - 1) << TIMER_SHIFT) * PITCONST); pit_set_out(t, 1); pit.thit[t] = 0; } @@ -122,7 +119,7 @@ static void pit_load(int t) if (pit.initial[t]) { pit.count[t] = l; - pit.c[t] = (int64_t)((((l + 1) >> 1) << TIMER_SHIFT) * PITCONST); + pit.c[t] = (int)((((l + 1) >> 1) << TIMER_SHIFT) * PITCONST); pit_set_out(t, 1); pit.thit[t] = 0; } @@ -135,7 +132,7 @@ static void pit_load(int t) else { pit.count[t] = l; - pit.c[t] = (int64_t)((l << TIMER_SHIFT) * PITCONST); + pit.c[t] = (int)((l << TIMER_SHIFT) * PITCONST); pit_set_out(t, 0); pit.thit[t] = 0; } @@ -153,7 +150,7 @@ static void pit_load(int t) void pit_set_gate(int t, int gate) { - int64_t l = pit.l[t] ? pit.l[t] : 0x10000; + int l = pit.l[t] ? pit.l[t] : 0x10000; if (pit.disabled[t]) { @@ -173,7 +170,7 @@ void pit_set_gate(int t, int gate) if (gate && !pit.gate[t]) { pit.count[t] = l; - pit.c[t] = (int64_t)((l << TIMER_SHIFT) * PITCONST); + pit.c[t] = (int)((l << TIMER_SHIFT) * PITCONST); pit_set_out(t, 0); pit.thit[t] = 0; pit.enabled[t] = 1; @@ -183,7 +180,7 @@ void pit_set_gate(int t, int gate) if (gate && !pit.gate[t]) { pit.count[t] = l - 1; - pit.c[t] = (int64_t)(((l - 1) << TIMER_SHIFT) * PITCONST); + pit.c[t] = (int)(((l - 1) << TIMER_SHIFT) * PITCONST); pit_set_out(t, 1); pit.thit[t] = 0; } @@ -193,7 +190,7 @@ void pit_set_gate(int t, int gate) if (gate && !pit.gate[t]) { pit.count[t] = l; - pit.c[t] = (int64_t)((((l + 1) >> 1) << TIMER_SHIFT) * PITCONST); + pit.c[t] = (int)((((l + 1) >> 1) << TIMER_SHIFT) * PITCONST); pit_set_out(t, 1); pit.thit[t] = 0; } @@ -208,7 +205,7 @@ void pit_set_gate(int t, int gate) static void pit_over(int t) { - int64_t l = pit.l[t] ? pit.l[t] : 0x10000; + int l = pit.l[t] ? pit.l[t] : 0x10000; if (pit.disabled[t]) { pit.count[t] += 0xffff; @@ -225,7 +222,7 @@ static void pit_over(int t) pit_set_out(t, 1); pit.thit[t] = 1; pit.count[t] += 0xffff; - pit.c[t] += (int64_t)((0xffff << TIMER_SHIFT) * PITCONST); + pit.c[t] += (int)((0xffff << TIMER_SHIFT) * PITCONST); break; case 2: /*Rate generator*/ pit.count[t] += l; @@ -238,13 +235,13 @@ static void pit_over(int t) { pit_set_out(t, 0); pit.count[t] += (l >> 1); - pit.c[t] += (int64_t)(((l >> 1) << TIMER_SHIFT) * PITCONST); + pit.c[t] += (int)(((l >> 1) << TIMER_SHIFT) * PITCONST); } else { pit_set_out(t, 1); pit.count[t] += ((l + 1) >> 1); - pit.c[t] = (int64_t)((((l + 1) >> 1) << TIMER_SHIFT) * PITCONST); + pit.c[t] = (int)((((l + 1) >> 1) << TIMER_SHIFT) * PITCONST); } // if (!t) pclog("pit_over: square wave mode c=%x %lli %f\n", pit.c[t], tsc, PITCONST); break; @@ -258,13 +255,13 @@ static void pit_over(int t) { pit.newcount[t] = 0; pit.count[t] += l; - pit.c[t] += (int64_t)((l << TIMER_SHIFT) * PITCONST); + pit.c[t] += (int)((l << TIMER_SHIFT) * PITCONST); } else { pit.thit[t] = 1; pit.count[t] += 0xffff; - pit.c[t] += (int64_t)((0xffff << TIMER_SHIFT) * PITCONST); + pit.c[t] += (int)((0xffff << TIMER_SHIFT) * PITCONST); } break; case 5: /*Hardware triggered strove*/ @@ -275,7 +272,7 @@ static void pit_over(int t) } pit.thit[t] = 1; pit.count[t] += 0xffff; - pit.c[t] += (int64_t)((0xffff << TIMER_SHIFT) * PITCONST); + pit.c[t] += (int)((0xffff << TIMER_SHIFT) * PITCONST); break; } pit.running[t] = pit.enabled[t] && pit.using_timer[t] && !pit.disabled[t]; @@ -283,7 +280,7 @@ static void pit_over(int t) int pit_get_timer_0() { - int read = (int)((int64_t)((pit.c[0] + ((1 << TIMER_SHIFT) - 1)) / PITCONST) >> TIMER_SHIFT); + int read = (int)((pit.c[0] + ((1 << TIMER_SHIFT) - 1)) / PITCONST) >> TIMER_SHIFT; //pclog("pit_get_timer_0: t=%i using_timer=%i m=%i\n", 0, pit.using_timer[0], pit.m[0]); if (pit.m[0] == 2) read++; @@ -302,7 +299,7 @@ static int pit_read_timer(int t) // pclog("pit_read_timer: t=%i using_timer=%i m=%i\n", t, pit.using_timer[t], pit.m[t]); if (pit.using_timer[t]) { - int read = (int)((int64_t)((pit.c[t] + ((1 << TIMER_SHIFT) - 1)) / PITCONST) >> TIMER_SHIFT); + int read = (int)((pit.c[t] + ((1 << TIMER_SHIFT) - 1)) / PITCONST) >> TIMER_SHIFT; if (pit.m[t] == 2) read++; if (read < 0) @@ -332,11 +329,11 @@ void pit_write(uint16_t addr, uint8_t val, void *priv) if (!(val&0x20)) { if (val & 2) - pit.rl[0] = pit.using_timer[0] ? (int)(((int64_t) (pit.c[0] / PITCONST)) >> TIMER_SHIFT) : pit.count[0]; + pit.rl[0] = pit.using_timer[0] ? ((int)(pit.c[0] / PITCONST) >> TIMER_SHIFT) : pit.count[0]; if (val & 4) - pit.rl[1] = pit.using_timer[1] ? (int)(((int64_t) (pit.c[1] / PITCONST)) >> TIMER_SHIFT) : pit.count[1]; + pit.rl[1] = pit.using_timer[1] ? ((int)(pit.c[1] / PITCONST) >> TIMER_SHIFT) : pit.count[1]; if (val & 8) - pit.rl[2] = pit.using_timer[2] ? (int)(((int64_t) (pit.c[2] / PITCONST)) >> TIMER_SHIFT) : pit.count[2]; + pit.rl[2] = pit.using_timer[2] ? ((int)(pit.c[2] / PITCONST) >> TIMER_SHIFT) : pit.count[2]; } if (!(val & 0x10)) { @@ -412,7 +409,7 @@ void pit_write(uint16_t addr, uint8_t val, void *priv) pit.l[t]=val; // pit.thit[t]=0; pit_load(t); -// pit.c[t]=((int64_t)pit.l[t])*PITCONST; +// pit.c[t]=pit.l[t]*PITCONST; // if (!t) // picintc(1); break; @@ -551,7 +548,7 @@ void pit_set_using_timer(int t, int using_timer) if (pit.using_timer[t] && !using_timer) pit.count[t] = pit_read_timer(t); if (!pit.using_timer[t] && using_timer) - pit.c[t] = (int64_t)((((int64_t) pit.count[t]) << TIMER_SHIFT) * PITCONST); + pit.c[t] = (int)((pit.count[t] << TIMER_SHIFT) * PITCONST); pit.using_timer[t] = using_timer; pit.running[t] = pit.enabled[t] && pit.using_timer[t] && !pit.disabled[t]; timer_update_outstanding(); diff --git a/src/pit.h b/src/pit.h index a0102e1af..3d5018bd1 100644 --- a/src/pit.h +++ b/src/pit.h @@ -1,8 +1,4 @@ -/* Copyright holders: Sarah Walker, Tenshi - see COPYING for more details -*/ extern double PITCONST; -extern float cpuclock; void pit_init(); void pit_reset(); void pit_set_gate(int channel, int gate); diff --git a/src/timer.c b/src/timer.c index 92686e906..45268869e 100644 --- a/src/timer.c +++ b/src/timer.c @@ -1,6 +1,3 @@ -/* Copyright holders: Sarah Walker, Tenshi - see COPYING for more details -*/ #include "ibm.h" /*#include "sound_opl.h" @@ -20,15 +17,15 @@ static struct int present; void (*callback)(void *priv); void *priv; - int64_t *enable; - int64_t *count; + int *enable; + int *count; } timers[TIMERS_MAX]; int timers_present = 0; -int64_t timer_one = 1; +int timer_one = 1; -int64_t timer_count = 0, timer_latch = 0; -int64_t timer_start = 0; +int timer_count = 0, timer_latch = 0; +int timer_start = 0; void timer_process() { @@ -36,7 +33,7 @@ void timer_process() int retry; int process = 0; /*Get actual elapsed time*/ - int64_t diff = timer_latch - timer_count; + int diff = timer_latch - timer_count; int enable[TIMERS_MAX]; timer_latch = 0; @@ -82,7 +79,7 @@ void timer_process() void timer_update_outstanding() { int c; - timer_latch = 0x7fffffffffffffff; + timer_latch = 0x7fffffff; for (c = 0; c < timers_present; c++) { if (*timers[c].enable && *timers[c].count < timer_latch) @@ -99,7 +96,7 @@ void timer_reset() // timer_process(); } -int timer_add(void (*callback)(void *priv), int64_t *count, int64_t *enable, void *priv) +int timer_add(void (*callback)(void *priv), int *count, int *enable, void *priv) { if (timers_present < TIMERS_MAX) { diff --git a/src/timer.h b/src/timer.h index eb19633ce..50c83e55c 100644 --- a/src/timer.h +++ b/src/timer.h @@ -1,12 +1,9 @@ -/* Copyright holders: Sarah Walker, Tenshi - see COPYING for more details -*/ #ifndef _TIMER_H_ #define _TIMER_H_ #include "cpu.h" -extern int64_t timer_start; +extern int timer_start; #define timer_start_period(cycles) \ timer_start = cycles; @@ -14,7 +11,7 @@ extern int64_t timer_start; #define timer_end_period(cycles) \ do \ { \ - int64_t diff = timer_start - ((uint64_t) cycles); \ + int diff = timer_start - (cycles); \ timer_count -= diff; \ timer_start = cycles; \ if (timer_count <= 0) \ @@ -27,16 +24,16 @@ extern int64_t timer_start; #define timer_clock() \ do \ { \ - int64_t diff; \ + int diff; \ if (AT) \ { \ - diff = timer_start - (((uint64_t) cycles) << TIMER_SHIFT); \ - timer_start = ((uint64_t) cycles) << TIMER_SHIFT; \ + diff = timer_start - (cycles << TIMER_SHIFT); \ + timer_start = cycles << TIMER_SHIFT; \ } \ else \ { \ - diff = timer_start - (((uint64_t) cycles) * xt_cpu_multi); \ - timer_start = ((uint64_t) cycles) * xt_cpu_multi; \ + diff = timer_start - (cycles * xt_cpu_multi); \ + timer_start = cycles * xt_cpu_multi; \ } \ timer_count -= diff; \ timer_process(); \ @@ -46,13 +43,13 @@ extern int64_t timer_start; void timer_process(); void timer_update_outstanding(); void timer_reset(); -int timer_add(void (*callback)(void *priv), int64_t *count, int64_t *enable, void *priv); +int timer_add(void (*callback)(void *priv), int *count, int *enable, void *priv); void timer_set_callback(int timer, void (*callback)(void *priv)); #define TIMER_ALWAYS_ENABLED &timer_one -extern int64_t timer_count; -extern int64_t timer_one; +extern int timer_count; +extern int timer_one; #define TIMER_SHIFT 6 diff --git a/src/vid_et4000w32.c b/src/vid_et4000w32.c index df8555e99..f44fc5fe0 100644 --- a/src/vid_et4000w32.c +++ b/src/vid_et4000w32.c @@ -1,6 +1,3 @@ -/* Copyright holders: Sarah Walker, Tenshi - see COPYING for more details -*/ /*ET4000/W32p emulation (Diamond Stealth 32)*/ /*Known bugs : @@ -17,7 +14,6 @@ #include "video.h" #include "vid_svga.h" #include "vid_icd2061.h" -#include "vid_sdac_ramdac.h" #include "vid_stg_ramdac.h" #define FIFO_SIZE 65536 @@ -53,7 +49,6 @@ typedef struct et4000w32p_t svga_t svga; stg_ramdac_t ramdac; - sdac_ramdac_t sdac_ramdac; icd2061_t icd2061; int index; @@ -64,10 +59,7 @@ typedef struct et4000w32p_t uint8_t pci_regs[256]; - int vram_size; int interleaved; - int max_ram_mask; - int revision; /*Accelerator*/ struct @@ -100,7 +92,6 @@ typedef struct et4000w32p_t { uint32_t base[3]; uint8_t ctrl; - uint8_t unk[2]; } mmu; fifo_entry_t fifo[FIFO_SIZE]; @@ -143,24 +134,16 @@ void et4000w32p_out(uint16_t addr, uint8_t val, void *p) switch (addr) { case 0x3c2: - if (gfxcard == GFX_ET4000W32) - icd2061_write(&et4000->icd2061, (val >> 2) & 3); + icd2061_write(&et4000->icd2061, (val >> 2) & 3); break; case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9: - if (gfxcard == GFX_ET4000W32CS) - { - sdac_ramdac_out(addr, val, &et4000->sdac_ramdac, svga); - } - else - { - stg_ramdac_out(addr, val, &et4000->ramdac, svga); - } + stg_ramdac_out(addr, val, &et4000->ramdac, svga); return; case 0x3CB: /*Banking extension*/ - svga->write_bank = (svga->write_bank & 0xfffff) | ((val & 3) << 20); - svga->read_bank = (svga->read_bank & 0xfffff) | ((val & 0x30) << 16); + svga->write_bank = (svga->write_bank & 0xfffff) | ((val & 1) << 20); + svga->read_bank = (svga->read_bank & 0xfffff) | ((val & 0x10) << 16); et4000->banking2 = val; return; case 0x3CD: /*Banking*/ @@ -183,8 +166,6 @@ void et4000w32p_out(uint16_t addr, uint8_t val, void *p) return; case 0x3D5: // pclog("Write CRTC R%02X %02X\n", crtcreg, val); - if (svga->crtcreg <= 0x18) - val &= mask_crtc[svga->crtcreg]; if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80)) return; if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80)) @@ -201,7 +182,16 @@ void et4000w32p_out(uint16_t addr, uint8_t val, void *p) } if (svga->crtcreg == 0x30) { - et4000->linearbase = val * 0x400000; + if (PCI) + { + et4000->linearbase &= 0xc0000000; + et4000->linearbase = (val & 0xfc) << 22; + } + else + { + et4000->linearbase = val << 22; + } + // et4000->linearbase = val * 0x400000; // pclog("Linear base now at %08X %02X\n", et4000w32p_linearbase, val); et4000w32p_recalcmapping(et4000); } @@ -255,14 +245,7 @@ uint8_t et4000w32p_in(uint16_t addr, void *p) break; case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9: - if (gfxcard == GFX_ET4000W32CS) - { - return sdac_ramdac_in(addr, &et4000->sdac_ramdac, svga); - } - else - { - return stg_ramdac_in(addr, &et4000->ramdac, svga); - } + return stg_ramdac_in(addr, &et4000->ramdac, svga); case 0x3CB: return et4000->banking2; @@ -288,10 +271,8 @@ uint8_t et4000w32p_in(uint16_t addr, void *p) return et4000->index; case 0x210B: case 0x211B: case 0x212B: case 0x213B: case 0x214B: case 0x215B: case 0x216B: case 0x217B: - // if (et4000->index==0xec) - // return (et4000->regs[0xec] & 0xf) | 0x60; /*ET4000/W32p rev D*/ if (et4000->index==0xec) - return (et4000->regs[0xec] & 0xf) | (et4000->revision << 4); /*ET4000/W32p rev D*/ + return (et4000->regs[0xec] & 0xf) | 0x60; /*ET4000/W32p rev D*/ if (et4000->index == 0xef) { if (PCI) return et4000->regs[0xef] | 0xe0; /*PCI*/ @@ -317,37 +298,11 @@ void et4000w32p_recalctimings(svga_t *svga) if (svga->crtc[0x3F] & 0x01) svga->htotal += 256; if (svga->attrregs[0x16] & 0x20) svga->hdisp <<= 1; - if (gfxcard == GFX_ET4000W32) - { - switch ((svga->miscout >> 2) & 3) - { - case 0: case 1: break; - case 2: case 3: svga->clock = cpuclock / icd2061_getfreq(&et4000->icd2061, 2); break; - } - } - else if (gfxcard == GFX_ET4000W32C) - { - svga->clock = cpuclock / stg_getclock((svga->miscout >> 2) & 3, &et4000->ramdac); - } - else - { - svga->clock = cpuclock / sdac_getclock((svga->miscout >> 2) & 3, &et4000->sdac_ramdac); - switch (sdac_get_clock_divider(&et4000->sdac_ramdac)) - { - case 1: - svga->clock *= 2.0; - break; - case 3: - svga->clock /= 1.5; - break; - case 4: - svga->clock /= 2.0; - break; - case 6: - svga->clock /= 3.0; - break; - } - } + switch ((svga->miscout >> 2) & 3) + { + case 0: case 1: break; + case 2: case 3: svga->clock = cpuclock / icd2061_getfreq(&et4000->icd2061, 2); break; + } switch (svga->bpp) { @@ -637,8 +592,6 @@ void et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *p) case 0x7f0a: et4000->mmu.base[2] = (et4000->mmu.base[2] & 0xFF00FFFF) | (val << 16); break; case 0x7f0d: et4000->mmu.base[2] = (et4000->mmu.base[2] & 0x00FFFFFF) | (val << 24); break; case 0x7f13: et4000->mmu.ctrl=val; break; - case 0x7f30: et4000->mmu.unk[0] = val; break; - case 0x7f32: et4000->mmu.unk[1] = val; break; } break; } @@ -694,8 +647,6 @@ uint8_t et4000w32p_mmu_read(uint32_t addr, void *p) case 0x7f0a: return et4000->mmu.base[2] >> 16; case 0x7f0b: return et4000->mmu.base[2] >> 24; case 0x7f13: return et4000->mmu.ctrl; - case 0x7f30: return et4000->mmu.unk[0]; - case 0x7f32: return et4000->mmu.unk[1]; case 0x7f36: temp = et4000->acl.status; @@ -880,21 +831,21 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400 while (count--) { if (bltout) pclog("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y); - pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->max_ram_mask]; - source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & et4000->max_ram_mask]; - if (bltout) pclog("%06X %06X ", (et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->max_ram_mask, (et4000->acl.source_addr + et4000->acl.source_x) & et4000->max_ram_mask); + pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff]; + source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff]; + if (bltout) pclog("%06X %06X ", (et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff, (et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff); if (cpu_input == 2) { source = sdat & 0xff; sdat >>= 8; } - dest = svga->vram[et4000->acl.dest_addr & et4000->max_ram_mask]; + dest = svga->vram[et4000->acl.dest_addr & 0x1fffff]; out = 0; if (bltout) pclog("%06X ", et4000->acl.dest_addr); if ((et4000->acl.internal.ctrl_routing & 0xa) == 8) { - mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & et4000->max_ram_mask] & (1 << (et4000->acl.mix_addr & 7)); - if (bltout) pclog("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & et4000->max_ram_mask]); + mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff] & (1 << (et4000->acl.mix_addr & 7)); + if (bltout) pclog("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff]); } else { @@ -911,11 +862,11 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400 if (pattern & (1 << c)) d |= 4; if (rop & (1 << d)) out |= (1 << c); } - if (bltout) pclog("%06X = %02X\n", et4000->acl.dest_addr & et4000->max_ram_mask, out); + if (bltout) pclog("%06X = %02X\n", et4000->acl.dest_addr & 0x1fffff, out); if (!(et4000->acl.internal.ctrl_routing & 0x40)) { - svga->vram[et4000->acl.dest_addr & et4000->max_ram_mask] = out; - svga->changedvram[(et4000->acl.dest_addr & et4000->max_ram_mask) >> 12] = changeframecount; + svga->vram[et4000->acl.dest_addr & 0x1fffff] = out; + svga->changedvram[(et4000->acl.dest_addr & 0x1fffff) >> 12] = changeframecount; } else { @@ -1000,22 +951,22 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400 { if (bltout) pclog("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y); - pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->max_ram_mask]; - source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & et4000->max_ram_mask]; - if (bltout) pclog("%i %06X %06X %02X %02X ", et4000->acl.pattern_y, (et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->max_ram_mask, (et4000->acl.source_addr + et4000->acl.source_x) & et4000->max_ram_mask, pattern, source); + pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff]; + source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff]; + if (bltout) pclog("%i %06X %06X %02X %02X ", et4000->acl.pattern_y, (et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff, (et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff, pattern, source); if (cpu_input == 2) { source = sdat & 0xff; sdat >>= 8; } - dest = svga->vram[et4000->acl.dest_addr & et4000->max_ram_mask]; + dest = svga->vram[et4000->acl.dest_addr & 0x1fffff]; out = 0; if (bltout) pclog("%06X %02X %i %08X %08X ", dest, et4000->acl.dest_addr, mix & 1, mix, et4000->acl.mix_addr); if ((et4000->acl.internal.ctrl_routing & 0xa) == 8) { - mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & et4000->max_ram_mask] & (1 << (et4000->acl.mix_addr & 7)); - if (bltout) pclog("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & et4000->max_ram_mask]); + mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff] & (1 << (et4000->acl.mix_addr & 7)); + if (bltout) pclog("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff]); } else { @@ -1032,11 +983,11 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400 if (pattern & (1 << c)) d |= 4; if (rop & (1 << d)) out |= (1 << c); } - if (bltout) pclog("%06X = %02X\n", et4000->acl.dest_addr & et4000->max_ram_mask, out); + if (bltout) pclog("%06X = %02X\n", et4000->acl.dest_addr & 0x1fffff, out); if (!(et4000->acl.internal.ctrl_routing & 0x40)) { - svga->vram[et4000->acl.dest_addr & et4000->max_ram_mask] = out; - svga->changedvram[(et4000->acl.dest_addr & et4000->max_ram_mask) >> 12] = changeframecount; + svga->vram[et4000->acl.dest_addr & 0x1fffff] = out; + svga->changedvram[(et4000->acl.dest_addr & 0x1fffff) >> 12] = changeframecount; } else { @@ -1091,23 +1042,21 @@ void et4000w32p_hwcursor_draw(svga_t *svga, int displine) { int x, offset; uint8_t dat; - int y_add = enable_overscan ? 16 : 0; - int x_add = enable_overscan ? 8 : 0; offset = svga->hwcursor_latch.xoff; for (x = 0; x < 64 - svga->hwcursor_latch.xoff; x += 4) { dat = svga->vram[svga->hwcursor_latch.addr + (offset >> 2)]; - if (!(dat & 2)) ((uint32_t *)buffer32->line[displine + y_add])[svga->hwcursor_latch.x + x + 32 + x_add] = (dat & 1) ? 0xFFFFFF : 0; - else if ((dat & 3) == 3) ((uint32_t *)buffer32->line[displine + y_add])[svga->hwcursor_latch.x + x + 32 + x_add] ^= 0xFFFFFF; + if (!(dat & 2)) ((uint32_t *)buffer32->line[displine])[svga->hwcursor_latch.x + x + 32] = (dat & 1) ? 0xFFFFFF : 0; + else if ((dat & 3) == 3) ((uint32_t *)buffer32->line[displine])[svga->hwcursor_latch.x + x + 32] ^= 0xFFFFFF; dat >>= 2; - if (!(dat & 2)) ((uint32_t *)buffer32->line[displine + y_add])[svga->hwcursor_latch.x + x + 33 + x_add] = (dat & 1) ? 0xFFFFFF : 0; - else if ((dat & 3) == 3) ((uint32_t *)buffer32->line[displine + y_add])[svga->hwcursor_latch.x + x + 33 + x_add] ^= 0xFFFFFF; + if (!(dat & 2)) ((uint32_t *)buffer32->line[displine])[svga->hwcursor_latch.x + x + 33] = (dat & 1) ? 0xFFFFFF : 0; + else if ((dat & 3) == 3) ((uint32_t *)buffer32->line[displine])[svga->hwcursor_latch.x + x + 33] ^= 0xFFFFFF; dat >>= 2; - if (!(dat & 2)) ((uint32_t *)buffer32->line[displine + y_add])[svga->hwcursor_latch.x + x + 34 + x_add] = (dat & 1) ? 0xFFFFFF : 0; - else if ((dat & 3) == 3) ((uint32_t *)buffer32->line[displine + y_add])[svga->hwcursor_latch.x + x + 34 + x_add] ^= 0xFFFFFF; + if (!(dat & 2)) ((uint32_t *)buffer32->line[displine])[svga->hwcursor_latch.x + x + 34] = (dat & 1) ? 0xFFFFFF : 0; + else if ((dat & 3) == 3) ((uint32_t *)buffer32->line[displine])[svga->hwcursor_latch.x + x + 34] ^= 0xFFFFFF; dat >>= 2; - if (!(dat & 2)) ((uint32_t *)buffer32->line[displine + y_add])[svga->hwcursor_latch.x + x + 35 + x_add] = (dat & 1) ? 0xFFFFFF : 0; - else if ((dat & 3) == 3) ((uint32_t *)buffer32->line[displine + y_add])[svga->hwcursor_latch.x + x + 35 + x_add] ^= 0xFFFFFF; + if (!(dat & 2)) ((uint32_t *)buffer32->line[displine])[svga->hwcursor_latch.x + x + 35] = (dat & 1) ? 0xFFFFFF : 0; + else if ((dat & 3) == 3) ((uint32_t *)buffer32->line[displine])[svga->hwcursor_latch.x + x + 35] ^= 0xFFFFFF; dat >>= 2; offset += 4; } @@ -1149,37 +1098,37 @@ uint8_t et4000w32p_pci_read(int func, int addr, void *p) et4000w32p_t *et4000 = (et4000w32p_t *)p; svga_t *svga = &et4000->svga; -// pclog("ET4000 PCI read %08X\n", addr); + pclog("ET4000 PCI read %08X\n", addr); switch (addr) { case 0x00: return 0x0c; /*Tseng Labs*/ case 0x01: return 0x10; - // case 0x02: return 0x06; /*ET4000W32p Rev D*/ - case 0x02: return et4000->revision; + case 0x02: return 0x06; /*ET4000W32p Rev D*/ case 0x03: return 0x32; case PCI_REG_COMMAND: - return et4000->pci_regs[PCI_REG_COMMAND]; /*Respond to IO and memory accesses*/ + return et4000->pci_regs[PCI_REG_COMMAND] | 0x80; /*Respond to IO and memory accesses*/ case 0x07: return 1 << 1; /*Medium DEVSEL timing*/ case 0x08: return 0; /*Revision ID*/ case 0x09: return 0; /*Programming interface*/ - case 0x0a: return 0x01; /*Supports VGA interface, XGA compatible*/ + case 0x0a: return 0x00; /*Supports VGA interface, XGA compatible*/ case 0x0b: return 0x03; case 0x10: return 0x00; /*Linear frame buffer address*/ case 0x11: return 0x00; - case 0x12: return svga->crtc[0x5a] & 0x80; - case 0x13: return svga->crtc[0x59]; + case 0x12: return (et4000->linearbase >> 16) & 0xff; + case 0x13: return (et4000->linearbase >> 24); case 0x30: return et4000->pci_regs[0x30] & 0x01; /*BIOS ROM address*/ case 0x31: return 0x00; - case 0x32: return et4000->pci_regs[0x32]; - case 0x33: return et4000->pci_regs[0x33]; + case 0x32: return 0x00; + case 0x33: return (et4000->pci_regs[0x33]) & 0xf0; + } return 0; } @@ -1187,11 +1136,15 @@ uint8_t et4000w32p_pci_read(int func, int addr, void *p) void et4000w32p_pci_write(int func, int addr, uint8_t val, void *p) { et4000w32p_t *et4000 = (et4000w32p_t *)p; + svga_t *svga = &et4000->svga; + uint32_t temp = 0; + + pclog("ET4000 PCI Write: value %02X to address %08X\n"); switch (addr) { case PCI_REG_COMMAND: - et4000->pci_regs[PCI_REG_COMMAND] = val & 0x27; + et4000->pci_regs[PCI_REG_COMMAND] = (val & 0x23) | 0x80; if (val & PCI_COMMAND_IO) et4000w32p_io_set(et4000); else @@ -1200,88 +1153,55 @@ void et4000w32p_pci_write(int func, int addr, uint8_t val, void *p) break; case 0x13: - et4000->linearbase = val << 24; + et4000->linearbase &= 0xffff0000; + et4000->linearbase = (et4000->pci_regs[0x12] << 16) | (et4000->pci_regs[0x13] << 24); + svga->crtc[0x30] = ((et4000->linearbase & 0x3fc00000) >> 22); et4000w32p_recalcmapping(et4000); break; - case 0x30: case 0x32: case 0x33: + case 0x30: case 0x31: case 0x32: case 0x33: et4000->pci_regs[addr] = val; + et4000->pci_regs[0x30] = 1; + et4000->pci_regs[0x31] = 0; + et4000->pci_regs[0x32] = 0; + et4000->pci_regs[0x33] &= 0xf0; if (et4000->pci_regs[0x30] & 0x01) { - uint32_t addr = (et4000->pci_regs[0x32] << 16) | (et4000->pci_regs[0x33] << 24); - // pclog("ET4000 bios_rom enabled at %08x\n", addr); + // uint32_t addr = ((et4000->pci_regs[0x31] & 0x80) << 8) | ((et4000->pci_regs[0x32] & 0x0f) << 16) | (et4000->pci_regs[0x33] << 24); + uint32_t addr = (et4000->pci_regs[0x33] << 24); + if (!addr) + { + addr = 0xC0000; + } + pclog("ET4000 bios_rom enabled at %08x\n", addr); mem_mapping_set_addr(&et4000->bios_rom.mapping, addr, 0x8000); } else { - // pclog("ET4000 bios_rom disabled\n"); + pclog("ET4000 bios_rom disabled\n"); mem_mapping_disable(&et4000->bios_rom.mapping); } return; } } -void *et4000w32p_common_init(char *biosfile) +void *et4000w32p_init() { int vram_size; - int bios_offset = 0; - int checksum_diff = 0; et4000w32p_t *et4000 = malloc(sizeof(et4000w32p_t)); memset(et4000, 0, sizeof(et4000w32p_t)); vram_size = device_get_config_int("memory"); - et4000->vram_size = vram_size; - - et4000->revision = device_get_config_int("revision"); et4000->interleaved = (vram_size == 2) ? 1 : 0; - // et4000->max_ram_mask = (gfxcard == GFX_ET4000W32) ? 0x1fffff : 0x3fffff; - et4000->max_ram_mask = (vram_size << 20) - 1; - // et4000->max_ram_mask = 0x1fffff; - svga_init(&et4000->svga, et4000, vram_size << 20, et4000w32p_recalctimings, et4000w32p_in, et4000w32p_out, et4000w32p_hwcursor_draw, NULL); - rom_init(&et4000->bios_rom, biosfile, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); - if (vram_size == 4) - { - /* The ROM is hardcoded to 256k sticks, so let's patch it for 1M. */ - if (memcmp(&((&et4000->bios_rom)->rom[0x008f]), "06/28/94 V1.0CN", 15) == 0) - { - bios_offset = 0x026d; - } - else if (memcmp(&((&et4000->bios_rom)->rom[0x008f]), "04/28/95 V2.10N", 15) == 0) - { - bios_offset = 0x0244; - } - else if (memcmp(&((&et4000->bios_rom)->rom[0x008f]), "05/15/95 V8.00N", 15) == 0) - { - bios_offset = 0x027f; - } - else if (memcmp(&((&et4000->bios_rom)->rom[0x008f]), "05/17/95 V8.00N", 15) == 0) - { - bios_offset = 0x041d; - } - if (bios_offset) - { - checksum_diff = (&et4000->bios_rom)->rom[bios_offset] - 0x03; - if (checksum_diff) - { - (&et4000->bios_rom)->rom[bios_offset] = 0x03; - (&et4000->bios_rom)->rom[0x7fff] += checksum_diff; - pclog("BIOS patched: %08X: %02X 03\n", bios_offset, checksum_diff + 0x03); - } - } - else - { - pclog("No known BIOS detected or BIOS already set to 1 MB DRAM modules, maximum VRAM is 2 MB\n"); - vram_size == 2; - } - } + rom_init(&et4000->bios_rom, "roms/et4000w32.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); if (PCI) mem_mapping_disable(&et4000->bios_rom.mapping); @@ -1292,11 +1212,20 @@ void *et4000w32p_common_init(char *biosfile) pci_add(et4000w32p_pci_read, et4000w32p_pci_write, et4000); - et4000->pci_regs[0x04] = 7; + /* Hardwired bits: 00000000 1xx0x0xx */ + /* R/W bits: xx xxxx */ + /* PCem bits: 111 */ + et4000->pci_regs[0x04] = 0x83; + + et4000->pci_regs[0x10] = 0x00; + et4000->pci_regs[0x11] = 0x00; + et4000->pci_regs[0x12] = 0xff; + et4000->pci_regs[0x13] = 0xff; et4000->pci_regs[0x30] = 0x00; - et4000->pci_regs[0x32] = 0x0c; - et4000->pci_regs[0x33] = 0x00; + et4000->pci_regs[0x31] = 0x00; + et4000->pci_regs[0x32] = 0x00; + et4000->pci_regs[0x33] = 0xf0; et4000->wake_fifo_thread = thread_create_event(); et4000->fifo_not_full_event = thread_create_event(); @@ -1305,36 +1234,11 @@ void *et4000w32p_common_init(char *biosfile) return et4000; } -void *et4000w32p_init() -{ - return et4000w32p_common_init("roms/et4000w32.bin"); -} - -void *et4000w32pc_init() -{ - return et4000w32p_common_init("roms/cardex.vbi"); -} - -void *et4000w32pcs_init() -{ - return et4000w32p_common_init("roms/TSENG.BIN"); -} - int et4000w32p_available() { return rom_present("roms/et4000w32.bin"); } -int et4000w32pc_available() -{ - return rom_present("roms/cardex.vbi"); -} - -int et4000w32pcs_available() -{ - return rom_present("roms/TSENG.BIN"); -} - void et4000w32p_close(void *p) { et4000w32p_t *et4000 = (et4000w32p_t *)p; @@ -1396,93 +1300,6 @@ static device_config_t et4000w32p_config[] = }, .default_int = 2 }, - { - .name = "revision", - .description = "Revision", - .type = CONFIG_SELECTION, - .selection = - { - { - .description = "Rev. A", - .value = 2 - }, - { - .description = "Rev. B", - .value = 5 - }, - { - .description = "Rev. D", - .value = 6 - }, - { - .description = "Rev. C", - .value = 7 - }, - { - .description = "" - } - }, - .default_int = 6 - }, - { - .type = -1 - } -}; - -static device_config_t et4000w32pc_config[] = -{ - { - .name = "memory", - .description = "Memory size", - .type = CONFIG_SELECTION, - .selection = - { - { - .description = "1 MB", - .value = 1 - }, - { - .description = "2 MB", - .value = 2 - }, - { - .description = "4 MB", - .value = 4 - }, - { - .description = "" - } - }, - .default_int = 2 - }, - { - .name = "revision", - .description = "Revision", - .type = CONFIG_SELECTION, - .selection = - { - { - .description = "Rev. A", - .value = 2 - }, - { - .description = "Rev. B", - .value = 5 - }, - { - .description = "Rev. D", - .value = 6 - }, - { - .description = "Rev. C", - .value = 7 - }, - { - .description = "" - } - }, - .default_int = 6 - }, { .type = -1 } @@ -1500,29 +1317,3 @@ device_t et4000w32p_device = et4000w32p_add_status_info, et4000w32p_config }; - -device_t et4000w32pc_device = -{ - "Cardex 1703-DDC (ET4000/W32P)", - 0, - et4000w32pc_init, - et4000w32p_close, - et4000w32pc_available, - et4000w32p_speed_changed, - et4000w32p_force_redraw, - et4000w32p_add_status_info, - et4000w32pc_config -}; - -device_t et4000w32pcs_device = -{ - "Cardex ICS5341 (ET4000/W32P)", - 0, - et4000w32pcs_init, - et4000w32p_close, - et4000w32pcs_available, - et4000w32p_speed_changed, - et4000w32p_force_redraw, - et4000w32p_add_status_info, - et4000w32pc_config -}; diff --git a/src/vid_et4000w32.h b/src/vid_et4000w32.h index fa27ae837..32a344259 100644 --- a/src/vid_et4000w32.h +++ b/src/vid_et4000w32.h @@ -1,6 +1 @@ -/* Copyright holders: Sarah Walker, Tenshi - see COPYING for more details -*/ extern device_t et4000w32p_device; -extern device_t et4000w32pc_device; -extern device_t et4000w32pcs_device; diff --git a/src/vid_svga.c b/src/vid_svga.c index 592fb83a1..0212dde34 100644 --- a/src/vid_svga.c +++ b/src/vid_svga.c @@ -927,9 +927,9 @@ int svga_init(svga_t *svga, void *p, int memsize, svga_pointer = svga; - io_sethandler(0x22ca, 0x0002, svga_in, NULL, NULL, svga_out, NULL, NULL, svga); + /* io_sethandler(0x22ca, 0x0002, svga_in, NULL, NULL, svga_out, NULL, NULL, svga); io_sethandler(0x22ce, 0x0002, svga_in, NULL, NULL, svga_out, NULL, NULL, svga); - io_sethandler(0x32ca, 0x0002, svga_in, NULL, NULL, svga_out, NULL, NULL, svga); + io_sethandler(0x32ca, 0x0002, svga_in, NULL, NULL, svga_out, NULL, NULL, svga); */ return 0; } diff --git a/src/video.c b/src/video.c index 3adf96d23..02d8f0bdc 100644 --- a/src/video.c +++ b/src/video.c @@ -61,8 +61,6 @@ static VIDEO_CARD video_cards[] = {"ATI VGA Charger (ATI-28800-5)", &ati28800_device, GFX_VGACHARGER}, {"ATI VGA Wonder XL24 (ATI-28800-6)", &ati28800_wonderxl24_device, GFX_VGAWONDERXL24}, {"ATI VGA Edge-16 (ATI-18800)", &ati18800_device, GFX_VGAEDGE16}, - {"Cardex 1703-DDC (ET4000/W32P)", &et4000w32pc_device, GFX_ET4000W32C}, - {"Cardex ICS5341 (ET4000/W32P)", &et4000w32pcs_device, GFX_ET4000W32CS}, {"CGA", &cga_device, GFX_CGA}, {"Cirrus Logic CL-GD5429", &gd5429_device, GFX_CL_GD5429}, {"Diamond Stealth 32 (Tseng ET4000/w32p)", &et4000w32p_device, GFX_ET4000W32},