diff --git a/src/chipset/ali1429.c b/src/chipset/ali1429.c index 5e19983c7..f52c5ef50 100644 --- a/src/chipset/ali1429.c +++ b/src/chipset/ali1429.c @@ -6,103 +6,144 @@ * * This file is part of the 86Box distribution. * - * Implementation of the ALi M-1429/1431 chipset. + * Implementation of the ALi M1429 chipset. * + * Note: This chipset has no datasheet, everything were done via + * reverse engineering the BIOS of various machines using it. * + * Authors: Tiseno100 * - * Authors: Sarah Walker, - * Miran Grca, + * Copyright 2020 Tiseno100 * - * Copyright 2008-2019 Sarah Walker. - * Copyright 2016-2019 Miran Grca. */ -#include + +#include #include +#include #include #include #include +#define HAVE_STDARG_H #include <86box/86box.h> #include "cpu.h" #include <86box/timer.h> #include <86box/io.h> -#include <86box/mem.h> #include <86box/device.h> #include <86box/keyboard.h> +#include <86box/mem.h> #include <86box/fdd.h> #include <86box/fdc.h> -#include <86box/hdc.h> -#include <86box/hdc_ide.h> -#include <86box/timer.h> #include <86box/port_92.h> #include <86box/chipset.h> +#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY) + +#ifdef ENABLE_ALI1429_LOG +int ali1429_do_log = ENABLE_ALI1429_LOG; +static void +ali1429_log(const char *fmt, ...) +{ + va_list ap; + + if (ali1429_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } +} +#else +#define ali1429_log(fmt, ...) +#endif + typedef struct { - uint8_t cur_reg, - regs[256]; + uint8_t index, cfg_locked, + regs[256]; } ali1429_t; - -static void -ali1429_recalc(ali1429_t *dev) +static void ali1429_shadow_recalc(ali1429_t *dev) { - uint32_t base; - uint32_t i, shflags = 0; - shadowbios = 0; - shadowbios_write = 0; +uint32_t base, i, can_write, can_read; - for (i = 0; i < 8; i++) { - base = 0xc0000 + (i << 15); +shadowbios = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x01); +shadowbios_write = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x02); - if (dev->regs[0x13] & (1 << i)) { - shadowbios |= (base >= 0xe8000) && !!(dev->regs[0x14] & 0x01); - shadowbios_write |= (base >= 0xe8000) && !!(dev->regs[0x14] & 0x02); - shflags = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= !(dev->regs[0x14] & 0x02) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL; - mem_set_mem_state(base, 0x8000, shflags); - } else - mem_set_mem_state(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - } +can_write = (dev->regs[0x14] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; +can_read = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + +for(i = 0; i < 8; i++) +{ +base = 0xc0000 + (i << 15); + +if(dev->regs[0x13] & (1 << i)) +mem_set_mem_state_both(base, 0x8000, can_read | can_write); +else +mem_set_mem_state_both(base, 0x8000, disabled_shadow); - flushmmucache(); } +flushmmucache(); +} static void -ali1429_write(uint16_t port, uint8_t val, void *priv) +ali1429_write(uint16_t addr, uint8_t val, void *priv) { ali1429_t *dev = (ali1429_t *) priv; - if (port & 1) { - dev->regs[dev->cur_reg] = val; + switch (addr) { + case 0x22: + dev->index = val; + break; + + case 0x23: - switch (dev->cur_reg) { - case 0x13: - ali1429_recalc(dev); - break; - case 0x14: - ali1429_recalc(dev); - break; - } - } else - dev->cur_reg = val; + /* Don't log register unlock patterns */ + if(dev->index != 0x03) + { + ali1429_log("M1429: dev->regs[%02x] = %02x\n", dev->index, val); + } + + dev->regs[dev->index] = val; + + /* Unlock/Lock Registers */ + dev->cfg_locked = !(dev->regs[0x03] && 0xc5); + + if(dev->cfg_locked == 0) + { + switch(dev->index){ + /* Shadow RAM */ + case 0x13: + case 0x14: + ali1429_shadow_recalc(dev); + break; + + /* Cache */ + case 0x18: + cpu_cache_ext_enabled = (val & 0x80); + break; + } + } + + break; + } } static uint8_t -ali1429_read(uint16_t port, void *priv) +ali1429_read(uint16_t addr, void *priv) { uint8_t ret = 0xff; ali1429_t *dev = (ali1429_t *) priv; - if (!(port & 1)) - ret = dev->cur_reg; - else if (((dev->cur_reg >= 0xc0) || (dev->cur_reg == 0x20)) && cpu_iscyrix) - ret = 0xff; /*Don't conflict with Cyrix config registers*/ - else - ret = dev->regs[dev->cur_reg]; + switch (addr) { + case 0x23: + /* Do not conflict with Cyrix configuration registers */ + if(!(((dev->index >= 0xc0) || (dev->index == 0x20)) && cpu_iscyrix)) + ret = dev->regs[dev->index]; + break; + } return ret; } @@ -123,21 +164,28 @@ ali1429_init(const device_t *info) ali1429_t *dev = (ali1429_t *) malloc(sizeof(ali1429_t)); memset(dev, 0, sizeof(ali1429_t)); - memset(dev->regs, 0xff, 256); - dev->regs[0x13] = dev->regs[0x14] = 0x00; - - io_sethandler(0x0022, 0x0002, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, dev); - - ali1429_recalc(dev); + /* + M1429 Ports: + 22h Index Port + 23h Data Port + */ + io_sethandler(0x022, 0x0001, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, dev); + io_sethandler(0x023, 0x0001, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, dev); + + dev->cfg_locked = 1; device_add(&port_92_device); + dev->regs[0x13] = 0x00; + dev->regs[0x14] = 0x00; + ali1429_shadow_recalc(dev); + return dev; } const device_t ali1429_device = { - "ALi-M1429", + "ALi M1429", 0, 0, ali1429_init, ali1429_close, NULL, diff --git a/src/chipset/ali1489.c b/src/chipset/ali1489.c new file mode 100644 index 000000000..5eb22d087 --- /dev/null +++ b/src/chipset/ali1489.c @@ -0,0 +1,541 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of the ALi M1489 chipset. + * + * + * + * Authors: Tiseno100 + * + * Copyright 2020 Tiseno100 + * + */ + +#include +#include +#include +#include +#include +#include +#define HAVE_STDARG_H +#include <86box/86box.h> +#include "cpu.h" +#include <86box/timer.h> +#include <86box/io.h> +#include <86box/device.h> +#include <86box/keyboard.h> +#include <86box/mem.h> +#include <86box/fdd.h> +#include <86box/fdc.h> +#include <86box/pci.h> +#include <86box/dma.h> +#include <86box/hdc_ide.h> +#include <86box/port_92.h> +#include <86box/chipset.h> + +#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY) +#define ENABLE_ALI1489_LOG 0 + +#ifdef ENABLE_ALI1489_LOG +int ali1489_do_log = ENABLE_ALI1489_LOG; +static void +ali1489_log(const char *fmt, ...) +{ + va_list ap; + + if (ali1489_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } +} +#else +#define ali1489_log(fmt, ...) +#endif + +typedef struct +{ + uint8_t index, ide_index, ide_chip_id, + regs[256], pci_conf[256], ide_regs[256]; + port_92_t * port_92; + +} ali1489_t; + +static void +ali1489_defaults(void *priv) +{ + ali1489_t *dev = (ali1489_t *) priv; + + /* IDE registers */ + dev->ide_regs[0x01] = 0x02; + dev->ide_regs[0x08] = 0xff; + dev->ide_regs[0x09] = 0x41; + dev->ide_regs[0x34] = 0xff; + dev->ide_regs[0x35] = 0x01; + + /* PCI registers */ + dev->pci_conf[0x00] = 0xb9; + dev->pci_conf[0x01] = 0x10; + dev->pci_conf[0x02] = 0x89; + dev->pci_conf[0x03] = 0x14; + dev->pci_conf[0x04] = 0x07; + dev->pci_conf[0x07] = 0x04; + dev->pci_conf[0x0b] = 0x06; + + /* ISA registers */ + dev->regs[0x01] = 0x0f; + dev->regs[0x02] = 0x0f; + dev->regs[0x10] = 0xf1; + dev->regs[0x11] = 0xff; + dev->regs[0x13] = 0x00; + dev->regs[0x14] = 0x00; + dev->regs[0x15] = 0x20; + dev->regs[0x16] = 0x30; + dev->regs[0x19] = 0x04; + dev->regs[0x21] = 0x72; + dev->regs[0x28] = 0x02; + dev->regs[0x2b] = 0xdb; + dev->regs[0x3c] = 0x03; + dev->regs[0x3d] = 0x01; + dev->regs[0x40] = 0x03; + +} + +static void ali1489_shadow_recalc(ali1489_t *dev) +{ + +uint32_t base, i; + + +for(i = 0; i < 8; i++){ + +base = 0xc0000 + (i << 14); +if(dev->regs[0x13] & (1 << i)) +mem_set_mem_state_both(base, 0x4000, ((dev->regs[0x14] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x14] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); +else +mem_set_mem_state_both(base, 0x4000, disabled_shadow); + +} + + +for(i = 0; i < 4; i++){ +base = 0xe0000 + (i << 15); + +shadowbios = (dev->regs[0x14] & 0x10); +shadowbios_write = (dev->regs[0x14] & 0x20); + +if(dev->regs[0x14] & (1 << i)) +mem_set_mem_state_both(base, 0x8000, ((dev->regs[0x14] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x14] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); +else +mem_set_mem_state_both(base, 0x8000, disabled_shadow); +} + +flushmmucache(); +} + +static void ali1489_smm_recalc(ali1489_t *dev) +{ + if((dev->regs[0x19] & 0x08) && (((dev->regs[0x19] & 0x03) << 4) != 0x00)) + { + if(((dev->regs[0x19] & 0x03) << 4) & 0x01) + { + mem_set_mem_state_smm(0xa0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + } + + if(((dev->regs[0x19] & 0x03) << 4) & 0x02) + { + mem_set_mem_state_smm(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + } + + if(((dev->regs[0x19] & 0x03) << 4) & 0x03) + { + mem_set_mem_state_smm(0x38000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + } + } +} + +static void +ali1489_write(uint16_t addr, uint8_t val, void *priv) +{ + ali1489_t *dev = (ali1489_t *) priv; + + switch (addr) { + case 0x22: + dev->index = val; + break; + case 0x23: + + dev->regs[dev->index] = val; + + if(dev->regs[0x03] == 0xc5) /* Check if the configuration registers are unlocked */ + { + switch(dev->index){ + + case 0x10: /* DRAM Configuration Register I */ + case 0x11: /* DRAM Configuration Register II */ + case 0x12: /* ROM Function Register */ + dev->regs[dev->index] = val; + break; + + case 0x13: /* Shadow Region Register */ + case 0x14: /* Shadow Control Register */ + + if(dev->index == 0x14) + dev->regs[dev->index] = (val & 0xbf); + else + { + dev->regs[dev->index] = val; + } + + ali1489_shadow_recalc(dev); + break; + + case 0x15: /* Cycle Check Point Control Register */ + dev->regs[dev->index] = (val & 0xf1); + break; + + case 0x16: /* Cache Control Register I */ + dev->regs[dev->index] = val; + cpu_cache_int_enabled = (val & 0x01); + cpu_cache_ext_enabled = (val & 0x02); + break; + + case 0x17: /* Cache Control Register II */ + dev->regs[dev->index] = val; + break; + + case 0x19: /* SMM Control Register */ + dev->regs[dev->index] = val; + ali1489_smm_recalc(dev); + break; + + case 0x1a: /* EDO DRAM Configuration Register */ + case 0x1b: /* DRAM Timing Control Register */ + case 0x1c: /* Memory Data Buffer Direction Control Register */ + dev->regs[dev->index] = val; + break; + + case 0x1e: /* Linear Wrapped Burst Order Mode Control Register */ + dev->regs[dev->index] = (val & 0x40); + break; + + case 0x20: /* CPU to PCI Buffer Control Register */ + case 0x21: /* DEVSELJ Check Point Setting Register */ + dev->regs[dev->index] = val; + break; + + case 0x22: /* PCI to CPU W/R Buffer Configuration Register */ + dev->regs[dev->index] = (val & 0xfd); + break; + + case 0x25: /* GP/MEM Address Definition Register I */ + case 0x26: /* GP/MEM Address Definition Register II */ + case 0x27: /* GP/MEM Address Definition Register III */ + case 0x28: /* PCI Arbiter Control Register */ + dev->regs[dev->index] = val; + break; + + case 0x29: /* System Clock Register */ + dev->regs[dev->index] = val; + + if(val & 0x10) + port_92_add(dev->port_92); + else + port_92_remove(dev->port_92); + break; + + case 0x2a: /* I/O Recovery Register */ + dev->regs[dev->index] = val; + break; + + case 0x2b: /* Turbo Function Register */ + dev->regs[dev->index] = (val & 0xbf); + break; + + case 0x30: /* Power Management Unit Control Register */ + case 0x31: /* Mode Timer Monitoring Events Selection Register I */ + case 0x32: /* Mode Timer Monitoring Events Selection Register II */ + case 0x33: /* SMI Triggered Events Selection Register I */ + case 0x34: /* SMI Triggered Events Selection Register II */ + case 0x35: /* SMI Status Register */ + dev->regs[dev->index] = val; + break; + + case 0x36: /* IRQ Channel Group Selected Control Register I */ + dev->regs[dev->index] = (val & 0xe5); + break; + + case 0x37: /* IRQ Channel Group Selected Control Register II */ + dev->regs[dev->index] = (val & 0xef); + break; + + case 0x38: /* DRQ Channel Selected Control Register */ + case 0x39: /* Mode Timer Setting Register */ + case 0x3a: /* Input_device Timer Setting Register */ + case 0x3b: /* GP/MEM Timer Setting Register */ + case 0x3c: /* LED Flash Control Register */ + dev->regs[dev->index] = val; + break; + + case 0x3d: /* Miscellaneous Register I */ + dev->regs[dev->index] = (val & 0x07); + break; + + case 0x3f: /* Shadow Port 70h Register */ + dev->regs[dev->index] = val; + break; + + case 0x40: /* Clock Generator Control Feature Register */ + dev->regs[dev->index] = (val & 0x3f); + break; + + case 0x41: /* Power Control Output Register */ + dev->regs[dev->index] = val; + break; + + case 0x42: /* PCI INTx Routing Table Mapping Register I */ + if((val & 0x0f) != 0) + pci_set_irq(PCI_INTA, (val & 0x0f)); + else + pci_set_irq(PCI_INTA, PCI_IRQ_DISABLED); + + if(((val & 0x0f) << 4) != 0) + pci_set_irq(PCI_INTB, ((val & 0x0f) << 4)); + else + pci_set_irq(PCI_INTB, PCI_IRQ_DISABLED); + break; + + case 0x43: /* PCI INTx Routing Table Mapping Register II */ + if((val & 0x0f) != 0) + pci_set_irq(PCI_INTC, (val & 0x0f)); + else + pci_set_irq(PCI_INTC, PCI_IRQ_DISABLED); + + if(((val & 0x0f) << 4) != 0) + pci_set_irq(PCI_INTD, ((val & 0x0f) << 4)); + else + pci_set_irq(PCI_INTD, PCI_IRQ_DISABLED); + break; + + case 0x44: /* PCI INTx Sensitivity Register */ + dev->regs[dev->index] = val; + break; + + } + + if(dev->index != 0x03) + { + ali1489_log("M1489: dev->regs[%02x] = %02x\n", dev->index, val); + } + + } + + break; + } +} + + +static uint8_t +ali1489_read(uint16_t addr, void *priv) +{ + uint8_t ret = 0xff; + ali1489_t *dev = (ali1489_t *) priv; + + switch (addr) { + case 0x23: + + if(((dev->index == 0x20) || (dev->index >= 0xc0)) && cpu_iscyrix) /* Avoid conflict with Cyrix CPU registers */ + ret = 0xff; + else + { + ret = dev->regs[dev->index]; + } + + break; + } + + return ret; +} + +static void +ali1489_pci_write(int func, int addr, uint8_t val, void *priv) +{ + +ali1489_t *dev = (ali1489_t *) priv; + +ali1489_log("M1489-PCI: dev->regs[%02x] = %02x\n", addr, val); + +switch (addr) +{ + /* Dummy PCI Config */ + case 0x04: + dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x07) | (val & 0x07); + break; + + /* Dummy PCI Status */ + case 0x07: + dev->pci_conf[0x07] = val; + break; +} + +} + +static uint8_t +ali1489_pci_read(int func, int addr, void *priv) +{ + ali1489_t *dev = (ali1489_t *) priv; + uint8_t ret = 0xff; + + ret = dev->pci_conf[addr]; + + return ret; +} + +static void +ali1489_ide_write(uint16_t addr, uint8_t val, void *priv) +{ + +ali1489_t *dev = (ali1489_t *) priv; + + switch (addr) { + case 0xf4: /* Usually it writes 30h here */ + dev->ide_chip_id = val; + break; + + case 0xf8: + dev->ide_index = val; + break; + + case 0xfc: + ali1489_log("M1489-IDE: dev->regs[%02x] = %02x\n", dev->ide_index, val); + dev->ide_regs[dev->ide_index] = val; + + ide_pri_disable(); + ide_sec_disable(); + + if(dev->ide_regs[0x01] & 0x01){ /*The datasheet doesn't clearly explain the channel selection */ + ide_pri_enable(); /*So we treat it according to the chipset programming manual. */ + ide_set_base(0, 0x1f0); + ide_set_side(0, 0x3f6); + + if(!(dev->ide_regs[0x35] & 0x41)){ + ide_sec_enable(); + ide_set_base(1, 0x170); + ide_set_side(1, 0x376); + } + + } + + break; + } + +} + +static uint8_t +ali1489_ide_read(uint16_t addr, void *priv) +{ + + uint8_t ret = 0xff; + ali1489_t *dev = (ali1489_t *) priv; + + switch (addr) { + case 0xf4: + ret = dev->ide_chip_id; + break; + case 0xfc: + ret = dev->ide_regs[dev->ide_index]; + break; + } + + return ret; +} + +static void +ali1489_reset(void *priv) +{ + +ali1489_t *dev = (ali1489_t *) priv; + +ide_pri_disable(); +ide_sec_disable(); + +pci_set_irq(PCI_INTA, PCI_IRQ_DISABLED); +pci_set_irq(PCI_INTB, PCI_IRQ_DISABLED); +pci_set_irq(PCI_INTC, PCI_IRQ_DISABLED); +pci_set_irq(PCI_INTD, PCI_IRQ_DISABLED); + +ali1489_defaults(dev); + +} + +static void +ali1489_close(void *priv) +{ + ali1489_t *dev = (ali1489_t *) priv; + + free(dev); +} + + +static void * +ali1489_init(const device_t *info) +{ + ali1489_t *dev = (ali1489_t *) malloc(sizeof(ali1489_t)); + memset(dev, 0, sizeof(ali1489_t)); + + /* + M1487/M1489 + 22h Index Port + 23h Data Port + */ + io_sethandler(0x022, 0x0001, ali1489_read, NULL, NULL, ali1489_write, NULL, NULL, dev); + io_sethandler(0x023, 0x0001, ali1489_read, NULL, NULL, ali1489_write, NULL, NULL, dev); + + /* + M1489 IDE controller + F4h Chip ID we write always 30h onto it + F8h Index Port + FCh Data Port + */ + io_sethandler(0x0f4, 0x0001, ali1489_ide_read, NULL, NULL, ali1489_ide_write, NULL, NULL, dev); + io_sethandler(0x0f8, 0x0001, ali1489_ide_read, NULL, NULL, ali1489_ide_write, NULL, NULL, dev); + io_sethandler(0x0fc, 0x0001, ali1489_ide_read, NULL, NULL, ali1489_ide_write, NULL, NULL, dev); + + /* Dummy M1489 PCI device */ + pci_add_card(0, ali1489_pci_read, ali1489_pci_write, dev); + + ide_pri_disable(); + ide_sec_disable(); + + dev->port_92 = device_add(&port_92_pci_device); + + pci_set_irq(PCI_INTA, PCI_IRQ_DISABLED); + pci_set_irq(PCI_INTB, PCI_IRQ_DISABLED); + pci_set_irq(PCI_INTC, PCI_IRQ_DISABLED); + pci_set_irq(PCI_INTD, PCI_IRQ_DISABLED); + + ali1489_defaults(dev); + + ali1489_shadow_recalc(dev); + + return dev; +} + + +const device_t ali1489_device = { + "ALi M1489", + 0, + 0, + ali1489_init, + ali1489_close, + ali1489_reset, + NULL, + NULL, + NULL, + NULL +}; diff --git a/src/include/86box/chipset.h b/src/include/86box/chipset.h index a5cf6e3ab..cddd86100 100644 --- a/src/include/86box/chipset.h +++ b/src/include/86box/chipset.h @@ -23,6 +23,9 @@ extern const device_t acc2168_device; /* ALi */ extern const device_t ali1429_device; +#if defined(DEV_BRANCH) && defined(USE_M1489) +extern const device_t ali1489_device; +#endif /* AMD */ extern const device_t amd640_device; diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index a6fa26573..76604b298 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -290,6 +290,9 @@ extern int machine_at_486ap4_init(const machine_t *); #if defined(DEV_BRANCH) && defined(NO_SIO) extern int machine_at_486vipio2_init(const machine_t *); #endif +#if defined(DEV_BRANCH) && defined(USE_M1489) +extern int machine_at_abpb4_init(const machine_t *); +#endif #if defined(DEV_BRANCH) && defined(USE_STPC) extern int machine_at_itoxstar_init(const machine_t *); extern int machine_at_arb1479_init(const machine_t *); @@ -370,6 +373,7 @@ extern int machine_at_p55va_init(const machine_t *); extern int machine_at_i430vx_init(const machine_t *); extern int machine_at_brio80xx_init(const machine_t *); extern int machine_at_8500tvxa_init(const machine_t *); +extern int machine_at_presario4500_init(const machine_t *); extern int machine_at_pb680_init(const machine_t *); extern int machine_at_nupro592_init(const machine_t *); diff --git a/src/machine/m_at_286_386sx.c b/src/machine/m_at_286_386sx.c index 202be5102..41f0650b0 100644 --- a/src/machine/m_at_286_386sx.c +++ b/src/machine/m_at_286_386sx.c @@ -152,7 +152,7 @@ machine_at_quadt286_init(const machine_t *model) if (bios_only || !ret) return ret; - machine_at_common_ide_init(model); + machine_at_common_init(model); device_add(&keyboard_at_device); device_add(&fdc_at_device); device_add(&headland_gc10x_device); diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index d30244343..474ff3e1d 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -342,7 +342,7 @@ machine_at_403tg_init(const machine_t *model) if (bios_only || !ret) return ret; - machine_at_common_ide_init(model); + machine_at_common_init(model); device_add(&opti895_device); @@ -704,6 +704,35 @@ machine_at_486vipio2_init(const machine_t *model) } #endif +#if defined(DEV_BRANCH) && defined(USE_M1489) +int +machine_at_abpb4_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/abpb4/486-AB-PB4.BIN", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2); + + device_add(&ali1489_device); + device_add(&ide_pci_2ch_device); + device_add(&w83787f_device); + device_add(&keyboard_at_device); + + return ret; +} +#endif + #if defined(DEV_BRANCH) && defined(USE_STPC) int machine_at_itoxstar_init(const machine_t *model) diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c index a029b717c..f7286d16a 100644 --- a/src/machine/m_at_socket7_s7.c +++ b/src/machine/m_at_socket7_s7.c @@ -657,6 +657,35 @@ machine_at_8500tvxa_init(const machine_t *model) return ret; } +int +machine_at_presario4500_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/presario4500/B013300I.ROM", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x14, PCI_CARD_ONBOARD, 4, 0, 0, 0); + + device_add(&i430vx_device); + device_add(&piix3_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&fdc37c931apm_device); + device_add(&intel_flash_bxt_device); + spd_register(SPD_TYPE_SDRAM, 0x01, 128); + + return ret; +} + int machine_at_pb680_init(const machine_t *model) { diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index c45795752..d1392aa08 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -149,7 +149,7 @@ const machine_t machines[] = { { "[SCAT] Samsung Deskmaster 286", "deskmaster286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_deskmaster286_init, NULL }, { "[GC103] Quadtel 286 clone", "quadt286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_quadt286_init, NULL }, { "[GC103] Trigem 286M", "tg286m", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_tg286m_init, NULL }, - { "[ISA] MR 286 clone", "mr286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_mr286_init, NULL }, + { "[ISA] MR 286 clone", "mr286", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 127, machine_at_mr286_init, NULL }, #if defined(DEV_BRANCH) && defined(USE_SIEMENS) { "[ISA] Siemens PCD-2L", "siemens", MACHINE_TYPE_286, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_siemens_init, NULL }, #endif @@ -170,8 +170,8 @@ const machine_t machines[] = { #endif { "[WD76C10] Amstrad MegaPC", "megapc", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1, 32, 1, 127, machine_at_wd76c10_init, NULL }, { "[SCAMP] Commodore SL386SX", "cbm_sl386sx25", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1024, 8192, 512, 127,machine_at_commodore_sl386sx_init, at_commodore_sl386sx_get_device }, - { "[NEAT] DTK 386SX clone", "dtk386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_neat_init, NULL }, - { "[NEAT] Goldstar 386", "goldstar386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_goldstar386_init, NULL }, + { "[NEAT] DTK 386SX clone", "dtk386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_neat_init, NULL }, + { "[NEAT] Goldstar 386", "goldstar386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_goldstar386_init, NULL }, { "[SCAT] KMX-C-02", "kmxc02", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL }, { "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL }, @@ -182,10 +182,10 @@ const machine_t machines[] = { { "[MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"IBM",cpus_IBM486SLC},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL }, /* 386DX machines */ - { "[ACC 2168] AMI 386DX clone", "acc386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 16384, 128, 127, machine_at_acc386_init, NULL }, - { "[SiS 310] ASUS ISA-386C", "asus386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 16384, 128, 127, machine_at_asus386_init, NULL }, + { "[ACC 2168] AMI 386DX clone", "acc386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 16384, 128, 127, machine_at_acc386_init, NULL }, + { "[SiS 310] ASUS ISA-386C", "asus386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 16384, 128, 127, machine_at_asus386_init, NULL }, { "[ISA] Compaq Portable III (386)", "portableiii386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 127, machine_at_portableiii386_init, at_cpqiii_get_device }, - { "[ISA] Micronics 386 clone", "micronics386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_micronics386_init, NULL }, + { "[ISA] Micronics 386 clone", "micronics386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_micronics386_init, NULL }, { "[C&T 386] ECS 386/32", "ecs386", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 1, 16, 1, 127, machine_at_ecs386_init, NULL }, /* 386DX machines which utilize the VLB bus */ @@ -236,6 +236,9 @@ const machine_t machines[] = { #if defined(DEV_BRANCH) && defined(NO_SIO) { "[VIA VT82C496G] FIC VIP-IO2", "486vipio2", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 255, machine_at_486vipio2_init, NULL }, #endif +#if defined(DEV_BRANCH) && defined(USE_M1489) + { "[ALi M1489] ABit AB-PB4", "abpb4", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 255, machine_at_abpb4_init, NULL }, +#endif #if defined(DEV_BRANCH) && defined(USE_STPC) { "[STPC Client] ITOX STAR", "itoxstar", MACHINE_TYPE_486, {{"ST", cpus_STPC6675}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_itoxstar_init, NULL }, { "[STPC Consumer-II] Acrosser AR-B1479", "arb1479", MACHINE_TYPE_486, {{"ST", cpus_STPC133}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 32, 160, 8, 255, machine_at_arb1479_init, NULL }, @@ -305,6 +308,7 @@ const machine_t machines[] = { { "[i430VX] Epox P55-VA", "p55va", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL }, { "[i430VX] HP Brio 80xx", "brio80xx", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_brio80xx_init, NULL }, { "[i430VX] Biostar MB-8500TVX-A", "8500tvxa", MACHINE_TYPE_SOCKET7, {{"Intel", cpus_Pentium}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_8500tvxa_init, NULL }, + { "[i430VX] Compaq Presario 4500", "presario4500", MACHINE_TYPE_SOCKET7, {{"Intel", cpus_Pentium}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_presario4500_init, NULL }, { "[i430VX] Packard Bell PB680", "pb680", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_pb680_init, NULL }, /* 430TX */ diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index e2281d55a..ea362b2b8 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -81,6 +81,9 @@ ifeq ($(DEV_BUILD), y) ifndef STPC STPC := y endif + ifndef M1489 + M1489 := y + endif ifndef VGAWONDER VGAWONDER := y endif @@ -160,6 +163,9 @@ else ifndef STPC STPC := y endif + ifndef M1489 + M1489 := n + endif ifndef VGAWONDER VGAWONDER := n endif @@ -563,6 +569,11 @@ OPTS += -DUSE_STPC DEVBROBJ += stpc.o endif +ifeq ($(M1489), y) +OPTS += -DUSE_M1489 +DEVBROBJ += ali1489.o +endif + ifeq ($(596B), y) OPTS += -DUSE_596B endif