diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c
index c156cf8e6..cf2901146 100644
--- a/src/chipset/intel_4x0.c
+++ b/src/chipset/intel_4x0.c
@@ -8,7 +8,7 @@
  *
  *		Implementation of the Intel PCISet chips from 420TX to 440FX.
  *
- * Version:	@(#)intel_4x0.c	1.0.1	2019/10/19
+ * Version:	@(#)intel_4x0.c	1.0.2	2019/10/21
  *
  * Authors:	Sarah Walker, <http://pcem-emulator.co.uk/>
  *		Miran Grca, <mgrca8@gmail.com>
@@ -21,6 +21,7 @@
 #include <string.h>
 #include <wchar.h>
 #include "../86box.h"
+#include "../cpu/cpu.h"
 #include "../mem.h"
 #include "../io.h"
 #include "../rom.h"
@@ -118,6 +119,17 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
 		}
 		break;
 
+	case 0x52: /*Cache Control Register*/
+#if defined(DEV_BRANCH) && defined(USE_I686)
+		if (dev->type < INTEL_440FX) {
+#endif
+			cpu_cache_ext_enabled = (val & 0x01);
+			cpu_update_waitstates();
+#if defined(DEV_BRANCH) && defined(USE_I686)
+		}
+#endif
+		break;
+
 	case 0x59: /*PAM0*/
 		if ((dev->regs[0x59] ^ val) & 0xf0) {
 			i4x0_map(0xf0000, 0x10000, val >> 4);
@@ -305,6 +317,13 @@ static void
     if (i4x0->type >= INTEL_430FX)
 	i4x0->regs[0x72] = 0x02;
 
+#if defined(DEV_BRANCH) && defined(USE_I686)
+    if (i4x0->type == INTEL_440FX) {
+	cpu_cache_ext_enabled = 1;
+	cpu_update_waitstates();
+    }
+#endif
+
     pci_add_card(0, i4x0_read, i4x0_write, i4x0);
 
     return i4x0;
diff --git a/src/chipset/sis_85c471.c b/src/chipset/sis_85c471.c
index 077a2d1e6..934e84c55 100644
--- a/src/chipset/sis_85c471.c
+++ b/src/chipset/sis_85c471.c
@@ -11,13 +11,11 @@
  *		SiS sis85c471 Super I/O Chip
  *		Used by DTK PKM-0038S E-2
  *
- * Version:	@(#)sis_85c471.c	1.0.1	2019/10/19
+ * Version:	@(#)sis_85c471.c	1.0.2	2019/10/21
  *
  * Authors:	Miran Grca, <mgrca8@gmail.com>
- *		Sarah Walker, <http://pcem-emulator.co.uk/>
  *
  *		Copyright 2019 Miran Grca.
- *		Copyright 2008-2019 Sarah Walker.
  */
 #include <stdio.h>
 #include <stdint.h>
@@ -25,6 +23,7 @@
 #include <string.h>
 #include <wchar.h>
 #include "../86box.h"
+#include "../cpu/cpu.h"
 #include "../mem.h"
 #include "../io.h"
 #include "../lpt.h"
@@ -95,6 +94,11 @@ sis_85c471_write(uint16_t port, uint8_t val, void *priv)
     }
 
     switch(dev->cur_reg) {
+	case 0x51:
+		cpu_cache_ext_enabled = ((val & 0x84) == 0x84);
+		cpu_update_waitstates();
+		break;
+
 	case 0x52:
 		sis_85c471_recalcmapping(dev);
 		break;
diff --git a/src/chipset/sis_85c496.c b/src/chipset/sis_85c496.c
index 07fc4e571..cddb74b9d 100644
--- a/src/chipset/sis_85c496.c
+++ b/src/chipset/sis_85c496.c
@@ -8,11 +8,12 @@
  *
  *		Implementation of the SiS 85c496/85c497 chip.
  *
- * Version:	@(#)sis_85c496.c	1.0.1	2019/10/19
+ * Version:	@(#)sis_85c496.c	1.0.2	2019/10/21
  *
  * Authors:	Sarah Walker, <http://pcem-emulator.co.uk/>
  *		Miran Grca, <mgrca8@gmail.com>
  *
+ *		Copyright 2008-2019 Sarah Walker.
  *		Copyright 2019 Miran Grca.
  */
 #include <stdio.h>
@@ -21,6 +22,7 @@
 #include <string.h>
 #include <wchar.h>
 #include "../86box.h"
+#include "../cpu/cpu.h"
 #include "../mem.h"
 #include "../io.h"
 #include "../rom.h"
@@ -121,6 +123,11 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
     valxor = old ^ val;
 
     switch (addr) {
+	case 0x42: /*Cache configure*/
+		cpu_cache_ext_enabled = (val & 0x01);
+		cpu_update_waitstates();
+		break;
+
 	case 0x44: /*Shadow configure*/
 		if (valxor & 0xff)
 			sis_85c496_recalcmapping(dev);