diff --git a/src/cpu/386_ops.h b/src/cpu/386_ops.h
index 299a95d9c..233e1cd58 100644
--- a/src/cpu/386_ops.h
+++ b/src/cpu/386_ops.h
@@ -8,7 +8,7 @@
*
* 286/386+ instruction handlers list.
*
- * Version: @(#)386_ops.h 1.0.2 2018/02/18
+ * Version: @(#)386_ops.h 1.0.3 2018/04/25
*
* Author: Sarah Walker,
* leilei,
@@ -147,6 +147,15 @@ static int ILLEGAL(uint32_t fetchdat)
return 0;
}
+#if defined(DEV_BRANCH) && (defined(USE_AMD_K) || defined(USE_I686))
+static int internal_illegal(char *s)
+{
+ cpu_state.pc = cpu_state.oldpc;
+ x86gpf(s, 0);
+ return cpu_state.abrt;
+}
+#endif
+
#include "x86seg.h"
#ifdef DEV_BRANCH
#ifdef USE_AMD_K
diff --git a/src/cpu/x86_ops_amd.h b/src/cpu/x86_ops_amd.h
index 969862a1f..acd7790ff 100644
--- a/src/cpu/x86_ops_amd.h
+++ b/src/cpu/x86_ops_amd.h
@@ -8,21 +8,12 @@
*
* AMD SYSCALL and SYSRET CPU Instructions.
*
- * Version: @(#)x86_ops_amd.h 1.0.2 2018/03/26
+ * Version: @(#)x86_ops_amd.h 1.0.3 2018/04/25
*
* Author: Miran Grca,
* Copyright 2016-2018 Miran Grca.
*/
-#ifndef internal_illegal
-static int internal_illegal(char *s)
-{
- cpu_state.pc = cpu_state.oldpc;
- x86gpf(s, 0);
- return cpu_state.abrt;
-}
-#endif
-
/* 0 = Limit 0-15
1 = Base 0-15
2 = Base 16-23 (bits 0-7), Access rights
diff --git a/src/cpu/x86_ops_i686.h b/src/cpu/x86_ops_i686.h
index 27317f061..d4418bfb4 100644
--- a/src/cpu/x86_ops_i686.h
+++ b/src/cpu/x86_ops_i686.h
@@ -8,21 +8,12 @@
*
* x86 i686 (Pentium Pro/Pentium II) CPU Instructions.
*
- * Version: @(#)x86_ops_i686.h 1.0.3 2018/03/26
+ * Version: @(#)x86_ops_i686.h 1.0.4 2018/04/25
*
* Author: Miran Grca,
* Copyright 2016-2018 Miran Grca.
*/
-#ifndef internal_illegal
-static int internal_illegal(char *s)
-{
- cpu_state.pc = cpu_state.oldpc;
- x86gpf(s, 0);
- return cpu_state.abrt;
-}
-#endif
-
/* 0 = Limit 0-15
1 = Base 0-15
2 = Base 16-23 (bits 0-7), Access rights